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gerrit-public.fairphone.software / kernel / msm-4.9 / 4f9ed545a33746864ee9f55bc0b601e09167dfc4 / . / arch / arm / mach-omap2 / powerdomain44xx.c
blob: aeac6f35ca10cf4e4709bd79d69801d4475286ac [file] [log] [blame]
Rajendra Nayakf327e072010-12-21 20:01:18 -0700[diff] [blame]1/*
2 * OMAP4 powerdomain control
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2007-2009 Nokia Corporation
6 *
7 * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
8 * Rajendra Nayak <rnayak@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/io.h>
16#include <linux/errno.h>
17#include <linux/delay.h>
Tony Lindgren4647ca52012-03-08 10:20:14 -0800[diff] [blame]18#include <linux/bug.h>
Paul Walmsley6e014782010-12-21 20:01:20 -0700[diff] [blame]19
Paul Walmsley72e06d02010-12-21 21:05:16 -0700[diff] [blame]20#include "powerdomain.h"
Rajendra Nayakf327e072010-12-21 20:01:18 -0700[diff] [blame]21#include <plat/prcm.h>
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]22#include "prm2xxx_3xxx.h"
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]23#include "prm44xx.h"
Paul Walmsleya64bb9c2010-12-21 21:05:14 -0700[diff] [blame]24#include "prminst44xx.h"
Rajendra Nayakf327e072010-12-21 20:01:18 -0700[diff] [blame]25#include "prm-regbits-44xx.h"
Rajendra Nayakf327e072010-12-21 20:01:18 -0700[diff] [blame]26
27static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
28{
Paul Walmsleya64bb9c2010-12-21 21:05:14 -0700[diff] [blame]29 omap4_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK,
30 (pwrst << OMAP_POWERSTATE_SHIFT),
31 pwrdm->prcm_partition,
32 pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
Rajendra Nayakf327e072010-12-21 20:01:18 -0700[diff] [blame]33 return 0;
34}
35
36static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
37{
Paul Walmsleya64bb9c2010-12-21 21:05:14 -0700[diff] [blame]38 u32 v;
39
40 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
41 OMAP4_PM_PWSTCTRL);
42 v &= OMAP_POWERSTATE_MASK;
43 v >>= OMAP_POWERSTATE_SHIFT;
44
45 return v;
Rajendra Nayakf327e072010-12-21 20:01:18 -0700[diff] [blame]46}
47
48static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm)
49{
Paul Walmsleya64bb9c2010-12-21 21:05:14 -0700[diff] [blame]50 u32 v;
51
52 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
53 OMAP4_PM_PWSTST);
54 v &= OMAP_POWERSTATEST_MASK;
55 v >>= OMAP_POWERSTATEST_SHIFT;
56
57 return v;
Rajendra Nayakf327e072010-12-21 20:01:18 -0700[diff] [blame]58}
59
60static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
61{
Paul Walmsleya64bb9c2010-12-21 21:05:14 -0700[diff] [blame]62 u32 v;
63
64 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
65 OMAP4_PM_PWSTST);
66 v &= OMAP4430_LASTPOWERSTATEENTERED_MASK;
67 v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT;
68
69 return v;
Rajendra Nayakf327e072010-12-21 20:01:18 -0700[diff] [blame]70}
71
Rajendra Nayak9b7fc902010-12-21 20:01:19 -0700[diff] [blame]72static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
73{
Paul Walmsleya64bb9c2010-12-21 21:05:14 -0700[diff] [blame]74 omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
75 (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
76 pwrdm->prcm_partition,
77 pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
Rajendra Nayak9b7fc902010-12-21 20:01:19 -0700[diff] [blame]78 return 0;
79}
80
Santosh Shilimkar4b4f62c2010-12-21 20:01:19 -0700[diff] [blame]81static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
82{
Paul Walmsleya64bb9c2010-12-21 21:05:14 -0700[diff] [blame]83 omap4_prminst_rmw_inst_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK,
84 OMAP4430_LASTPOWERSTATEENTERED_MASK,
85 pwrdm->prcm_partition,
86 pwrdm->prcm_offs, OMAP4_PM_PWSTST);
Santosh Shilimkar4b4f62c2010-12-21 20:01:19 -0700[diff] [blame]87 return 0;
88}
89
Rajendra Nayak12627572010-12-21 20:01:18 -0700[diff] [blame]90static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
91{
92 u32 v;
93
94 v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK);
Paul Walmsleya64bb9c2010-12-21 21:05:14 -0700[diff] [blame]95 omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v,
96 pwrdm->prcm_partition, pwrdm->prcm_offs,
97 OMAP4_PM_PWSTCTRL);
Rajendra Nayak12627572010-12-21 20:01:18 -0700[diff] [blame]98
99 return 0;
100}
101
Rajendra Nayak9b7fc902010-12-21 20:01:19 -0700[diff] [blame]102static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
Paul Walmsleya64bb9c2010-12-21 21:05:14 -0700[diff] [blame]103 u8 pwrst)
Rajendra Nayak9b7fc902010-12-21 20:01:19 -0700[diff] [blame]104{
105 u32 m;
106
107 m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
108
Paul Walmsleya64bb9c2010-12-21 21:05:14 -0700[diff] [blame]109 omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
110 pwrdm->prcm_partition, pwrdm->prcm_offs,
111 OMAP4_PM_PWSTCTRL);
Rajendra Nayak9b7fc902010-12-21 20:01:19 -0700[diff] [blame]112
113 return 0;
114}
115
116static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
Paul Walmsleya64bb9c2010-12-21 21:05:14 -0700[diff] [blame]117 u8 pwrst)
Rajendra Nayak9b7fc902010-12-21 20:01:19 -0700[diff] [blame]118{
119 u32 m;
120
121 m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
122
Paul Walmsleya64bb9c2010-12-21 21:05:14 -0700[diff] [blame]123 omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
124 pwrdm->prcm_partition, pwrdm->prcm_offs,
125 OMAP4_PM_PWSTCTRL);
Rajendra Nayak9b7fc902010-12-21 20:01:19 -0700[diff] [blame]126
127 return 0;
128}
129
Rajendra Nayak12627572010-12-21 20:01:18 -0700[diff] [blame]130static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
131{
Paul Walmsleya64bb9c2010-12-21 21:05:14 -0700[diff] [blame]132 u32 v;
133
134 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
135 OMAP4_PM_PWSTST);
136 v &= OMAP4430_LOGICSTATEST_MASK;
137 v >>= OMAP4430_LOGICSTATEST_SHIFT;
138
139 return v;
Rajendra Nayak12627572010-12-21 20:01:18 -0700[diff] [blame]140}
141
142static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
143{
Paul Walmsleya64bb9c2010-12-21 21:05:14 -0700[diff] [blame]144 u32 v;
145
146 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
147 OMAP4_PM_PWSTCTRL);
148 v &= OMAP4430_LOGICRETSTATE_MASK;
149 v >>= OMAP4430_LOGICRETSTATE_SHIFT;
150
151 return v;
Rajendra Nayak12627572010-12-21 20:01:18 -0700[diff] [blame]152}
153
Rajendra Nayak9b7fc902010-12-21 20:01:19 -0700[diff] [blame]154static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
155{
Paul Walmsleya64bb9c2010-12-21 21:05:14 -0700[diff] [blame]156 u32 m, v;
Rajendra Nayak9b7fc902010-12-21 20:01:19 -0700[diff] [blame]157
158 m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
159
Paul Walmsleya64bb9c2010-12-21 21:05:14 -0700[diff] [blame]160 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
161 OMAP4_PM_PWSTST);
162 v &= m;
163 v >>= __ffs(m);
164
165 return v;
Rajendra Nayak9b7fc902010-12-21 20:01:19 -0700[diff] [blame]166}
167
168static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
169{
Paul Walmsleya64bb9c2010-12-21 21:05:14 -0700[diff] [blame]170 u32 m, v;
Rajendra Nayak9b7fc902010-12-21 20:01:19 -0700[diff] [blame]171
172 m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
173
Paul Walmsleya64bb9c2010-12-21 21:05:14 -0700[diff] [blame]174 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
175 OMAP4_PM_PWSTCTRL);
176 v &= m;
177 v >>= __ffs(m);
178
179 return v;
Rajendra Nayak9b7fc902010-12-21 20:01:19 -0700[diff] [blame]180}
181
182static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
183{
184 u32 c = 0;
185
186 /*
187 * REVISIT: pwrdm_wait_transition() may be better implemented
188 * via a callback and a periodic timer check -- how long do we expect
189 * powerdomain transitions to take?
190 */
191
192 /* XXX Is this udelay() value meaningful? */
Paul Walmsleya64bb9c2010-12-21 21:05:14 -0700[diff] [blame]193 while ((omap4_prminst_read_inst_reg(pwrdm->prcm_partition,
194 pwrdm->prcm_offs,
195 OMAP4_PM_PWSTST) &
Rajendra Nayak9b7fc902010-12-21 20:01:19 -0700[diff] [blame]196 OMAP_INTRANSITION_MASK) &&
Paul Walmsleya64bb9c2010-12-21 21:05:14 -0700[diff] [blame]197 (c++ < PWRDM_TRANSITION_BAILOUT))
198 udelay(1);
Rajendra Nayak9b7fc902010-12-21 20:01:19 -0700[diff] [blame]199
200 if (c > PWRDM_TRANSITION_BAILOUT) {
Paul Walmsley7852ec02012-07-26 00:54:26 -0600[diff] [blame]201 pr_err("powerdomain: %s: waited too long to complete transition\n",
202 pwrdm->name);
Rajendra Nayak9b7fc902010-12-21 20:01:19 -0700[diff] [blame]203 return -EAGAIN;
204 }
205
206 pr_debug("powerdomain: completed transition in %d loops\n", c);
207
208 return 0;
209}
210
Rajendra Nayakf327e072010-12-21 20:01:18 -0700[diff] [blame]211struct pwrdm_ops omap4_pwrdm_operations = {
212 .pwrdm_set_next_pwrst = omap4_pwrdm_set_next_pwrst,
213 .pwrdm_read_next_pwrst = omap4_pwrdm_read_next_pwrst,
214 .pwrdm_read_pwrst = omap4_pwrdm_read_pwrst,
215 .pwrdm_read_prev_pwrst = omap4_pwrdm_read_prev_pwrst,
Rajendra Nayak9b7fc902010-12-21 20:01:19 -0700[diff] [blame]216 .pwrdm_set_lowpwrstchange = omap4_pwrdm_set_lowpwrstchange,
Santosh Shilimkar4b4f62c2010-12-21 20:01:19 -0700[diff] [blame]217 .pwrdm_clear_all_prev_pwrst = omap4_pwrdm_clear_all_prev_pwrst,
Rajendra Nayak12627572010-12-21 20:01:18 -0700[diff] [blame]218 .pwrdm_set_logic_retst = omap4_pwrdm_set_logic_retst,
219 .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst,
220 .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst,
Rajendra Nayak9b7fc902010-12-21 20:01:19 -0700[diff] [blame]221 .pwrdm_read_mem_pwrst = omap4_pwrdm_read_mem_pwrst,
222 .pwrdm_read_mem_retst = omap4_pwrdm_read_mem_retst,
223 .pwrdm_set_mem_onst = omap4_pwrdm_set_mem_onst,
224 .pwrdm_set_mem_retst = omap4_pwrdm_set_mem_retst,
225 .pwrdm_wait_transition = omap4_pwrdm_wait_transition,
Rajendra Nayakf327e072010-12-21 20:01:18 -0700[diff] [blame]226};