blob: 0221b5c20e8739bb511754869e0ea477990f4ad3 [file] [log] [blame]
Vaibhav Hiremathddd04b92012-06-18 00:47:26 -06001/*
2 * AM33XX PRM_XXX register bits
3 *
4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
17#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
18
19#include "prm.h"
20
21/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
22#define AM33XX_ABBOFF_ACT_EXPORT_SHIFT 1
23#define AM33XX_ABBOFF_ACT_EXPORT_MASK (1 << 1)
24
25/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
26#define AM33XX_ABBOFF_SLEEP_EXPORT_SHIFT 2
27#define AM33XX_ABBOFF_SLEEP_EXPORT_MASK (1 << 2)
28
29/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
30#define AM33XX_AIPOFF_SHIFT 8
31#define AM33XX_AIPOFF_MASK (1 << 8)
32
33/* Used by PM_WKUP_PWRSTST */
34#define AM33XX_DEBUGSS_MEM_STATEST_SHIFT 17
35#define AM33XX_DEBUGSS_MEM_STATEST_MASK (0x3 << 17)
36
37/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
38#define AM33XX_DISABLE_RTA_EXPORT_SHIFT 0
39#define AM33XX_DISABLE_RTA_EXPORT_MASK (1 << 0)
40
41/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
42#define AM33XX_DPLL_CORE_RECAL_EN_SHIFT 12
43#define AM33XX_DPLL_CORE_RECAL_EN_MASK (1 << 12)
44
45/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
46#define AM33XX_DPLL_CORE_RECAL_ST_SHIFT 12
47#define AM33XX_DPLL_CORE_RECAL_ST_MASK (1 << 12)
48
49/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
50#define AM33XX_DPLL_DDR_RECAL_EN_SHIFT 14
51#define AM33XX_DPLL_DDR_RECAL_EN_MASK (1 << 14)
52
53/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
54#define AM33XX_DPLL_DDR_RECAL_ST_SHIFT 14
55#define AM33XX_DPLL_DDR_RECAL_ST_MASK (1 << 14)
56
57/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
58#define AM33XX_DPLL_DISP_RECAL_EN_SHIFT 15
59#define AM33XX_DPLL_DISP_RECAL_EN_MASK (1 << 15)
60
61/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
62#define AM33XX_DPLL_DISP_RECAL_ST_SHIFT 13
63#define AM33XX_DPLL_DISP_RECAL_ST_MASK (1 << 13)
64
65/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
66#define AM33XX_DPLL_MPU_RECAL_EN_SHIFT 11
67#define AM33XX_DPLL_MPU_RECAL_EN_MASK (1 << 11)
68
69/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
70#define AM33XX_DPLL_MPU_RECAL_ST_SHIFT 11
71#define AM33XX_DPLL_MPU_RECAL_ST_MASK (1 << 11)
72
73/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
74#define AM33XX_DPLL_PER_RECAL_EN_SHIFT 13
75#define AM33XX_DPLL_PER_RECAL_EN_MASK (1 << 13)
76
77/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
78#define AM33XX_DPLL_PER_RECAL_ST_SHIFT 15
79#define AM33XX_DPLL_PER_RECAL_ST_MASK (1 << 15)
80
81/* Used by RM_WKUP_RSTST */
82#define AM33XX_EMULATION_M3_RST_SHIFT 6
83#define AM33XX_EMULATION_M3_RST_MASK (1 << 6)
84
85/* Used by RM_MPU_RSTST */
86#define AM33XX_EMULATION_MPU_RST_SHIFT 5
87#define AM33XX_EMULATION_MPU_RST_MASK (1 << 5)
88
89/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
90#define AM33XX_ENFUNC1_EXPORT_SHIFT 3
91#define AM33XX_ENFUNC1_EXPORT_MASK (1 << 3)
92
93/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
94#define AM33XX_ENFUNC3_EXPORT_SHIFT 5
95#define AM33XX_ENFUNC3_EXPORT_MASK (1 << 5)
96
97/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
98#define AM33XX_ENFUNC4_SHIFT 6
99#define AM33XX_ENFUNC4_MASK (1 << 6)
100
101/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
102#define AM33XX_ENFUNC5_SHIFT 7
103#define AM33XX_ENFUNC5_MASK (1 << 7)
104
105/* Used by PRM_RSTST */
106#define AM33XX_EXTERNAL_WARM_RST_SHIFT 5
107#define AM33XX_EXTERNAL_WARM_RST_MASK (1 << 5)
108
109/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
110#define AM33XX_FORCEWKUP_EN_SHIFT 10
111#define AM33XX_FORCEWKUP_EN_MASK (1 << 10)
112
113/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
114#define AM33XX_FORCEWKUP_ST_SHIFT 10
115#define AM33XX_FORCEWKUP_ST_MASK (1 << 10)
116
117/* Used by PM_GFX_PWRSTCTRL */
118#define AM33XX_GFX_MEM_ONSTATE_SHIFT 17
119#define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17)
120
121/* Used by PM_GFX_PWRSTCTRL */
122#define AM33XX_GFX_MEM_RETSTATE_SHIFT 6
123#define AM33XX_GFX_MEM_RETSTATE_MASK (1 << 6)
124
125/* Used by PM_GFX_PWRSTST */
126#define AM33XX_GFX_MEM_STATEST_SHIFT 4
127#define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4)
128
129/* Used by RM_GFX_RSTCTRL, RM_GFX_RSTST */
130#define AM33XX_GFX_RST_SHIFT 0
131#define AM33XX_GFX_RST_MASK (1 << 0)
132
133/* Used by PRM_RSTST */
134#define AM33XX_GLOBAL_COLD_RST_SHIFT 0
135#define AM33XX_GLOBAL_COLD_RST_MASK (1 << 0)
136
137/* Used by PRM_RSTST */
138#define AM33XX_GLOBAL_WARM_SW_RST_SHIFT 1
139#define AM33XX_GLOBAL_WARM_SW_RST_MASK (1 << 1)
140
141/* Used by RM_WKUP_RSTST */
142#define AM33XX_ICECRUSHER_M3_RST_SHIFT 7
143#define AM33XX_ICECRUSHER_M3_RST_MASK (1 << 7)
144
145/* Used by RM_MPU_RSTST */
146#define AM33XX_ICECRUSHER_MPU_RST_SHIFT 6
147#define AM33XX_ICECRUSHER_MPU_RST_MASK (1 << 6)
148
149/* Used by PRM_RSTST */
150#define AM33XX_ICEPICK_RST_SHIFT 9
151#define AM33XX_ICEPICK_RST_MASK (1 << 9)
152
153/* Used by RM_PER_RSTCTRL */
154#define AM33XX_PRUSS_LRST_SHIFT 1
155#define AM33XX_PRUSS_LRST_MASK (1 << 1)
156
157/* Used by PM_PER_PWRSTCTRL */
158#define AM33XX_PRUSS_MEM_ONSTATE_SHIFT 5
159#define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5)
160
161/* Used by PM_PER_PWRSTCTRL */
162#define AM33XX_PRUSS_MEM_RETSTATE_SHIFT 7
163#define AM33XX_PRUSS_MEM_RETSTATE_MASK (1 << 7)
164
165/* Used by PM_PER_PWRSTST */
166#define AM33XX_PRUSS_MEM_STATEST_SHIFT 23
167#define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23)
168
169/*
170 * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
171 * PM_WKUP_PWRSTST, PM_RTC_PWRSTST
172 */
173#define AM33XX_INTRANSITION_SHIFT 20
174#define AM33XX_INTRANSITION_MASK (1 << 20)
175
176/* Used by PM_CEFUSE_PWRSTST */
177#define AM33XX_LASTPOWERSTATEENTERED_SHIFT 24
178#define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24)
179
180/* Used by PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_RTC_PWRSTCTRL */
181#define AM33XX_LOGICRETSTATE_SHIFT 2
182#define AM33XX_LOGICRETSTATE_MASK (1 << 2)
183
184/* Renamed from LOGICRETSTATE Used by PM_PER_PWRSTCTRL, PM_WKUP_PWRSTCTRL */
185#define AM33XX_LOGICRETSTATE_3_3_SHIFT 3
186#define AM33XX_LOGICRETSTATE_3_3_MASK (1 << 3)
187
188/*
189 * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
190 * PM_WKUP_PWRSTST, PM_RTC_PWRSTST
191 */
192#define AM33XX_LOGICSTATEST_SHIFT 2
193#define AM33XX_LOGICSTATEST_MASK (1 << 2)
194
195/*
196 * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
197 * PM_MPU_PWRSTCTRL, PM_WKUP_PWRSTCTRL, PM_RTC_PWRSTCTRL
198 */
199#define AM33XX_LOWPOWERSTATECHANGE_SHIFT 4
200#define AM33XX_LOWPOWERSTATECHANGE_MASK (1 << 4)
201
202/* Used by PM_MPU_PWRSTCTRL */
203#define AM33XX_MPU_L1_ONSTATE_SHIFT 18
204#define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18)
205
206/* Used by PM_MPU_PWRSTCTRL */
207#define AM33XX_MPU_L1_RETSTATE_SHIFT 22
208#define AM33XX_MPU_L1_RETSTATE_MASK (1 << 22)
209
210/* Used by PM_MPU_PWRSTST */
211#define AM33XX_MPU_L1_STATEST_SHIFT 6
212#define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6)
213
214/* Used by PM_MPU_PWRSTCTRL */
215#define AM33XX_MPU_L2_ONSTATE_SHIFT 20
216#define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20)
217
218/* Used by PM_MPU_PWRSTCTRL */
219#define AM33XX_MPU_L2_RETSTATE_SHIFT 23
220#define AM33XX_MPU_L2_RETSTATE_MASK (1 << 23)
221
222/* Used by PM_MPU_PWRSTST */
223#define AM33XX_MPU_L2_STATEST_SHIFT 8
224#define AM33XX_MPU_L2_STATEST_MASK (0x3 << 8)
225
226/* Used by PM_MPU_PWRSTCTRL */
227#define AM33XX_MPU_RAM_ONSTATE_SHIFT 16
228#define AM33XX_MPU_RAM_ONSTATE_MASK (0x3 << 16)
229
230/* Used by PM_MPU_PWRSTCTRL */
231#define AM33XX_MPU_RAM_RETSTATE_SHIFT 24
232#define AM33XX_MPU_RAM_RETSTATE_MASK (1 << 24)
233
234/* Used by PM_MPU_PWRSTST */
235#define AM33XX_MPU_RAM_STATEST_SHIFT 4
236#define AM33XX_MPU_RAM_STATEST_MASK (0x3 << 4)
237
238/* Used by PRM_RSTST */
239#define AM33XX_MPU_SECURITY_VIOL_RST_SHIFT 2
240#define AM33XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2)
241
242/* Used by PRM_SRAM_COUNT */
243#define AM33XX_PCHARGECNT_VALUE_SHIFT 0
244#define AM33XX_PCHARGECNT_VALUE_MASK (0x3f << 0)
245
246/* Used by RM_PER_RSTCTRL */
247#define AM33XX_PCI_LRST_SHIFT 0
248#define AM33XX_PCI_LRST_MASK (1 << 0)
249
250/* Renamed from PCI_LRST Used by RM_PER_RSTST */
251#define AM33XX_PCI_LRST_5_5_SHIFT 5
252#define AM33XX_PCI_LRST_5_5_MASK (1 << 5)
253
254/* Used by PM_PER_PWRSTCTRL */
255#define AM33XX_PER_MEM_ONSTATE_SHIFT 25
256#define AM33XX_PER_MEM_ONSTATE_MASK (0x3 << 25)
257
258/* Used by PM_PER_PWRSTCTRL */
259#define AM33XX_PER_MEM_RETSTATE_SHIFT 29
260#define AM33XX_PER_MEM_RETSTATE_MASK (1 << 29)
261
262/* Used by PM_PER_PWRSTST */
263#define AM33XX_PER_MEM_STATEST_SHIFT 17
264#define AM33XX_PER_MEM_STATEST_MASK (0x3 << 17)
265
266/*
267 * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
268 * PM_MPU_PWRSTCTRL
269 */
270#define AM33XX_POWERSTATE_SHIFT 0
271#define AM33XX_POWERSTATE_MASK (0x3 << 0)
272
273/* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST */
274#define AM33XX_POWERSTATEST_SHIFT 0
275#define AM33XX_POWERSTATEST_MASK (0x3 << 0)
276
277/* Used by PM_PER_PWRSTCTRL */
278#define AM33XX_RAM_MEM_ONSTATE_SHIFT 30
279#define AM33XX_RAM_MEM_ONSTATE_MASK (0x3 << 30)
280
281/* Used by PM_PER_PWRSTCTRL */
282#define AM33XX_RAM_MEM_RETSTATE_SHIFT 27
283#define AM33XX_RAM_MEM_RETSTATE_MASK (1 << 27)
284
285/* Used by PM_PER_PWRSTST */
286#define AM33XX_RAM_MEM_STATEST_SHIFT 21
287#define AM33XX_RAM_MEM_STATEST_MASK (0x3 << 21)
288
289/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
290#define AM33XX_RETMODE_ENABLE_SHIFT 0
291#define AM33XX_RETMODE_ENABLE_MASK (1 << 0)
292
293/* Used by REVISION_PRM */
294#define AM33XX_REV_SHIFT 0
295#define AM33XX_REV_MASK (0xff << 0)
296
297/* Used by PRM_RSTTIME */
298#define AM33XX_RSTTIME1_SHIFT 0
299#define AM33XX_RSTTIME1_MASK (0xff << 0)
300
301/* Used by PRM_RSTTIME */
302#define AM33XX_RSTTIME2_SHIFT 8
303#define AM33XX_RSTTIME2_MASK (0x1f << 8)
304
305/* Used by PRM_RSTCTRL */
306#define AM33XX_RST_GLOBAL_COLD_SW_SHIFT 1
307#define AM33XX_RST_GLOBAL_COLD_SW_MASK (1 << 1)
308
309/* Used by PRM_RSTCTRL */
310#define AM33XX_RST_GLOBAL_WARM_SW_SHIFT 0
311#define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0)
312
313/* Used by PRM_SRAM_COUNT */
314#define AM33XX_SLPCNT_VALUE_SHIFT 16
315#define AM33XX_SLPCNT_VALUE_MASK (0xff << 16)
316
317/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
318#define AM33XX_SRAMLDO_STATUS_SHIFT 8
319#define AM33XX_SRAMLDO_STATUS_MASK (1 << 8)
320
321/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
322#define AM33XX_SRAM_IN_TRANSITION_SHIFT 9
323#define AM33XX_SRAM_IN_TRANSITION_MASK (1 << 9)
324
325/* Used by PRM_SRAM_COUNT */
326#define AM33XX_STARTUP_COUNT_SHIFT 24
327#define AM33XX_STARTUP_COUNT_MASK (0xff << 24)
328
329/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
330#define AM33XX_TRANSITION_EN_SHIFT 8
331#define AM33XX_TRANSITION_EN_MASK (1 << 8)
332
333/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
334#define AM33XX_TRANSITION_ST_SHIFT 8
335#define AM33XX_TRANSITION_ST_MASK (1 << 8)
336
337/* Used by PRM_SRAM_COUNT */
338#define AM33XX_VSETUPCNT_VALUE_SHIFT 8
339#define AM33XX_VSETUPCNT_VALUE_MASK (0xff << 8)
340
341/* Used by PRM_RSTST */
342#define AM33XX_WDT0_RST_SHIFT 3
343#define AM33XX_WDT0_RST_MASK (1 << 3)
344
345/* Used by PRM_RSTST */
346#define AM33XX_WDT1_RST_SHIFT 4
347#define AM33XX_WDT1_RST_MASK (1 << 4)
348
349/* Used by RM_WKUP_RSTCTRL */
350#define AM33XX_WKUP_M3_LRST_SHIFT 3
351#define AM33XX_WKUP_M3_LRST_MASK (1 << 3)
352
353/* Renamed from WKUP_M3_LRST Used by RM_WKUP_RSTST */
354#define AM33XX_WKUP_M3_LRST_5_5_SHIFT 5
355#define AM33XX_WKUP_M3_LRST_5_5_MASK (1 << 5)
356
357#endif