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gerrit-public.fairphone.software / kernel / msm-4.9 / 4f9ed545a33746864ee9f55bc0b601e09167dfc4 / . / arch / arm / mach-omap2 / prm.h
blob: 39d562169d185d11a3a3d5aebcaa541754423dea [file] [log] [blame]
Paul Walmsley69d88a02008-03-18 10:02:50 +0200[diff] [blame]1/*
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]2 * OMAP2/3/4 Power/Reset Management (PRM) bitfield definitions
Paul Walmsley69d88a02008-03-18 10:02:50 +0200[diff] [blame]3 *
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]4 * Copyright (C) 2007-2009 Texas Instruments, Inc.
Benoît Cousson0be16212010-09-21 10:34:10 -0600[diff] [blame]5 * Copyright (C) 2010 Nokia Corporation
Paul Walmsley69d88a02008-03-18 10:02:50 +0200[diff] [blame]6 *
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]7 * Paul Walmsley
Paul Walmsley69d88a02008-03-18 10:02:50 +0200[diff] [blame]8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]13#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
14#define __ARCH_ARM_MACH_OMAP2_PRM_H
Paul Walmsley69d88a02008-03-18 10:02:50 +0200[diff] [blame]15
16#include "prcm-common.h"
17
Paul Walmsley69d88a02008-03-18 10:02:50 +0200[diff] [blame]18/*
19 * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
20 *
21 * 2430: PM_PWSTST_MDM
22 *
23 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
24 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
25 * PM_PWSTST_NEON
26 */
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600[diff] [blame]27#define OMAP_INTRANSITION_MASK (1 << 20)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200[diff] [blame]28
29
30/*
31 * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
32 *
33 * 2430: PM_PWSTST_MDM
34 *
35 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
36 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
37 * PM_PWSTST_NEON
38 */
39#define OMAP_POWERSTATEST_SHIFT 0
40#define OMAP_POWERSTATEST_MASK (0x3 << 0)
41
42/*
Paul Walmsley69d88a02008-03-18 10:02:50 +0200[diff] [blame]43 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
44 * PM_PWSTCTRL_DSP, PM_PWSTST_MPU
45 *
46 * 2430: PM_PWSTCTRL_MDM shared bits
47 *
48 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
49 * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
50 * PM_PWSTCTRL_NEON shared bits
51 */
52#define OMAP_POWERSTATE_SHIFT 0
53#define OMAP_POWERSTATE_MASK (0x3 << 0)
54
55
Paul Walmsley69d88a02008-03-18 10:02:50 +0200[diff] [blame]56#endif