blob: e7dbb6cf1255dd077aca1a4965dc9f59f659de24 [file] [log] [blame]
Vaibhav Hiremathddd04b92012-06-18 00:47:26 -06001/*
2 * AM33XX PRM functions
3 *
4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/errno.h>
19#include <linux/err.h>
20#include <linux/io.h>
21
22#include <plat/common.h>
23
24#include "common.h"
25#include "prm33xx.h"
26#include "prm-regbits-33xx.h"
27
28/* Read a register in a PRM instance */
29u32 am33xx_prm_read_reg(s16 inst, u16 idx)
30{
31 return __raw_readl(prm_base + inst + idx);
32}
33
34/* Write into a register in a PRM instance */
35void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx)
36{
37 __raw_writel(val, prm_base + inst + idx);
38}
39
40/* Read-modify-write a register in PRM. Caller must lock */
41u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
42{
43 u32 v;
44
45 v = am33xx_prm_read_reg(inst, idx);
46 v &= ~mask;
47 v |= bits;
48 am33xx_prm_write_reg(v, inst, idx);
49
50 return v;
51}
52
53/**
54 * am33xx_prm_is_hardreset_asserted - read the HW reset line state of
55 * submodules contained in the hwmod module
56 * @shift: register bit shift corresponding to the reset line to check
57 * @inst: CM instance register offset (*_INST macro)
58 * @rstctrl_offs: RM_RSTCTRL register address offset for this module
59 *
60 * Returns 1 if the (sub)module hardreset line is currently asserted,
61 * 0 if the (sub)module hardreset line is not currently asserted, or
62 * -EINVAL upon parameter error.
63 */
64int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, u16 rstctrl_offs)
65{
66 u32 v;
67
68 v = am33xx_prm_read_reg(inst, rstctrl_offs);
69 v &= 1 << shift;
70 v >>= shift;
71
72 return v;
73}
74
75/**
76 * am33xx_prm_assert_hardreset - assert the HW reset line of a submodule
77 * @shift: register bit shift corresponding to the reset line to assert
78 * @inst: CM instance register offset (*_INST macro)
79 * @rstctrl_reg: RM_RSTCTRL register address for this module
80 *
81 * Some IPs like dsp, ipu or iva contain processors that require an HW
82 * reset line to be asserted / deasserted in order to fully enable the
83 * IP. These modules may have multiple hard-reset lines that reset
84 * different 'submodules' inside the IP block. This function will
85 * place the submodule into reset. Returns 0 upon success or -EINVAL
86 * upon an argument error.
87 */
88int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs)
89{
90 u32 mask = 1 << shift;
91
92 am33xx_prm_rmw_reg_bits(mask, mask, inst, rstctrl_offs);
93
94 return 0;
95}
96
97/**
98 * am33xx_prm_deassert_hardreset - deassert a submodule hardreset line and
99 * wait
100 * @shift: register bit shift corresponding to the reset line to deassert
101 * @inst: CM instance register offset (*_INST macro)
102 * @rstctrl_reg: RM_RSTCTRL register address for this module
103 * @rstst_reg: RM_RSTST register address for this module
104 *
105 * Some IPs like dsp, ipu or iva contain processors that require an HW
106 * reset line to be asserted / deasserted in order to fully enable the
107 * IP. These modules may have multiple hard-reset lines that reset
108 * different 'submodules' inside the IP block. This function will
109 * take the submodule out of reset and wait until the PRCM indicates
110 * that the reset has completed before returning. Returns 0 upon success or
111 * -EINVAL upon an argument error, -EEXIST if the submodule was already out
112 * of reset, or -EBUSY if the submodule did not exit reset promptly.
113 */
114int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
115 u16 rstctrl_offs, u16 rstst_offs)
116{
117 int c;
118 u32 mask = 1 << shift;
119
120 /* Check the current status to avoid de-asserting the line twice */
121 if (am33xx_prm_is_hardreset_asserted(shift, inst, rstctrl_offs) == 0)
122 return -EEXIST;
123
124 /* Clear the reset status by writing 1 to the status bit */
125 am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs);
126 /* de-assert the reset control line */
127 am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);
128 /* wait the status to be set */
129
130 omap_test_timeout(am33xx_prm_is_hardreset_asserted(shift, inst,
131 rstst_offs),
132 MAX_MODULE_HARDRESET_WAIT, c);
133
134 return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
135}