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gerrit-public.fairphone.software / kernel / msm-4.9 / 4fa78825797e32edc7f878d0366a925b2d1e9e9b / . / arch / arm64 / boot / dts / qcom / sdm845-sde-display.dtsi
blob: 2ff9b2f03dc01601b2345cb82a00391ad107dbe8 [file] [log] [blame]
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]1/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]13#include "dsi-panel-sim-video.dtsi"
14#include "dsi-panel-sim-cmd.dtsi"
15#include "dsi-panel-sim-dualmipi-video.dtsi"
16#include "dsi-panel-sim-dualmipi-cmd.dtsi"
17#include "dsi-panel-sharp-dsc-4k-video.dtsi"
18#include "dsi-panel-sharp-dsc-4k-cmd.dtsi"
19#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi"
20#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi"
21#include "dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi"
22#include "dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi"
23#include "dsi-panel-sharp-1080p-cmd.dtsi"
24#include "dsi-panel-sharp-dualmipi-1080p-120hz.dtsi"
25#include "dsi-panel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi"
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]26
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]27&soc {
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]28 dsi_panel_pwr_supply: dsi_panel_pwr_supply {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 qcom,panel-supply-entry@0 {
33 reg = <0>;
34 qcom,supply-name = "vddio";
35 qcom,supply-min-voltage = <1800000>;
36 qcom,supply-max-voltage = <1800000>;
37 qcom,supply-enable-load = <62000>;
38 qcom,supply-disable-load = <80>;
39 qcom,supply-post-on-sleep = <20>;
40 };
41
42 qcom,panel-supply-entry@1 {
43 reg = <1>;
44 qcom,supply-name = "lab";
45 qcom,supply-min-voltage = <4600000>;
46 qcom,supply-max-voltage = <6000000>;
47 qcom,supply-enable-load = <100000>;
48 qcom,supply-disable-load = <100>;
49 };
50
51 qcom,panel-supply-entry@2 {
52 reg = <2>;
53 qcom,supply-name = "ibb";
54 qcom,supply-min-voltage = <4600000>;
55 qcom,supply-max-voltage = <6000000>;
56 qcom,supply-enable-load = <100000>;
57 qcom,supply-disable-load = <100>;
58 qcom,supply-post-on-sleep = <20>;
59 };
60 };
61
62 dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb {
63 #address-cells = <1>;
64 #size-cells = <0>;
65
66 qcom,panel-supply-entry@0 {
67 reg = <0>;
68 qcom,supply-name = "vddio";
69 qcom,supply-min-voltage = <1800000>;
70 qcom,supply-max-voltage = <1800000>;
71 qcom,supply-enable-load = <62000>;
72 qcom,supply-disable-load = <80>;
73 qcom,supply-post-on-sleep = <20>;
74 };
75 };
76
77 dsi_panel_pwr_supply_vdd_no_labibb: dsi_panel_pwr_supply_vdd_no_labibb {
78 #address-cells = <1>;
79 #size-cells = <0>;
80
81 qcom,panel-supply-entry@0 {
82 reg = <0>;
83 qcom,supply-name = "vddio";
84 qcom,supply-min-voltage = <1800000>;
85 qcom,supply-max-voltage = <1800000>;
86 qcom,supply-enable-load = <62000>;
87 qcom,supply-disable-load = <80>;
88 qcom,supply-post-on-sleep = <20>;
89 };
90
91 qcom,panel-supply-entry@1 {
92 reg = <1>;
93 qcom,supply-name = "vdd";
94 qcom,supply-min-voltage = <3000000>;
95 qcom,supply-max-voltage = <3000000>;
96 qcom,supply-enable-load = <857000>;
97 qcom,supply-disable-load = <0>;
98 qcom,supply-post-on-sleep = <0>;
99 };
100 };
101
102 dsi_sharp_4k_dsc_video_display: qcom,dsi-display@0 {
103 compatible = "qcom,dsi-display";
Shashank Babu Chinta Venkata5f3ddcd22017-03-29 14:27:21 -0700[diff] [blame]104 label = "dsi_sharp_4k_dsc_video_display";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]105 qcom,display-type = "primary";
106
107 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
108 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
109 clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
110 <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
111 clock-names = "src_byte_clk", "src_pixel_clk";
112
113 pinctrl-names = "panel_active", "panel_suspend";
114 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
115 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
116 qcom,platform-te-gpio = <&tlmm 10 0>;
117 qcom,platform-reset-gpio = <&tlmm 6 0>;
118
119 qcom,dsi-panel = <&dsi_sharp_4k_dsc_video>;
120 vddio-supply = <&pm8998_l14>;
121 lab-supply = <&lab_regulator>;
122 ibb-supply = <&ibb_regulator>;
123 };
124
125 dsi_sharp_4k_dsc_cmd_display: qcom,dsi-display@1 {
126 compatible = "qcom,dsi-display";
Shashank Babu Chinta Venkata5f3ddcd22017-03-29 14:27:21 -0700[diff] [blame]127 label = "dsi_sharp_4k_dsc_cmd_display";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]128 qcom,display-type = "primary";
129
130 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
131 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
132 clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
133 <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
134 clock-names = "src_byte_clk", "src_pixel_clk";
135
136 pinctrl-names = "panel_active", "panel_suspend";
137 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
138 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
139 qcom,platform-te-gpio = <&tlmm 10 0>;
140 qcom,platform-reset-gpio = <&tlmm 6 0>;
141
142 qcom,dsi-panel = <&dsi_sharp_4k_dsc_cmd>;
143 vddio-supply = <&pm8998_l14>;
144 lab-supply = <&lab_regulator>;
145 ibb-supply = <&ibb_regulator>;
146 };
147
148 dsi_sharp_1080_cmd_display: qcom,dsi-display@2 {
149 compatible = "qcom,dsi-display";
Shashank Babu Chinta Venkata5f3ddcd22017-03-29 14:27:21 -0700[diff] [blame]150 label = "dsi_sharp_1080_cmd_display";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]151 qcom,display-type = "primary";
152
153 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
154 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
155 clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
156 <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
157 clock-names = "src_byte_clk", "src_pixel_clk";
158
159 pinctrl-names = "panel_active", "panel_suspend";
160 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
161 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
162 qcom,platform-te-gpio = <&tlmm 10 0>;
163 qcom,platform-reset-gpio = <&tlmm 6 0>;
164
165 qcom,dsi-panel = <&dsi_sharp_1080_cmd>;
166 vddio-supply = <&pm8998_l14>;
167 lab-supply = <&lab_regulator>;
168 ibb-supply = <&ibb_regulator>;
169 };
170
171 dsi_dual_sharp_1080_120hz_cmd_display: qcom,dsi-display@3 {
172 compatible = "qcom,dsi-display";
Shashank Babu Chinta Venkata5f3ddcd22017-03-29 14:27:21 -0700[diff] [blame]173 label = "dsi_dual_sharp_1080_120hz_cmd_display";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]174 qcom,display-type = "primary";
175
176 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
177 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
178 clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
179 <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
180 clock-names = "src_byte_clk", "src_pixel_clk";
181
182 pinctrl-names = "panel_active", "panel_suspend";
183 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
184 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
185 qcom,platform-te-gpio = <&tlmm 10 0>;
186 qcom,platform-reset-gpio = <&tlmm 6 0>;
187
188 qcom,dsi-panel = <&dsi_dual_sharp_1080_120hz_cmd>;
189 vddio-supply = <&pm8998_l14>;
190 lab-supply = <&lab_regulator>;
191 ibb-supply = <&ibb_regulator>;
192 };
193
194 dsi_dual_nt35597_truly_video_display: qcom,dsi-display@4 {
195 compatible = "qcom,dsi-display";
Shashank Babu Chinta Venkata5f3ddcd22017-03-29 14:27:21 -0700[diff] [blame]196 label = "dsi_dual_nt35597_truly_video_display";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]197 qcom,display-type = "primary";
198
199 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
200 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
201 clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
202 <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
203 clock-names = "src_byte_clk", "src_pixel_clk";
204
205 pinctrl-names = "panel_active", "panel_suspend";
206 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
207 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
208 qcom,platform-te-gpio = <&tlmm 10 0>;
209 qcom,platform-reset-gpio = <&tlmm 6 0>;
210
211 qcom,dsi-panel = <&dsi_dual_nt35597_truly_video>;
212 vddio-supply = <&pm8998_l14>;
213 lab-supply = <&lab_regulator>;
214 ibb-supply = <&ibb_regulator>;
215 };
216
217 dsi_dual_nt35597_truly_cmd_display: qcom,dsi-display@5 {
218 compatible = "qcom,dsi-display";
Shashank Babu Chinta Venkata5f3ddcd22017-03-29 14:27:21 -0700[diff] [blame]219 label = "dsi_dual_nt35597_truly_cmd_display";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]220 qcom,display-type = "primary";
221
222 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
223 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
224 clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
225 <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
226 clock-names = "src_byte_clk", "src_pixel_clk";
227
228 pinctrl-names = "panel_active", "panel_suspend";
229 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
230 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
231 qcom,platform-te-gpio = <&tlmm 10 0>;
232 qcom,platform-reset-gpio = <&tlmm 6 0>;
233
234 qcom,dsi-panel = <&dsi_dual_nt35597_truly_cmd>;
235 vddio-supply = <&pm8998_l14>;
236 lab-supply = <&lab_regulator>;
237 ibb-supply = <&ibb_regulator>;
238 };
239
240 dsi_nt35597_truly_dsc_cmd_display: qcom,dsi-display@6 {
241 compatible = "qcom,dsi-display";
Shashank Babu Chinta Venkata5f3ddcd22017-03-29 14:27:21 -0700[diff] [blame]242 label = "dsi_nt35597_truly_dsc_cmd_display";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]243 qcom,display-type = "primary";
244
245 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
246 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
247 clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
248 <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
249 clock-names = "src_byte_clk", "src_pixel_clk";
250
251 pinctrl-names = "panel_active", "panel_suspend";
252 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
253 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
254 qcom,platform-te-gpio = <&tlmm 10 0>;
255 qcom,platform-reset-gpio = <&tlmm 6 0>;
256
257 qcom,dsi-panel = <&dsi_nt35597_truly_dsc_cmd>;
258 vddio-supply = <&pm8998_l14>;
259 lab-supply = <&lab_regulator>;
260 ibb-supply = <&ibb_regulator>;
261 };
262
263 dsi_nt35597_truly_dsc_video_display: qcom,dsi-display@7 {
264 compatible = "qcom,dsi-display";
Shashank Babu Chinta Venkata5f3ddcd22017-03-29 14:27:21 -0700[diff] [blame]265 label = "dsi_nt35597_truly_dsc_video_display";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]266 qcom,display-type = "primary";
267
268 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
269 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
270 clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
271 <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
272 clock-names = "src_byte_clk", "src_pixel_clk";
273
274 pinctrl-names = "panel_active", "panel_suspend";
275 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
276 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
277 qcom,platform-te-gpio = <&tlmm 10 0>;
278 qcom,platform-reset-gpio = <&tlmm 6 0>;
279
280 qcom,dsi-panel = <&dsi_nt35597_truly_dsc_video>;
281 vddio-supply = <&pm8998_l14>;
282 lab-supply = <&lab_regulator>;
283 ibb-supply = <&ibb_regulator>;
284 };
285
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]286 sde_wb: qcom,wb-display@0 {
287 compatible = "qcom,wb-display";
288 cell-index = <0>;
289 label = "wb_display";
290 };
291};
292
293&mdss_mdp {
294 connectors = <&sde_wb>;
295};
Shashank Babu Chinta Venkata939a3a42017-03-30 13:00:25 -0700[diff] [blame]296
297&dsi_dual_nt35597_truly_video {
298 qcom,mdss-dsi-panel-timings = [00 1c 07 07 23 21 07 07 05 03 04];
299 qcom,mdss-dsi-t-clk-post = <0x0D>;
300 qcom,mdss-dsi-t-clk-pre = <0x2D>;
301};
302
303&dsi_dual_nt35597_truly_cmd {
304 qcom,mdss-dsi-panel-timings = [00 1c 07 07 23 21 07 07 05 03 04];
305 qcom,mdss-dsi-t-clk-post = <0x0D>;
306 qcom,mdss-dsi-t-clk-pre = <0x2D>;
307};
308
309&dsi_nt35597_truly_dsc_cmd {
310 qcom,mdss-dsi-panel-timings = [00 15 05 05 20 1f 05 05 03 03 04];
311 qcom,mdss-dsi-t-clk-post = <0x0b>;
312 qcom,mdss-dsi-t-clk-pre = <0x23>;
313};
314
315&dsi_nt35597_truly_dsc_video {
316 qcom,mdss-dsi-panel-timings = [00 15 05 05 20 1f 05 05 03 03 04];
317 qcom,mdss-dsi-t-clk-post = <0x0b>;
318 qcom,mdss-dsi-t-clk-pre = <0x23>;
319};
320
321&dsi_sharp_4k_dsc_video {
322 qcom,mdss-dsi-panel-timings = [00 12 04 04 1e 1e 04 04 02 03 04];
323 qcom,mdss-dsi-t-clk-post = <0x0a>;
324 qcom,mdss-dsi-t-clk-pre = <0x1e>;
325};
326
327&dsi_sharp_4k_dsc_cmd {
328 qcom,mdss-dsi-panel-timings = [00 12 04 04 1e 1e 04 04 02 03 04];
329 qcom,mdss-dsi-t-clk-post = <0x0a>;
330 qcom,mdss-dsi-t-clk-pre = <0x1e>;
331};
332
333&dsi_dual_sharp_1080_120hz_cmd {
334 qcom,mdss-dsi-panel-timings = [00 24 09 09 26 24 09 09 06 03 04];
335 qcom,mdss-dsi-t-clk-post = <0x0f>;
336 qcom,mdss-dsi-t-clk-pre = <0x36>;
337};