Deepak Katragadda | 24ee246 | 2016-12-16 14:26:38 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/bitops.h> |
| 16 | #include <linux/err.h> |
| 17 | #include <linux/platform_device.h> |
| 18 | #include <linux/module.h> |
| 19 | #include <linux/of.h> |
| 20 | #include <linux/of_device.h> |
| 21 | #include <linux/clk.h> |
| 22 | #include <linux/clk-provider.h> |
| 23 | #include <linux/regmap.h> |
| 24 | #include <linux/reset-controller.h> |
| 25 | |
| 26 | #include <dt-bindings/clock/qcom,dispcc-sdm845.h> |
| 27 | |
| 28 | #include "common.h" |
| 29 | #include "clk-regmap.h" |
| 30 | #include "clk-pll.h" |
| 31 | #include "clk-rcg.h" |
| 32 | #include "clk-branch.h" |
| 33 | #include "reset.h" |
| 34 | #include "clk-alpha-pll.h" |
| 35 | #include "vdd-level-sdm845.h" |
| 36 | #include "clk-regmap-divider.h" |
| 37 | |
| 38 | #define DISP_CC_MISC_CMD 0x8000 |
| 39 | |
| 40 | #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } |
| 41 | #define F_SLEW(f, s, h, m, n, src_freq) { (f), (s), (2 * (h) - 1), (m), (n), \ |
| 42 | (src_freq) } |
| 43 | |
| 44 | static DEFINE_VDD_REGULATORS(vdd_cx, VDD_CX_NUM, 1, vdd_corner); |
| 45 | |
| 46 | enum { |
| 47 | P_BI_TCXO, |
| 48 | P_CORE_BI_PLL_TEST_SE, |
| 49 | P_DISP_CC_PLL0_OUT_MAIN, |
| 50 | P_DP_PHY_PLL_LINK_CLK, |
| 51 | P_DP_PHY_PLL_VCO_DIV_CLK, |
| 52 | P_DSI0_PHY_PLL_OUT_BYTECLK, |
| 53 | P_DSI0_PHY_PLL_OUT_DSICLK, |
| 54 | P_DSI1_PHY_PLL_OUT_BYTECLK, |
| 55 | P_DSI1_PHY_PLL_OUT_DSICLK, |
| 56 | P_GPLL0_OUT_MAIN, |
| 57 | P_GPLL0_OUT_MAIN_DIV, |
| 58 | }; |
| 59 | |
| 60 | static const struct parent_map disp_cc_parent_map_0[] = { |
| 61 | { P_BI_TCXO, 0 }, |
| 62 | { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, |
| 63 | { P_DSI1_PHY_PLL_OUT_BYTECLK, 2 }, |
| 64 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 65 | }; |
| 66 | |
| 67 | static const char * const disp_cc_parent_names_0[] = { |
| 68 | "bi_tcxo", |
| 69 | "dsi0_phy_pll_out_byteclk", |
| 70 | "dsi1_phy_pll_out_byteclk", |
| 71 | "core_bi_pll_test_se", |
| 72 | }; |
| 73 | |
| 74 | static const struct parent_map disp_cc_parent_map_1[] = { |
| 75 | { P_BI_TCXO, 0 }, |
| 76 | { P_DP_PHY_PLL_LINK_CLK, 1 }, |
| 77 | { P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, |
| 78 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 79 | }; |
| 80 | |
| 81 | static const char * const disp_cc_parent_names_1[] = { |
| 82 | "bi_tcxo", |
| 83 | "dp_phy_pll_link_clk", |
| 84 | "dp_phy_pll_vco_div_clk", |
| 85 | "core_bi_pll_test_se", |
| 86 | }; |
| 87 | |
| 88 | static const struct parent_map disp_cc_parent_map_2[] = { |
| 89 | { P_BI_TCXO, 0 }, |
| 90 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 91 | }; |
| 92 | |
| 93 | static const char * const disp_cc_parent_names_2[] = { |
| 94 | "bi_tcxo", |
| 95 | "core_bi_pll_test_se", |
| 96 | }; |
| 97 | |
| 98 | static const struct parent_map disp_cc_parent_map_3[] = { |
| 99 | { P_BI_TCXO, 0 }, |
| 100 | { P_DISP_CC_PLL0_OUT_MAIN, 1 }, |
| 101 | { P_GPLL0_OUT_MAIN, 4 }, |
| 102 | { P_GPLL0_OUT_MAIN_DIV, 5 }, |
| 103 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 104 | }; |
| 105 | |
| 106 | static const char * const disp_cc_parent_names_3[] = { |
| 107 | "bi_tcxo", |
| 108 | "disp_cc_pll0", |
Deepak Katragadda | d012b4d | 2017-04-10 12:03:37 -0700 | [diff] [blame] | 109 | "gcc_disp_gpll0_clk_src", |
| 110 | "gcc_disp_gpll0_div_clk_src", |
Deepak Katragadda | 24ee246 | 2016-12-16 14:26:38 -0800 | [diff] [blame] | 111 | "core_bi_pll_test_se", |
| 112 | }; |
| 113 | |
| 114 | static const struct parent_map disp_cc_parent_map_4[] = { |
| 115 | { P_BI_TCXO, 0 }, |
| 116 | { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, |
| 117 | { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, |
| 118 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 119 | }; |
| 120 | |
| 121 | static const char * const disp_cc_parent_names_4[] = { |
| 122 | "bi_tcxo", |
| 123 | "dsi0_phy_pll_out_dsiclk", |
| 124 | "dsi1_phy_pll_out_dsiclk", |
| 125 | "core_bi_pll_test_se", |
| 126 | }; |
| 127 | |
| 128 | static struct pll_vco fabia_vco[] = { |
| 129 | { 250000000, 2000000000, 0 }, |
| 130 | { 125000000, 1000000000, 1 }, |
| 131 | }; |
| 132 | |
| 133 | static const struct pll_config disp_cc_pll0_config = { |
| 134 | .l = 0x2c, |
| 135 | .frac = 0xcaab, |
| 136 | }; |
| 137 | |
| 138 | static struct clk_alpha_pll disp_cc_pll0 = { |
| 139 | .offset = 0x0, |
| 140 | .vco_table = fabia_vco, |
| 141 | .num_vco = ARRAY_SIZE(fabia_vco), |
| 142 | .type = FABIA_PLL, |
| 143 | .clkr = { |
| 144 | .hw.init = &(struct clk_init_data){ |
| 145 | .name = "disp_cc_pll0", |
| 146 | .parent_names = (const char *[]){ "bi_tcxo" }, |
| 147 | .num_parents = 1, |
| 148 | .ops = &clk_fabia_pll_ops, |
Deepak Katragadda | d04d2ca | 2017-03-30 11:03:20 -0700 | [diff] [blame] | 149 | VDD_CX_FMAX_MAP4( |
| 150 | MIN, 615000000, |
| 151 | LOW, 1066000000, |
| 152 | LOW_L1, 1600000000, |
| 153 | NOMINAL, 2000000000), |
Deepak Katragadda | 24ee246 | 2016-12-16 14:26:38 -0800 | [diff] [blame] | 154 | }, |
| 155 | }, |
| 156 | }; |
| 157 | |
| 158 | static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { |
| 159 | .cmd_rcgr = 0x20d0, |
| 160 | .mnd_width = 0, |
| 161 | .hid_width = 5, |
| 162 | .parent_map = disp_cc_parent_map_0, |
| 163 | .clkr.hw.init = &(struct clk_init_data){ |
| 164 | .name = "disp_cc_mdss_byte0_clk_src", |
| 165 | .parent_names = disp_cc_parent_names_0, |
| 166 | .num_parents = 4, |
| 167 | .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
| 168 | .ops = &clk_byte2_ops, |
| 169 | VDD_CX_FMAX_MAP5( |
| 170 | MIN, 19200000, |
| 171 | LOWER, 150000000, |
| 172 | LOW, 240000000, |
| 173 | LOW_L1, 262500000, |
| 174 | NOMINAL, 358000000), |
| 175 | }, |
| 176 | }; |
| 177 | |
| 178 | static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { |
| 179 | .cmd_rcgr = 0x20ec, |
| 180 | .mnd_width = 0, |
| 181 | .hid_width = 5, |
| 182 | .parent_map = disp_cc_parent_map_0, |
| 183 | .clkr.hw.init = &(struct clk_init_data){ |
| 184 | .name = "disp_cc_mdss_byte1_clk_src", |
| 185 | .parent_names = disp_cc_parent_names_0, |
| 186 | .num_parents = 4, |
| 187 | .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
| 188 | .ops = &clk_byte2_ops, |
| 189 | VDD_CX_FMAX_MAP5( |
| 190 | MIN, 19200000, |
| 191 | LOWER, 150000000, |
| 192 | LOW, 240000000, |
| 193 | LOW_L1, 262500000, |
| 194 | NOMINAL, 358000000), |
| 195 | }, |
| 196 | }; |
| 197 | |
| 198 | static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = { |
| 199 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 200 | { } |
| 201 | }; |
| 202 | |
| 203 | static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { |
| 204 | .cmd_rcgr = 0x219c, |
| 205 | .mnd_width = 0, |
| 206 | .hid_width = 5, |
| 207 | .parent_map = disp_cc_parent_map_2, |
| 208 | .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, |
| 209 | .clkr.hw.init = &(struct clk_init_data){ |
| 210 | .name = "disp_cc_mdss_dp_aux_clk_src", |
| 211 | .parent_names = disp_cc_parent_names_2, |
| 212 | .num_parents = 2, |
| 213 | .flags = CLK_SET_RATE_PARENT, |
| 214 | .ops = &clk_rcg2_ops, |
| 215 | VDD_CX_FMAX_MAP1( |
| 216 | MIN, 19200000), |
| 217 | }, |
| 218 | }; |
| 219 | |
| 220 | /* Need to get the exact frequencies that are supported */ |
| 221 | static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = { |
| 222 | F( 108000000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), |
| 223 | F( 180000000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), |
| 224 | F( 360000000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), |
| 225 | F( 540000000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), |
| 226 | { } |
| 227 | }; |
| 228 | |
| 229 | static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { |
| 230 | .cmd_rcgr = 0x2154, |
| 231 | .mnd_width = 0, |
| 232 | .hid_width = 5, |
| 233 | .parent_map = disp_cc_parent_map_1, |
| 234 | .freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src, |
| 235 | .clkr.hw.init = &(struct clk_init_data){ |
| 236 | .name = "disp_cc_mdss_dp_crypto_clk_src", |
| 237 | .parent_names = disp_cc_parent_names_1, |
| 238 | .num_parents = 4, |
| 239 | .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
| 240 | .ops = &clk_rcg2_ops, |
| 241 | VDD_CX_FMAX_MAP5( |
| 242 | MIN, 12800000, |
| 243 | LOWER, 108000000, |
| 244 | LOW, 180000000, |
| 245 | LOW_L1, 360000000, |
| 246 | NOMINAL, 540000000), |
| 247 | }, |
| 248 | }; |
| 249 | |
| 250 | /* Need to get the exact frequencies that are supported */ |
| 251 | static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { |
| 252 | F_SLEW( 162000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0, 324000000), |
| 253 | F_SLEW( 270000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0, 540000000), |
| 254 | F_SLEW( 540000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0, 1080000000), |
| 255 | F_SLEW( 810000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0, 1620000000), |
| 256 | { } |
| 257 | }; |
| 258 | |
| 259 | static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { |
| 260 | .cmd_rcgr = 0x2138, |
| 261 | .mnd_width = 0, |
| 262 | .hid_width = 5, |
| 263 | .parent_map = disp_cc_parent_map_1, |
| 264 | .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src, |
| 265 | .clkr.hw.init = &(struct clk_init_data){ |
| 266 | .name = "disp_cc_mdss_dp_link_clk_src", |
| 267 | .parent_names = disp_cc_parent_names_1, |
| 268 | .num_parents = 4, |
| 269 | .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
| 270 | .ops = &clk_rcg2_ops, |
| 271 | VDD_CX_FMAX_MAP5( |
| 272 | MIN, 19200000, |
| 273 | LOWER, 162000000, |
| 274 | LOW, 270000000, |
| 275 | LOW_L1, 540000000, |
| 276 | NOMINAL, 810000000), |
| 277 | }, |
| 278 | }; |
| 279 | |
| 280 | static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { |
| 281 | .cmd_rcgr = 0x2184, |
| 282 | .mnd_width = 16, |
| 283 | .hid_width = 5, |
| 284 | .parent_map = disp_cc_parent_map_1, |
| 285 | .clkr.hw.init = &(struct clk_init_data){ |
| 286 | .name = "disp_cc_mdss_dp_pixel1_clk_src", |
| 287 | .parent_names = (const char *[]){ |
| 288 | "dp_phy_pll_vco_div_clk", |
| 289 | }, |
| 290 | .num_parents = 1, |
| 291 | .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
| 292 | .ops = &clk_dp_ops, |
| 293 | VDD_CX_FMAX_MAP4( |
| 294 | MIN, 19200000, |
| 295 | LOWER, 202500000, |
| 296 | LOW, 296735905, |
| 297 | LOW_L1, 675000000), |
| 298 | }, |
| 299 | }; |
| 300 | |
| 301 | static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { |
| 302 | .cmd_rcgr = 0x216c, |
| 303 | .mnd_width = 16, |
| 304 | .hid_width = 5, |
| 305 | .parent_map = disp_cc_parent_map_1, |
| 306 | .clkr.hw.init = &(struct clk_init_data){ |
| 307 | .name = "disp_cc_mdss_dp_pixel_clk_src", |
| 308 | .parent_names = (const char *[]){ |
| 309 | "dp_phy_pll_vco_div_clk", |
| 310 | }, |
| 311 | .num_parents = 1, |
| 312 | .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
| 313 | .ops = &clk_dp_ops, |
| 314 | VDD_CX_FMAX_MAP4( |
| 315 | MIN, 19200000, |
| 316 | LOWER, 202500000, |
| 317 | LOW, 296735905, |
| 318 | LOW_L1, 675000000), |
| 319 | }, |
| 320 | }; |
| 321 | |
| 322 | static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = { |
| 323 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 324 | { } |
| 325 | }; |
| 326 | |
| 327 | static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { |
| 328 | .cmd_rcgr = 0x2108, |
| 329 | .mnd_width = 0, |
| 330 | .hid_width = 5, |
| 331 | .parent_map = disp_cc_parent_map_0, |
| 332 | .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, |
| 333 | .clkr.hw.init = &(struct clk_init_data){ |
| 334 | .name = "disp_cc_mdss_esc0_clk_src", |
| 335 | .parent_names = disp_cc_parent_names_0, |
| 336 | .num_parents = 4, |
| 337 | .flags = CLK_SET_RATE_PARENT, |
| 338 | .ops = &clk_rcg2_ops, |
| 339 | VDD_CX_FMAX_MAP1( |
| 340 | MIN, 19200000), |
| 341 | }, |
| 342 | }; |
| 343 | |
| 344 | static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { |
| 345 | .cmd_rcgr = 0x2120, |
| 346 | .mnd_width = 0, |
| 347 | .hid_width = 5, |
| 348 | .parent_map = disp_cc_parent_map_0, |
| 349 | .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, |
| 350 | .clkr.hw.init = &(struct clk_init_data){ |
| 351 | .name = "disp_cc_mdss_esc1_clk_src", |
| 352 | .parent_names = disp_cc_parent_names_0, |
| 353 | .num_parents = 4, |
| 354 | .flags = CLK_SET_RATE_PARENT, |
| 355 | .ops = &clk_rcg2_ops, |
| 356 | VDD_CX_FMAX_MAP1( |
| 357 | MIN, 19200000), |
| 358 | }, |
| 359 | }; |
| 360 | |
| 361 | static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { |
| 362 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 363 | F(85714286, P_GPLL0_OUT_MAIN, 7, 0, 0), |
| 364 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), |
| 365 | F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), |
| 366 | F(165000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0), |
| 367 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), |
| 368 | F(275000000, P_DISP_CC_PLL0_OUT_MAIN, 1.5, 0, 0), |
| 369 | F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), |
| 370 | F(412500000, P_DISP_CC_PLL0_OUT_MAIN, 1, 0, 0), |
| 371 | { } |
| 372 | }; |
| 373 | |
| 374 | static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { |
| 375 | .cmd_rcgr = 0x2088, |
| 376 | .mnd_width = 0, |
| 377 | .hid_width = 5, |
| 378 | .parent_map = disp_cc_parent_map_3, |
| 379 | .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, |
| 380 | .enable_safe_config = true, |
| 381 | .clkr.hw.init = &(struct clk_init_data){ |
| 382 | .name = "disp_cc_mdss_mdp_clk_src", |
| 383 | .parent_names = disp_cc_parent_names_3, |
| 384 | .num_parents = 5, |
| 385 | .flags = CLK_SET_RATE_PARENT, |
| 386 | .ops = &clk_rcg2_ops, |
| 387 | VDD_CX_FMAX_MAP4( |
| 388 | MIN, 19200000, |
| 389 | LOWER, 165000000, |
| 390 | LOW, 300000000, |
| 391 | NOMINAL, 412500000), |
| 392 | }, |
| 393 | }; |
| 394 | |
| 395 | static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { |
| 396 | .cmd_rcgr = 0x2058, |
| 397 | .mnd_width = 8, |
| 398 | .hid_width = 5, |
| 399 | .parent_map = disp_cc_parent_map_4, |
| 400 | .clkr.hw.init = &(struct clk_init_data){ |
| 401 | .name = "disp_cc_mdss_pclk0_clk_src", |
| 402 | .parent_names = disp_cc_parent_names_4, |
| 403 | .num_parents = 4, |
| 404 | .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
| 405 | .ops = &clk_pixel_ops, |
| 406 | VDD_CX_FMAX_MAP5( |
| 407 | MIN, 19200000, |
| 408 | LOWER, 184000000, |
| 409 | LOW, 295000000, |
| 410 | LOW_L1, 350000000, |
| 411 | NOMINAL, 571428571), |
| 412 | }, |
| 413 | }; |
| 414 | |
| 415 | static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { |
| 416 | .cmd_rcgr = 0x2070, |
| 417 | .mnd_width = 8, |
| 418 | .hid_width = 5, |
| 419 | .parent_map = disp_cc_parent_map_4, |
| 420 | .clkr.hw.init = &(struct clk_init_data){ |
| 421 | .name = "disp_cc_mdss_pclk1_clk_src", |
| 422 | .parent_names = disp_cc_parent_names_4, |
| 423 | .num_parents = 4, |
| 424 | .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
| 425 | .ops = &clk_pixel_ops, |
| 426 | VDD_CX_FMAX_MAP5( |
| 427 | MIN, 19200000, |
| 428 | LOWER, 184000000, |
| 429 | LOW, 295000000, |
| 430 | LOW_L1, 350000000, |
| 431 | NOMINAL, 571428571), |
| 432 | }, |
| 433 | }; |
| 434 | |
| 435 | static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = { |
| 436 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 437 | F(165000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0), |
| 438 | F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), |
| 439 | F(412500000, P_DISP_CC_PLL0_OUT_MAIN, 1, 0, 0), |
| 440 | { } |
| 441 | }; |
| 442 | |
| 443 | static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { |
| 444 | .cmd_rcgr = 0x20a0, |
| 445 | .mnd_width = 0, |
| 446 | .hid_width = 5, |
| 447 | .parent_map = disp_cc_parent_map_3, |
| 448 | .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src, |
| 449 | .enable_safe_config = true, |
| 450 | .clkr.hw.init = &(struct clk_init_data){ |
| 451 | .name = "disp_cc_mdss_rot_clk_src", |
| 452 | .parent_names = disp_cc_parent_names_3, |
| 453 | .num_parents = 5, |
| 454 | .flags = CLK_SET_RATE_PARENT, |
| 455 | .ops = &clk_rcg2_ops, |
| 456 | VDD_CX_FMAX_MAP4( |
| 457 | MIN, 19200000, |
| 458 | LOWER, 165000000, |
| 459 | LOW, 300000000, |
| 460 | NOMINAL, 412500000), |
| 461 | }, |
| 462 | }; |
| 463 | |
| 464 | static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { |
| 465 | .cmd_rcgr = 0x20b8, |
| 466 | .mnd_width = 0, |
| 467 | .hid_width = 5, |
| 468 | .parent_map = disp_cc_parent_map_2, |
| 469 | .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, |
| 470 | .clkr.hw.init = &(struct clk_init_data){ |
| 471 | .name = "disp_cc_mdss_vsync_clk_src", |
| 472 | .parent_names = disp_cc_parent_names_2, |
| 473 | .num_parents = 2, |
| 474 | .flags = CLK_SET_RATE_PARENT, |
| 475 | .ops = &clk_rcg2_ops, |
| 476 | VDD_CX_FMAX_MAP1( |
| 477 | MIN, 19200000), |
| 478 | }, |
| 479 | }; |
| 480 | |
Deepak Katragadda | 24ee246 | 2016-12-16 14:26:38 -0800 | [diff] [blame] | 481 | static struct clk_branch disp_cc_mdss_ahb_clk = { |
| 482 | .halt_reg = 0x4004, |
| 483 | .halt_check = BRANCH_HALT, |
| 484 | .clkr = { |
| 485 | .enable_reg = 0x4004, |
| 486 | .enable_mask = BIT(0), |
| 487 | .hw.init = &(struct clk_init_data){ |
| 488 | .name = "disp_cc_mdss_ahb_clk", |
| 489 | .ops = &clk_branch2_ops, |
| 490 | }, |
| 491 | }, |
| 492 | }; |
| 493 | |
| 494 | static struct clk_branch disp_cc_mdss_axi_clk = { |
| 495 | .halt_reg = 0x4008, |
| 496 | .halt_check = BRANCH_HALT, |
| 497 | .clkr = { |
| 498 | .enable_reg = 0x4008, |
| 499 | .enable_mask = BIT(0), |
| 500 | .hw.init = &(struct clk_init_data){ |
| 501 | .name = "disp_cc_mdss_axi_clk", |
| 502 | .ops = &clk_branch2_ops, |
| 503 | }, |
| 504 | }, |
| 505 | }; |
| 506 | |
| 507 | static struct clk_branch disp_cc_mdss_byte0_clk = { |
| 508 | .halt_reg = 0x2028, |
| 509 | .halt_check = BRANCH_HALT, |
| 510 | .clkr = { |
| 511 | .enable_reg = 0x2028, |
| 512 | .enable_mask = BIT(0), |
| 513 | .hw.init = &(struct clk_init_data){ |
| 514 | .name = "disp_cc_mdss_byte0_clk", |
| 515 | .parent_names = (const char *[]){ |
| 516 | "disp_cc_mdss_byte0_clk_src", |
| 517 | }, |
| 518 | .num_parents = 1, |
| 519 | .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
| 520 | .ops = &clk_branch2_ops, |
| 521 | }, |
| 522 | }, |
| 523 | }; |
| 524 | |
| 525 | static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { |
| 526 | .reg = 0x20e8, |
| 527 | .shift = 0, |
| 528 | .width = 2, |
| 529 | .clkr = { |
| 530 | .hw.init = &(struct clk_init_data){ |
| 531 | .name = "disp_cc_mdss_byte0_div_clk_src", |
| 532 | .parent_names = (const char *[]){ |
| 533 | "disp_cc_mdss_byte0_clk_src", |
| 534 | }, |
| 535 | .num_parents = 1, |
Deepak Katragadda | 638c12e | 2017-04-20 14:56:53 -0700 | [diff] [blame] | 536 | .flags = CLK_GET_RATE_NOCACHE, |
Deepak Katragadda | 24ee246 | 2016-12-16 14:26:38 -0800 | [diff] [blame] | 537 | .ops = &clk_regmap_div_ops, |
| 538 | }, |
| 539 | }, |
| 540 | }; |
| 541 | |
| 542 | static struct clk_branch disp_cc_mdss_byte0_intf_clk = { |
| 543 | .halt_reg = 0x202c, |
| 544 | .halt_check = BRANCH_HALT, |
| 545 | .clkr = { |
| 546 | .enable_reg = 0x202c, |
| 547 | .enable_mask = BIT(0), |
| 548 | .hw.init = &(struct clk_init_data){ |
| 549 | .name = "disp_cc_mdss_byte0_intf_clk", |
| 550 | .parent_names = (const char *[]){ |
| 551 | "disp_cc_mdss_byte0_div_clk_src", |
| 552 | }, |
| 553 | .num_parents = 1, |
| 554 | .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
| 555 | .ops = &clk_branch2_ops, |
| 556 | }, |
| 557 | }, |
| 558 | }; |
| 559 | |
| 560 | static struct clk_branch disp_cc_mdss_byte1_clk = { |
| 561 | .halt_reg = 0x2030, |
| 562 | .halt_check = BRANCH_HALT, |
| 563 | .clkr = { |
| 564 | .enable_reg = 0x2030, |
| 565 | .enable_mask = BIT(0), |
| 566 | .hw.init = &(struct clk_init_data){ |
| 567 | .name = "disp_cc_mdss_byte1_clk", |
| 568 | .parent_names = (const char *[]){ |
| 569 | "disp_cc_mdss_byte1_clk_src", |
| 570 | }, |
| 571 | .num_parents = 1, |
| 572 | .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
| 573 | .ops = &clk_branch2_ops, |
| 574 | }, |
| 575 | }, |
| 576 | }; |
| 577 | |
| 578 | static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { |
| 579 | .reg = 0x2104, |
| 580 | .shift = 0, |
| 581 | .width = 2, |
| 582 | .clkr = { |
| 583 | .hw.init = &(struct clk_init_data){ |
| 584 | .name = "disp_cc_mdss_byte1_div_clk_src", |
| 585 | .parent_names = (const char *[]){ |
| 586 | "disp_cc_mdss_byte1_clk_src", |
| 587 | }, |
| 588 | .num_parents = 1, |
Deepak Katragadda | 638c12e | 2017-04-20 14:56:53 -0700 | [diff] [blame] | 589 | .flags = CLK_GET_RATE_NOCACHE, |
Deepak Katragadda | 24ee246 | 2016-12-16 14:26:38 -0800 | [diff] [blame] | 590 | .ops = &clk_regmap_div_ops, |
| 591 | }, |
| 592 | }, |
| 593 | }; |
| 594 | |
| 595 | static struct clk_branch disp_cc_mdss_byte1_intf_clk = { |
| 596 | .halt_reg = 0x2034, |
| 597 | .halt_check = BRANCH_HALT, |
| 598 | .clkr = { |
| 599 | .enable_reg = 0x2034, |
| 600 | .enable_mask = BIT(0), |
| 601 | .hw.init = &(struct clk_init_data){ |
| 602 | .name = "disp_cc_mdss_byte1_intf_clk", |
| 603 | .parent_names = (const char *[]){ |
| 604 | "disp_cc_mdss_byte1_div_clk_src", |
| 605 | }, |
| 606 | .num_parents = 1, |
| 607 | .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
| 608 | .ops = &clk_branch2_ops, |
| 609 | }, |
| 610 | }, |
| 611 | }; |
| 612 | |
| 613 | static struct clk_branch disp_cc_mdss_dp_aux_clk = { |
| 614 | .halt_reg = 0x2054, |
| 615 | .halt_check = BRANCH_HALT, |
| 616 | .clkr = { |
| 617 | .enable_reg = 0x2054, |
| 618 | .enable_mask = BIT(0), |
| 619 | .hw.init = &(struct clk_init_data){ |
| 620 | .name = "disp_cc_mdss_dp_aux_clk", |
| 621 | .parent_names = (const char *[]){ |
| 622 | "disp_cc_mdss_dp_aux_clk_src", |
| 623 | }, |
| 624 | .num_parents = 1, |
| 625 | .flags = CLK_SET_RATE_PARENT, |
| 626 | .ops = &clk_branch2_ops, |
| 627 | }, |
| 628 | }, |
| 629 | }; |
| 630 | |
| 631 | static struct clk_branch disp_cc_mdss_dp_crypto_clk = { |
| 632 | .halt_reg = 0x2048, |
| 633 | .halt_check = BRANCH_HALT, |
| 634 | .clkr = { |
| 635 | .enable_reg = 0x2048, |
| 636 | .enable_mask = BIT(0), |
| 637 | .hw.init = &(struct clk_init_data){ |
| 638 | .name = "disp_cc_mdss_dp_crypto_clk", |
| 639 | .parent_names = (const char *[]){ |
| 640 | "disp_cc_mdss_dp_crypto_clk_src", |
| 641 | }, |
| 642 | .num_parents = 1, |
| 643 | .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
| 644 | .ops = &clk_branch2_ops, |
| 645 | }, |
| 646 | }, |
| 647 | }; |
| 648 | |
| 649 | static struct clk_branch disp_cc_mdss_dp_link_clk = { |
| 650 | .halt_reg = 0x2040, |
| 651 | .halt_check = BRANCH_HALT, |
| 652 | .clkr = { |
| 653 | .enable_reg = 0x2040, |
| 654 | .enable_mask = BIT(0), |
| 655 | .hw.init = &(struct clk_init_data){ |
| 656 | .name = "disp_cc_mdss_dp_link_clk", |
| 657 | .parent_names = (const char *[]){ |
| 658 | "disp_cc_mdss_dp_link_clk_src", |
| 659 | }, |
| 660 | .num_parents = 1, |
| 661 | .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
| 662 | .ops = &clk_branch2_ops, |
| 663 | }, |
| 664 | }, |
| 665 | }; |
| 666 | |
| 667 | static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = { |
| 668 | .reg = 0x2150, |
| 669 | .shift = 0, |
| 670 | .width = 2, |
| 671 | .clkr = { |
| 672 | .hw.init = &(struct clk_init_data){ |
| 673 | .name = "disp_cc_mdss_dp_link_div_clk_src", |
| 674 | .parent_names = (const char *[]){ |
| 675 | "disp_cc_mdss_dp_link_clk_src", |
| 676 | }, |
| 677 | .num_parents = 1, |
| 678 | .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
| 679 | .ops = &clk_regmap_div_ops, |
| 680 | }, |
| 681 | }, |
| 682 | }; |
| 683 | |
| 684 | static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { |
| 685 | .halt_reg = 0x2044, |
| 686 | .halt_check = BRANCH_HALT, |
| 687 | .clkr = { |
| 688 | .enable_reg = 0x2044, |
| 689 | .enable_mask = BIT(0), |
| 690 | .hw.init = &(struct clk_init_data){ |
| 691 | .name = "disp_cc_mdss_dp_link_intf_clk", |
| 692 | .parent_names = (const char *[]){ |
| 693 | "disp_cc_mdss_dp_link_div_clk_src", |
| 694 | }, |
| 695 | .num_parents = 1, |
| 696 | .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
| 697 | .ops = &clk_branch2_ops, |
| 698 | }, |
| 699 | }, |
| 700 | }; |
| 701 | |
| 702 | static struct clk_branch disp_cc_mdss_dp_pixel1_clk = { |
| 703 | .halt_reg = 0x2050, |
| 704 | .halt_check = BRANCH_HALT, |
| 705 | .clkr = { |
| 706 | .enable_reg = 0x2050, |
| 707 | .enable_mask = BIT(0), |
| 708 | .hw.init = &(struct clk_init_data){ |
| 709 | .name = "disp_cc_mdss_dp_pixel1_clk", |
| 710 | .parent_names = (const char *[]){ |
| 711 | "disp_cc_mdss_dp_pixel1_clk_src", |
| 712 | }, |
| 713 | .num_parents = 1, |
| 714 | .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
| 715 | .ops = &clk_branch2_ops, |
| 716 | }, |
| 717 | }, |
| 718 | }; |
| 719 | |
| 720 | static struct clk_branch disp_cc_mdss_dp_pixel_clk = { |
| 721 | .halt_reg = 0x204c, |
| 722 | .halt_check = BRANCH_HALT, |
| 723 | .clkr = { |
| 724 | .enable_reg = 0x204c, |
| 725 | .enable_mask = BIT(0), |
| 726 | .hw.init = &(struct clk_init_data){ |
| 727 | .name = "disp_cc_mdss_dp_pixel_clk", |
| 728 | .parent_names = (const char *[]){ |
| 729 | "disp_cc_mdss_dp_pixel_clk_src", |
| 730 | }, |
| 731 | .num_parents = 1, |
| 732 | .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
| 733 | .ops = &clk_branch2_ops, |
| 734 | }, |
| 735 | }, |
| 736 | }; |
| 737 | |
| 738 | static struct clk_branch disp_cc_mdss_esc0_clk = { |
| 739 | .halt_reg = 0x2038, |
| 740 | .halt_check = BRANCH_HALT, |
| 741 | .clkr = { |
| 742 | .enable_reg = 0x2038, |
| 743 | .enable_mask = BIT(0), |
| 744 | .hw.init = &(struct clk_init_data){ |
| 745 | .name = "disp_cc_mdss_esc0_clk", |
| 746 | .parent_names = (const char *[]){ |
| 747 | "disp_cc_mdss_esc0_clk_src", |
| 748 | }, |
| 749 | .num_parents = 1, |
| 750 | .flags = CLK_SET_RATE_PARENT, |
| 751 | .ops = &clk_branch2_ops, |
| 752 | }, |
| 753 | }, |
| 754 | }; |
| 755 | |
| 756 | static struct clk_branch disp_cc_mdss_esc1_clk = { |
| 757 | .halt_reg = 0x203c, |
| 758 | .halt_check = BRANCH_HALT, |
| 759 | .clkr = { |
| 760 | .enable_reg = 0x203c, |
| 761 | .enable_mask = BIT(0), |
| 762 | .hw.init = &(struct clk_init_data){ |
| 763 | .name = "disp_cc_mdss_esc1_clk", |
| 764 | .parent_names = (const char *[]){ |
| 765 | "disp_cc_mdss_esc1_clk_src", |
| 766 | }, |
| 767 | .num_parents = 1, |
| 768 | .flags = CLK_SET_RATE_PARENT, |
| 769 | .ops = &clk_branch2_ops, |
| 770 | }, |
| 771 | }, |
| 772 | }; |
| 773 | |
| 774 | static struct clk_branch disp_cc_mdss_mdp_clk = { |
| 775 | .halt_reg = 0x200c, |
| 776 | .halt_check = BRANCH_HALT, |
| 777 | .clkr = { |
| 778 | .enable_reg = 0x200c, |
| 779 | .enable_mask = BIT(0), |
| 780 | .hw.init = &(struct clk_init_data){ |
| 781 | .name = "disp_cc_mdss_mdp_clk", |
| 782 | .parent_names = (const char *[]){ |
| 783 | "disp_cc_mdss_mdp_clk_src", |
| 784 | }, |
| 785 | .num_parents = 1, |
| 786 | .flags = CLK_SET_RATE_PARENT, |
| 787 | .ops = &clk_branch2_ops, |
| 788 | }, |
| 789 | }, |
| 790 | }; |
| 791 | |
| 792 | static struct clk_branch disp_cc_mdss_mdp_lut_clk = { |
| 793 | .halt_reg = 0x201c, |
| 794 | .halt_check = BRANCH_HALT, |
| 795 | .clkr = { |
| 796 | .enable_reg = 0x201c, |
| 797 | .enable_mask = BIT(0), |
| 798 | .hw.init = &(struct clk_init_data){ |
| 799 | .name = "disp_cc_mdss_mdp_lut_clk", |
| 800 | .parent_names = (const char *[]){ |
| 801 | "disp_cc_mdss_mdp_clk_src", |
| 802 | }, |
| 803 | .num_parents = 1, |
| 804 | .ops = &clk_branch2_ops, |
| 805 | }, |
| 806 | }, |
| 807 | }; |
| 808 | |
| 809 | static struct clk_branch disp_cc_mdss_pclk0_clk = { |
| 810 | .halt_reg = 0x2004, |
| 811 | .halt_check = BRANCH_HALT, |
| 812 | .clkr = { |
| 813 | .enable_reg = 0x2004, |
| 814 | .enable_mask = BIT(0), |
| 815 | .hw.init = &(struct clk_init_data){ |
| 816 | .name = "disp_cc_mdss_pclk0_clk", |
| 817 | .parent_names = (const char *[]){ |
| 818 | "disp_cc_mdss_pclk0_clk_src", |
| 819 | }, |
| 820 | .num_parents = 1, |
| 821 | .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
| 822 | .ops = &clk_branch2_ops, |
| 823 | }, |
| 824 | }, |
| 825 | }; |
| 826 | |
| 827 | static struct clk_branch disp_cc_mdss_pclk1_clk = { |
| 828 | .halt_reg = 0x2008, |
| 829 | .halt_check = BRANCH_HALT, |
| 830 | .clkr = { |
| 831 | .enable_reg = 0x2008, |
| 832 | .enable_mask = BIT(0), |
| 833 | .hw.init = &(struct clk_init_data){ |
| 834 | .name = "disp_cc_mdss_pclk1_clk", |
| 835 | .parent_names = (const char *[]){ |
| 836 | "disp_cc_mdss_pclk1_clk_src", |
| 837 | }, |
| 838 | .num_parents = 1, |
| 839 | .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
| 840 | .ops = &clk_branch2_ops, |
| 841 | }, |
| 842 | }, |
| 843 | }; |
| 844 | |
| 845 | static struct clk_branch disp_cc_mdss_qdss_at_clk = { |
| 846 | .halt_reg = 0x4010, |
| 847 | .halt_check = BRANCH_HALT, |
| 848 | .clkr = { |
| 849 | .enable_reg = 0x4010, |
| 850 | .enable_mask = BIT(0), |
| 851 | .hw.init = &(struct clk_init_data){ |
| 852 | .name = "disp_cc_mdss_qdss_at_clk", |
| 853 | .ops = &clk_branch2_ops, |
| 854 | }, |
| 855 | }, |
| 856 | }; |
| 857 | |
| 858 | static struct clk_branch disp_cc_mdss_qdss_tsctr_div8_clk = { |
| 859 | .halt_reg = 0x4014, |
| 860 | .halt_check = BRANCH_HALT, |
| 861 | .clkr = { |
| 862 | .enable_reg = 0x4014, |
| 863 | .enable_mask = BIT(0), |
| 864 | .hw.init = &(struct clk_init_data){ |
| 865 | .name = "disp_cc_mdss_qdss_tsctr_div8_clk", |
| 866 | .ops = &clk_branch2_ops, |
| 867 | }, |
| 868 | }, |
| 869 | }; |
| 870 | |
| 871 | static struct clk_branch disp_cc_mdss_rot_clk = { |
| 872 | .halt_reg = 0x2014, |
| 873 | .halt_check = BRANCH_HALT, |
| 874 | .clkr = { |
| 875 | .enable_reg = 0x2014, |
| 876 | .enable_mask = BIT(0), |
| 877 | .hw.init = &(struct clk_init_data){ |
| 878 | .name = "disp_cc_mdss_rot_clk", |
| 879 | .parent_names = (const char *[]){ |
| 880 | "disp_cc_mdss_rot_clk_src", |
| 881 | }, |
| 882 | .num_parents = 1, |
| 883 | .flags = CLK_SET_RATE_PARENT, |
| 884 | .ops = &clk_branch2_ops, |
| 885 | }, |
| 886 | }, |
| 887 | }; |
| 888 | |
| 889 | static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { |
| 890 | .halt_reg = 0x5004, |
| 891 | .halt_check = BRANCH_HALT, |
| 892 | .clkr = { |
| 893 | .enable_reg = 0x5004, |
| 894 | .enable_mask = BIT(0), |
| 895 | .hw.init = &(struct clk_init_data){ |
| 896 | .name = "disp_cc_mdss_rscc_ahb_clk", |
| 897 | .ops = &clk_branch2_ops, |
| 898 | }, |
| 899 | }, |
| 900 | }; |
| 901 | |
| 902 | static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { |
| 903 | .halt_reg = 0x5008, |
| 904 | .halt_check = BRANCH_HALT, |
| 905 | .clkr = { |
| 906 | .enable_reg = 0x5008, |
| 907 | .enable_mask = BIT(0), |
| 908 | .hw.init = &(struct clk_init_data){ |
| 909 | .name = "disp_cc_mdss_rscc_vsync_clk", |
| 910 | .parent_names = (const char *[]){ |
| 911 | "disp_cc_mdss_vsync_clk_src", |
| 912 | }, |
| 913 | .num_parents = 1, |
| 914 | .flags = CLK_SET_RATE_PARENT, |
| 915 | .ops = &clk_branch2_ops, |
| 916 | }, |
| 917 | }, |
| 918 | }; |
| 919 | |
| 920 | static struct clk_branch disp_cc_mdss_vsync_clk = { |
| 921 | .halt_reg = 0x2024, |
| 922 | .halt_check = BRANCH_HALT, |
| 923 | .clkr = { |
| 924 | .enable_reg = 0x2024, |
| 925 | .enable_mask = BIT(0), |
| 926 | .hw.init = &(struct clk_init_data){ |
| 927 | .name = "disp_cc_mdss_vsync_clk", |
| 928 | .parent_names = (const char *[]){ |
| 929 | "disp_cc_mdss_vsync_clk_src", |
| 930 | }, |
| 931 | .num_parents = 1, |
| 932 | .flags = CLK_SET_RATE_PARENT, |
| 933 | .ops = &clk_branch2_ops, |
| 934 | }, |
| 935 | }, |
| 936 | }; |
| 937 | |
| 938 | static struct clk_regmap *disp_cc_sdm845_clocks[] = { |
Deepak Katragadda | 24ee246 | 2016-12-16 14:26:38 -0800 | [diff] [blame] | 939 | [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, |
| 940 | [DISP_CC_MDSS_AXI_CLK] = &disp_cc_mdss_axi_clk.clkr, |
| 941 | [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, |
| 942 | [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, |
| 943 | [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, |
| 944 | [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = |
| 945 | &disp_cc_mdss_byte0_div_clk_src.clkr, |
| 946 | [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr, |
| 947 | [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr, |
| 948 | [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr, |
| 949 | [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = |
| 950 | &disp_cc_mdss_byte1_div_clk_src.clkr, |
| 951 | [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr, |
| 952 | [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr, |
| 953 | [DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr, |
| 954 | [DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = |
| 955 | &disp_cc_mdss_dp_crypto_clk_src.clkr, |
| 956 | [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr, |
| 957 | [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr, |
| 958 | [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = |
| 959 | &disp_cc_mdss_dp_link_div_clk_src.clkr, |
| 960 | [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr, |
| 961 | [DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr, |
| 962 | [DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] = |
| 963 | &disp_cc_mdss_dp_pixel1_clk_src.clkr, |
| 964 | [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr, |
| 965 | [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr, |
| 966 | [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, |
| 967 | [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, |
| 968 | [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr, |
| 969 | [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr, |
| 970 | [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, |
| 971 | [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, |
| 972 | [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, |
| 973 | [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, |
| 974 | [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, |
| 975 | [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr, |
| 976 | [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr, |
| 977 | [DISP_CC_MDSS_QDSS_AT_CLK] = &disp_cc_mdss_qdss_at_clk.clkr, |
| 978 | [DISP_CC_MDSS_QDSS_TSCTR_DIV8_CLK] = |
| 979 | &disp_cc_mdss_qdss_tsctr_div8_clk.clkr, |
| 980 | [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr, |
| 981 | [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr, |
| 982 | [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr, |
| 983 | [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr, |
| 984 | [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, |
| 985 | [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, |
| 986 | [DISP_CC_PLL0] = &disp_cc_pll0.clkr, |
| 987 | }; |
| 988 | |
| 989 | static const struct qcom_reset_map disp_cc_sdm845_resets[] = { |
| 990 | [DISP_CC_MDSS_CORE_BCR] = { 0x2000 }, |
| 991 | [DISP_CC_MDSS_GCC_CLOCKS_BCR] = { 0x4000 }, |
| 992 | [DISP_CC_MDSS_RSCC_BCR] = { 0x5000 }, |
| 993 | }; |
| 994 | |
| 995 | static const struct regmap_config disp_cc_sdm845_regmap_config = { |
| 996 | .reg_bits = 32, |
| 997 | .reg_stride = 4, |
| 998 | .val_bits = 32, |
| 999 | .max_register = 0x10000, |
| 1000 | .fast_io = true, |
| 1001 | }; |
| 1002 | |
| 1003 | static const struct qcom_cc_desc disp_cc_sdm845_desc = { |
| 1004 | .config = &disp_cc_sdm845_regmap_config, |
| 1005 | .clks = disp_cc_sdm845_clocks, |
| 1006 | .num_clks = ARRAY_SIZE(disp_cc_sdm845_clocks), |
| 1007 | .resets = disp_cc_sdm845_resets, |
| 1008 | .num_resets = ARRAY_SIZE(disp_cc_sdm845_resets), |
| 1009 | }; |
| 1010 | |
| 1011 | static const struct of_device_id disp_cc_sdm845_match_table[] = { |
| 1012 | { .compatible = "qcom,dispcc-sdm845" }, |
| 1013 | { } |
| 1014 | }; |
| 1015 | MODULE_DEVICE_TABLE(of, disp_cc_sdm845_match_table); |
| 1016 | |
| 1017 | static int disp_cc_sdm845_probe(struct platform_device *pdev) |
| 1018 | { |
| 1019 | struct regmap *regmap; |
| 1020 | int ret = 0; |
| 1021 | |
| 1022 | regmap = qcom_cc_map(pdev, &disp_cc_sdm845_desc); |
| 1023 | if (IS_ERR(regmap)) { |
| 1024 | pr_err("Failed to map the Display CC registers\n"); |
| 1025 | return PTR_ERR(regmap); |
| 1026 | } |
| 1027 | |
| 1028 | vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx"); |
| 1029 | if (IS_ERR(vdd_cx.regulator[0])) { |
| 1030 | if (!(PTR_ERR(vdd_cx.regulator[0]) == -EPROBE_DEFER)) |
| 1031 | dev_err(&pdev->dev, |
| 1032 | "Unable to get vdd_cx regulator\n"); |
| 1033 | return PTR_ERR(vdd_cx.regulator[0]); |
| 1034 | } |
| 1035 | |
| 1036 | clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); |
| 1037 | |
| 1038 | /* Enable clock gating for DSI and MDP clocks */ |
| 1039 | regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x7f0, 0x7f0); |
| 1040 | |
| 1041 | ret = qcom_cc_really_probe(pdev, &disp_cc_sdm845_desc, regmap); |
| 1042 | if (ret) { |
| 1043 | dev_err(&pdev->dev, "Failed to register Display CC clocks\n"); |
| 1044 | return ret; |
| 1045 | } |
| 1046 | |
| 1047 | dev_info(&pdev->dev, "Registered Display CC clocks\n"); |
| 1048 | return ret; |
| 1049 | } |
| 1050 | |
| 1051 | static struct platform_driver disp_cc_sdm845_driver = { |
| 1052 | .probe = disp_cc_sdm845_probe, |
| 1053 | .driver = { |
| 1054 | .name = "disp_cc-sdm845", |
| 1055 | .of_match_table = disp_cc_sdm845_match_table, |
| 1056 | }, |
| 1057 | }; |
| 1058 | |
| 1059 | static int __init disp_cc_sdm845_init(void) |
| 1060 | { |
| 1061 | return platform_driver_register(&disp_cc_sdm845_driver); |
| 1062 | } |
| 1063 | core_initcall(disp_cc_sdm845_init); |
| 1064 | |
| 1065 | static void __exit disp_cc_sdm845_exit(void) |
| 1066 | { |
| 1067 | platform_driver_unregister(&disp_cc_sdm845_driver); |
| 1068 | } |
| 1069 | module_exit(disp_cc_sdm845_exit); |
| 1070 | |
| 1071 | MODULE_DESCRIPTION("QTI DISP_CC SDM845 Driver"); |
| 1072 | MODULE_LICENSE("GPL v2"); |
| 1073 | MODULE_ALIAS("platform:disp_cc-sdm845"); |