David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1 | /* |
H Hartley Sweeten | bd474a0 | 2016-04-14 09:57:55 -0700 | [diff] [blame] | 2 | * Hardware driver for DAQ-STC based boards |
| 3 | * |
| 4 | * COMEDI - Linux Control and Measurement Device Interface |
| 5 | * Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org> |
| 6 | * Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 18 | |
| 19 | /* |
H Hartley Sweeten | bd474a0 | 2016-04-14 09:57:55 -0700 | [diff] [blame] | 20 | * This file is meant to be included by another file, e.g., |
| 21 | * ni_atmio.c or ni_pcimio.c. |
| 22 | * |
| 23 | * Interrupt support originally added by Truxton Fulton <trux@truxton.com> |
| 24 | * |
| 25 | * References (ftp://ftp.natinst.com/support/manuals): |
| 26 | * 340747b.pdf AT-MIO E series Register Level Programmer Manual |
| 27 | * 341079b.pdf PCI E Series RLPM |
| 28 | * 340934b.pdf DAQ-STC reference manual |
| 29 | * |
| 30 | * 67xx and 611x registers (ftp://ftp.ni.com/support/daq/mhddk/documentation/) |
| 31 | * release_ni611x.pdf |
| 32 | * release_ni67xx.pdf |
| 33 | * |
| 34 | * Other possibly relevant info: |
| 35 | * 320517c.pdf User manual (obsolete) |
| 36 | * 320517f.pdf User manual (new) |
| 37 | * 320889a.pdf delete |
| 38 | * 320906c.pdf maximum signal ratings |
| 39 | * 321066a.pdf about 16x |
| 40 | * 321791a.pdf discontinuation of at-mio-16e-10 rev. c |
| 41 | * 321808a.pdf about at-mio-16e-10 rev P |
| 42 | * 321837a.pdf discontinuation of at-mio-16de-10 rev d |
| 43 | * 321838a.pdf about at-mio-16de-10 rev N |
| 44 | * |
| 45 | * ISSUES: |
| 46 | * - the interrupt routine needs to be cleaned up |
| 47 | * |
| 48 | * 2006-02-07: S-Series PCI-6143: Support has been added but is not |
| 49 | * fully tested as yet. Terry Barnaby, BEAM Ltd. |
| 50 | */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 51 | |
Greg Kroah-Hartman | 25436dc | 2009-04-27 15:14:34 -0700 | [diff] [blame] | 52 | #include <linux/interrupt.h> |
Greg Kroah-Hartman | 4377a02 | 2009-10-12 14:58:16 -0700 | [diff] [blame] | 53 | #include <linux/sched.h> |
H Hartley Sweeten | 305591a | 2013-07-24 09:55:00 -0700 | [diff] [blame] | 54 | #include <linux/delay.h> |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 55 | #include "8255.h" |
| 56 | #include "mite.h" |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 57 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 58 | /* A timeout count */ |
| 59 | #define NI_TIMEOUT 1000 |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 60 | |
| 61 | /* Note: this table must match the ai_gain_* definitions */ |
| 62 | static const short ni_gainlkup[][16] = { |
| 63 | [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7, |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 64 | 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107}, |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 65 | [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107}, |
| 66 | [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7, |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 67 | 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107}, |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 68 | [ai_gain_4] = {0, 1, 4, 7}, |
| 69 | [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002, |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 70 | 0x003, 0x004, 0x005, 0x006}, |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 71 | [ai_gain_622x] = {0, 1, 4, 5}, |
| 72 | [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7}, |
| 73 | [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, |
| 74 | }; |
| 75 | |
H Hartley Sweeten | daed6c728 | 2013-12-09 17:30:59 -0700 | [diff] [blame] | 76 | static const struct comedi_lrange range_ni_E_ai = { |
| 77 | 16, { |
| 78 | BIP_RANGE(10), |
| 79 | BIP_RANGE(5), |
| 80 | BIP_RANGE(2.5), |
| 81 | BIP_RANGE(1), |
| 82 | BIP_RANGE(0.5), |
| 83 | BIP_RANGE(0.25), |
| 84 | BIP_RANGE(0.1), |
| 85 | BIP_RANGE(0.05), |
| 86 | UNI_RANGE(20), |
| 87 | UNI_RANGE(10), |
| 88 | UNI_RANGE(5), |
| 89 | UNI_RANGE(2), |
| 90 | UNI_RANGE(1), |
| 91 | UNI_RANGE(0.5), |
| 92 | UNI_RANGE(0.2), |
| 93 | UNI_RANGE(0.1) |
| 94 | } |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 95 | }; |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 96 | |
H Hartley Sweeten | daed6c728 | 2013-12-09 17:30:59 -0700 | [diff] [blame] | 97 | static const struct comedi_lrange range_ni_E_ai_limited = { |
| 98 | 8, { |
| 99 | BIP_RANGE(10), |
| 100 | BIP_RANGE(5), |
| 101 | BIP_RANGE(1), |
| 102 | BIP_RANGE(0.1), |
| 103 | UNI_RANGE(10), |
| 104 | UNI_RANGE(5), |
| 105 | UNI_RANGE(1), |
| 106 | UNI_RANGE(0.1) |
| 107 | } |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 108 | }; |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 109 | |
H Hartley Sweeten | daed6c728 | 2013-12-09 17:30:59 -0700 | [diff] [blame] | 110 | static const struct comedi_lrange range_ni_E_ai_limited14 = { |
| 111 | 14, { |
| 112 | BIP_RANGE(10), |
| 113 | BIP_RANGE(5), |
| 114 | BIP_RANGE(2), |
| 115 | BIP_RANGE(1), |
| 116 | BIP_RANGE(0.5), |
| 117 | BIP_RANGE(0.2), |
| 118 | BIP_RANGE(0.1), |
| 119 | UNI_RANGE(10), |
| 120 | UNI_RANGE(5), |
| 121 | UNI_RANGE(2), |
| 122 | UNI_RANGE(1), |
| 123 | UNI_RANGE(0.5), |
| 124 | UNI_RANGE(0.2), |
| 125 | UNI_RANGE(0.1) |
| 126 | } |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 127 | }; |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 128 | |
H Hartley Sweeten | daed6c728 | 2013-12-09 17:30:59 -0700 | [diff] [blame] | 129 | static const struct comedi_lrange range_ni_E_ai_bipolar4 = { |
| 130 | 4, { |
| 131 | BIP_RANGE(10), |
| 132 | BIP_RANGE(5), |
| 133 | BIP_RANGE(0.5), |
| 134 | BIP_RANGE(0.05) |
| 135 | } |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 136 | }; |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 137 | |
H Hartley Sweeten | daed6c728 | 2013-12-09 17:30:59 -0700 | [diff] [blame] | 138 | static const struct comedi_lrange range_ni_E_ai_611x = { |
| 139 | 8, { |
| 140 | BIP_RANGE(50), |
| 141 | BIP_RANGE(20), |
| 142 | BIP_RANGE(10), |
| 143 | BIP_RANGE(5), |
| 144 | BIP_RANGE(2), |
| 145 | BIP_RANGE(1), |
| 146 | BIP_RANGE(0.5), |
| 147 | BIP_RANGE(0.2) |
| 148 | } |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 149 | }; |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 150 | |
H Hartley Sweeten | daed6c728 | 2013-12-09 17:30:59 -0700 | [diff] [blame] | 151 | static const struct comedi_lrange range_ni_M_ai_622x = { |
| 152 | 4, { |
| 153 | BIP_RANGE(10), |
| 154 | BIP_RANGE(5), |
| 155 | BIP_RANGE(1), |
| 156 | BIP_RANGE(0.2) |
| 157 | } |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 158 | }; |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 159 | |
H Hartley Sweeten | daed6c728 | 2013-12-09 17:30:59 -0700 | [diff] [blame] | 160 | static const struct comedi_lrange range_ni_M_ai_628x = { |
| 161 | 7, { |
| 162 | BIP_RANGE(10), |
| 163 | BIP_RANGE(5), |
| 164 | BIP_RANGE(2), |
| 165 | BIP_RANGE(1), |
| 166 | BIP_RANGE(0.5), |
| 167 | BIP_RANGE(0.2), |
| 168 | BIP_RANGE(0.1) |
| 169 | } |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 170 | }; |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 171 | |
H Hartley Sweeten | daed6c728 | 2013-12-09 17:30:59 -0700 | [diff] [blame] | 172 | static const struct comedi_lrange range_ni_E_ao_ext = { |
| 173 | 4, { |
| 174 | BIP_RANGE(10), |
| 175 | UNI_RANGE(10), |
| 176 | RANGE_ext(-1, 1), |
| 177 | RANGE_ext(0, 1) |
| 178 | } |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 179 | }; |
| 180 | |
Bill Pemberton | 9ced1de | 2009-03-16 22:05:31 -0400 | [diff] [blame] | 181 | static const struct comedi_lrange *const ni_range_lkup[] = { |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 182 | [ai_gain_16] = &range_ni_E_ai, |
| 183 | [ai_gain_8] = &range_ni_E_ai_limited, |
| 184 | [ai_gain_14] = &range_ni_E_ai_limited14, |
| 185 | [ai_gain_4] = &range_ni_E_ai_bipolar4, |
| 186 | [ai_gain_611x] = &range_ni_E_ai_611x, |
| 187 | [ai_gain_622x] = &range_ni_M_ai_622x, |
| 188 | [ai_gain_628x] = &range_ni_M_ai_628x, |
H Hartley Sweeten | 50708d9 | 2013-04-03 13:39:34 -0700 | [diff] [blame] | 189 | [ai_gain_6143] = &range_bipolar5 |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 190 | }; |
| 191 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 192 | enum aimodes { |
| 193 | AIMODE_NONE = 0, |
| 194 | AIMODE_HALF_FULL = 1, |
| 195 | AIMODE_SCAN = 2, |
| 196 | AIMODE_SAMPLE = 3, |
| 197 | }; |
| 198 | |
| 199 | enum ni_common_subdevices { |
| 200 | NI_AI_SUBDEV, |
| 201 | NI_AO_SUBDEV, |
| 202 | NI_DIO_SUBDEV, |
| 203 | NI_8255_DIO_SUBDEV, |
| 204 | NI_UNUSED_SUBDEV, |
| 205 | NI_CALIBRATION_SUBDEV, |
| 206 | NI_EEPROM_SUBDEV, |
| 207 | NI_PFI_DIO_SUBDEV, |
| 208 | NI_CS5529_CALIBRATION_SUBDEV, |
| 209 | NI_SERIAL_SUBDEV, |
| 210 | NI_RTSI_SUBDEV, |
| 211 | NI_GPCT0_SUBDEV, |
| 212 | NI_GPCT1_SUBDEV, |
| 213 | NI_FREQ_OUT_SUBDEV, |
| 214 | NI_NUM_SUBDEVICES |
| 215 | }; |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 216 | |
H Hartley Sweeten | 0b235d5 | 2016-04-14 09:57:59 -0700 | [diff] [blame] | 217 | #define NI_GPCT_SUBDEV(x) (NI_GPCT0_SUBDEV + (x)) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 218 | |
| 219 | enum timebase_nanoseconds { |
| 220 | TIMEBASE_1_NS = 50, |
| 221 | TIMEBASE_2_NS = 10000 |
| 222 | }; |
| 223 | |
| 224 | #define SERIAL_DISABLED 0 |
| 225 | #define SERIAL_600NS 600 |
| 226 | #define SERIAL_1_2US 1200 |
| 227 | #define SERIAL_10US 10000 |
| 228 | |
| 229 | static const int num_adc_stages_611x = 3; |
| 230 | |
H Hartley Sweeten | 546615f | 2016-04-14 09:57:54 -0700 | [diff] [blame] | 231 | static void ni_writel(struct comedi_device *dev, unsigned int data, int reg) |
H Hartley Sweeten | 5a92cac | 2014-06-19 10:20:35 -0700 | [diff] [blame] | 232 | { |
H Hartley Sweeten | 5f8a5f4 | 2014-07-29 15:01:38 -0700 | [diff] [blame] | 233 | if (dev->mmio) |
| 234 | writel(data, dev->mmio + reg); |
H Hartley Sweeten | bd3a3cd | 2016-03-22 10:04:48 -0700 | [diff] [blame] | 235 | else |
| 236 | outl(data, dev->iobase + reg); |
H Hartley Sweeten | 5a92cac | 2014-06-19 10:20:35 -0700 | [diff] [blame] | 237 | } |
| 238 | |
H Hartley Sweeten | 546615f | 2016-04-14 09:57:54 -0700 | [diff] [blame] | 239 | static void ni_writew(struct comedi_device *dev, unsigned int data, int reg) |
H Hartley Sweeten | 5a92cac | 2014-06-19 10:20:35 -0700 | [diff] [blame] | 240 | { |
H Hartley Sweeten | 5f8a5f4 | 2014-07-29 15:01:38 -0700 | [diff] [blame] | 241 | if (dev->mmio) |
| 242 | writew(data, dev->mmio + reg); |
H Hartley Sweeten | bd3a3cd | 2016-03-22 10:04:48 -0700 | [diff] [blame] | 243 | else |
| 244 | outw(data, dev->iobase + reg); |
H Hartley Sweeten | 5a92cac | 2014-06-19 10:20:35 -0700 | [diff] [blame] | 245 | } |
| 246 | |
H Hartley Sweeten | 546615f | 2016-04-14 09:57:54 -0700 | [diff] [blame] | 247 | static void ni_writeb(struct comedi_device *dev, unsigned int data, int reg) |
H Hartley Sweeten | 5a92cac | 2014-06-19 10:20:35 -0700 | [diff] [blame] | 248 | { |
H Hartley Sweeten | 5f8a5f4 | 2014-07-29 15:01:38 -0700 | [diff] [blame] | 249 | if (dev->mmio) |
| 250 | writeb(data, dev->mmio + reg); |
H Hartley Sweeten | bd3a3cd | 2016-03-22 10:04:48 -0700 | [diff] [blame] | 251 | else |
| 252 | outb(data, dev->iobase + reg); |
H Hartley Sweeten | 5a92cac | 2014-06-19 10:20:35 -0700 | [diff] [blame] | 253 | } |
| 254 | |
H Hartley Sweeten | 546615f | 2016-04-14 09:57:54 -0700 | [diff] [blame] | 255 | static unsigned int ni_readl(struct comedi_device *dev, int reg) |
H Hartley Sweeten | 5a92cac | 2014-06-19 10:20:35 -0700 | [diff] [blame] | 256 | { |
H Hartley Sweeten | 5f8a5f4 | 2014-07-29 15:01:38 -0700 | [diff] [blame] | 257 | if (dev->mmio) |
| 258 | return readl(dev->mmio + reg); |
H Hartley Sweeten | 0953ee4 | 2014-07-16 10:43:34 -0700 | [diff] [blame] | 259 | |
| 260 | return inl(dev->iobase + reg); |
H Hartley Sweeten | 5a92cac | 2014-06-19 10:20:35 -0700 | [diff] [blame] | 261 | } |
| 262 | |
H Hartley Sweeten | 546615f | 2016-04-14 09:57:54 -0700 | [diff] [blame] | 263 | static unsigned int ni_readw(struct comedi_device *dev, int reg) |
H Hartley Sweeten | 5a92cac | 2014-06-19 10:20:35 -0700 | [diff] [blame] | 264 | { |
H Hartley Sweeten | 5f8a5f4 | 2014-07-29 15:01:38 -0700 | [diff] [blame] | 265 | if (dev->mmio) |
| 266 | return readw(dev->mmio + reg); |
H Hartley Sweeten | 0953ee4 | 2014-07-16 10:43:34 -0700 | [diff] [blame] | 267 | |
| 268 | return inw(dev->iobase + reg); |
H Hartley Sweeten | 5a92cac | 2014-06-19 10:20:35 -0700 | [diff] [blame] | 269 | } |
| 270 | |
H Hartley Sweeten | 546615f | 2016-04-14 09:57:54 -0700 | [diff] [blame] | 271 | static unsigned int ni_readb(struct comedi_device *dev, int reg) |
H Hartley Sweeten | 5a92cac | 2014-06-19 10:20:35 -0700 | [diff] [blame] | 272 | { |
H Hartley Sweeten | 5f8a5f4 | 2014-07-29 15:01:38 -0700 | [diff] [blame] | 273 | if (dev->mmio) |
| 274 | return readb(dev->mmio + reg); |
H Hartley Sweeten | 0953ee4 | 2014-07-16 10:43:34 -0700 | [diff] [blame] | 275 | |
| 276 | return inb(dev->iobase + reg); |
H Hartley Sweeten | 5a92cac | 2014-06-19 10:20:35 -0700 | [diff] [blame] | 277 | } |
| 278 | |
H Hartley Sweeten | b30f0d0 | 2014-06-19 10:20:37 -0700 | [diff] [blame] | 279 | /* |
| 280 | * We automatically take advantage of STC registers that can be |
| 281 | * read/written directly in the I/O space of the board. |
| 282 | * |
| 283 | * The AT-MIO and DAQCard devices map the low 8 STC registers to |
| 284 | * iobase+reg*2. |
| 285 | * |
| 286 | * Most PCIMIO devices also map the low 8 STC registers but the |
| 287 | * 611x devices map the read registers to iobase+(addr-1)*2. |
| 288 | * For now non-windowed STC access is disabled if a PCIMIO device |
| 289 | * is detected (devpriv->mite has been initialized). |
| 290 | * |
| 291 | * The M series devices do not used windowed registers for the |
| 292 | * STC registers. The functions below handle the mapping of the |
| 293 | * windowed STC registers to the m series register offsets. |
| 294 | */ |
H Hartley Sweeten | 00b14b1 | 2014-06-19 10:20:34 -0700 | [diff] [blame] | 295 | |
H Hartley Sweeten | 05dd0c9 | 2015-05-01 14:58:26 -0700 | [diff] [blame] | 296 | struct mio_regmap { |
| 297 | unsigned int mio_reg; |
| 298 | int size; |
| 299 | }; |
H Hartley Sweeten | b30f0d0 | 2014-06-19 10:20:37 -0700 | [diff] [blame] | 300 | |
H Hartley Sweeten | 05dd0c9 | 2015-05-01 14:58:26 -0700 | [diff] [blame] | 301 | static const struct mio_regmap m_series_stc_write_regmap[] = { |
H Hartley Sweeten | 480456d | 2015-05-01 14:58:54 -0700 | [diff] [blame] | 302 | [NISTC_INTA_ACK_REG] = { 0x104, 2 }, |
H Hartley Sweeten | 4a6de832 | 2015-05-01 14:58:55 -0700 | [diff] [blame] | 303 | [NISTC_INTB_ACK_REG] = { 0x106, 2 }, |
H Hartley Sweeten | a1da35a | 2015-05-01 14:58:56 -0700 | [diff] [blame] | 304 | [NISTC_AI_CMD2_REG] = { 0x108, 2 }, |
H Hartley Sweeten | 382b3c4 | 2015-05-01 14:58:57 -0700 | [diff] [blame] | 305 | [NISTC_AO_CMD2_REG] = { 0x10a, 2 }, |
H Hartley Sweeten | 5fa2fa4 | 2015-05-01 14:58:58 -0700 | [diff] [blame] | 306 | [NISTC_G0_CMD_REG] = { 0x10c, 2 }, |
| 307 | [NISTC_G1_CMD_REG] = { 0x10e, 2 }, |
H Hartley Sweeten | 4c4d715 | 2015-05-01 14:58:59 -0700 | [diff] [blame] | 308 | [NISTC_AI_CMD1_REG] = { 0x110, 2 }, |
H Hartley Sweeten | 7bfcc2d | 2015-05-01 14:59:00 -0700 | [diff] [blame] | 309 | [NISTC_AO_CMD1_REG] = { 0x112, 2 }, |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 310 | /* |
H Hartley Sweeten | 05aafee | 2015-05-01 14:59:01 -0700 | [diff] [blame] | 311 | * NISTC_DIO_OUT_REG maps to: |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 312 | * { NI_M_DIO_REG, 4 } and { NI_M_SCXI_SER_DO_REG, 1 } |
| 313 | */ |
H Hartley Sweeten | 05aafee | 2015-05-01 14:59:01 -0700 | [diff] [blame] | 314 | [NISTC_DIO_OUT_REG] = { 0, 0 }, /* DOES NOT MAP CLEANLY */ |
H Hartley Sweeten | 59a97c3 | 2015-05-01 14:59:02 -0700 | [diff] [blame] | 315 | [NISTC_DIO_CTRL_REG] = { 0, 0 }, /* DOES NOT MAP CLEANLY */ |
H Hartley Sweeten | bd358f5 | 2015-05-01 14:59:03 -0700 | [diff] [blame] | 316 | [NISTC_AI_MODE1_REG] = { 0x118, 2 }, |
H Hartley Sweeten | b134cc5 | 2015-05-01 14:59:04 -0700 | [diff] [blame] | 317 | [NISTC_AI_MODE2_REG] = { 0x11a, 2 }, |
H Hartley Sweeten | a2c5373 | 2015-05-01 14:59:05 -0700 | [diff] [blame] | 318 | [NISTC_AI_SI_LOADA_REG] = { 0x11c, 4 }, |
| 319 | [NISTC_AI_SI_LOADB_REG] = { 0x120, 4 }, |
| 320 | [NISTC_AI_SC_LOADA_REG] = { 0x124, 4 }, |
| 321 | [NISTC_AI_SC_LOADB_REG] = { 0x128, 4 }, |
| 322 | [NISTC_AI_SI2_LOADA_REG] = { 0x12c, 4 }, |
| 323 | [NISTC_AI_SI2_LOADB_REG] = { 0x130, 4 }, |
H Hartley Sweeten | aff2700 | 2015-05-01 14:59:06 -0700 | [diff] [blame] | 324 | [NISTC_G0_MODE_REG] = { 0x134, 2 }, |
| 325 | [NISTC_G1_MODE_REG] = { 0x136, 2 }, |
| 326 | [NISTC_G0_LOADA_REG] = { 0x138, 4 }, |
| 327 | [NISTC_G0_LOADB_REG] = { 0x13c, 4 }, |
| 328 | [NISTC_G1_LOADA_REG] = { 0x140, 4 }, |
| 329 | [NISTC_G1_LOADB_REG] = { 0x144, 4 }, |
| 330 | [NISTC_G0_INPUT_SEL_REG] = { 0x148, 2 }, |
| 331 | [NISTC_G1_INPUT_SEL_REG] = { 0x14a, 2 }, |
H Hartley Sweeten | 4e5ce0a | 2015-05-01 14:59:07 -0700 | [diff] [blame] | 332 | [NISTC_AO_MODE1_REG] = { 0x14c, 2 }, |
H Hartley Sweeten | ec8bf72 | 2015-05-01 14:59:08 -0700 | [diff] [blame] | 333 | [NISTC_AO_MODE2_REG] = { 0x14e, 2 }, |
H Hartley Sweeten | 37e0ece | 2015-05-01 14:59:09 -0700 | [diff] [blame] | 334 | [NISTC_AO_UI_LOADA_REG] = { 0x150, 4 }, |
| 335 | [NISTC_AO_UI_LOADB_REG] = { 0x154, 4 }, |
| 336 | [NISTC_AO_BC_LOADA_REG] = { 0x158, 4 }, |
| 337 | [NISTC_AO_BC_LOADB_REG] = { 0x15c, 4 }, |
| 338 | [NISTC_AO_UC_LOADA_REG] = { 0x160, 4 }, |
| 339 | [NISTC_AO_UC_LOADB_REG] = { 0x164, 4 }, |
H Hartley Sweeten | a47fc02 | 2015-05-01 14:59:10 -0700 | [diff] [blame] | 340 | [NISTC_CLK_FOUT_REG] = { 0x170, 2 }, |
H Hartley Sweeten | 5ecadf8 | 2015-05-01 14:59:12 -0700 | [diff] [blame] | 341 | [NISTC_IO_BIDIR_PIN_REG] = { 0x172, 2 }, |
H Hartley Sweeten | a4f18b1 | 2015-05-01 14:59:14 -0700 | [diff] [blame] | 342 | [NISTC_RTSI_TRIG_DIR_REG] = { 0x174, 2 }, |
H Hartley Sweeten | d8f62c4 | 2015-05-01 14:59:15 -0700 | [diff] [blame] | 343 | [NISTC_INT_CTRL_REG] = { 0x176, 2 }, |
H Hartley Sweeten | aa9d73b | 2015-05-01 14:59:16 -0700 | [diff] [blame] | 344 | [NISTC_AI_OUT_CTRL_REG] = { 0x178, 2 }, |
H Hartley Sweeten | 27cf6c0 | 2015-05-01 14:59:17 -0700 | [diff] [blame] | 345 | [NISTC_ATRIG_ETC_REG] = { 0x17a, 2 }, |
H Hartley Sweeten | 3e90889 | 2015-05-01 14:59:18 -0700 | [diff] [blame] | 346 | [NISTC_AI_START_STOP_REG] = { 0x17c, 2 }, |
H Hartley Sweeten | f878071 | 2015-05-01 14:59:19 -0700 | [diff] [blame] | 347 | [NISTC_AI_TRIG_SEL_REG] = { 0x17e, 2 }, |
H Hartley Sweeten | af5102a | 2015-05-01 14:59:20 -0700 | [diff] [blame] | 348 | [NISTC_AI_DIV_LOADA_REG] = { 0x180, 4 }, |
H Hartley Sweeten | 2b6285da | 2015-05-01 14:59:21 -0700 | [diff] [blame] | 349 | [NISTC_AO_START_SEL_REG] = { 0x184, 2 }, |
H Hartley Sweeten | f21844d | 2015-05-01 14:59:22 -0700 | [diff] [blame] | 350 | [NISTC_AO_TRIG_SEL_REG] = { 0x186, 2 }, |
H Hartley Sweeten | 38aba4c | 2015-05-01 14:59:23 -0700 | [diff] [blame] | 351 | [NISTC_G0_AUTOINC_REG] = { 0x188, 2 }, |
| 352 | [NISTC_G1_AUTOINC_REG] = { 0x18a, 2 }, |
H Hartley Sweeten | 72bca4f | 2015-05-01 14:59:24 -0700 | [diff] [blame] | 353 | [NISTC_AO_MODE3_REG] = { 0x18c, 2 }, |
H Hartley Sweeten | 707502f | 2015-05-01 14:59:25 -0700 | [diff] [blame] | 354 | [NISTC_RESET_REG] = { 0x190, 2 }, |
H Hartley Sweeten | 5cca26a | 2015-05-01 14:59:26 -0700 | [diff] [blame] | 355 | [NISTC_INTA_ENA_REG] = { 0x192, 2 }, |
H Hartley Sweeten | d84e9c3 | 2015-05-01 14:59:27 -0700 | [diff] [blame] | 356 | [NISTC_INTA2_ENA_REG] = { 0, 0 }, /* E-Series only */ |
H Hartley Sweeten | 4c9c1d2 | 2015-05-01 14:59:28 -0700 | [diff] [blame] | 357 | [NISTC_INTB_ENA_REG] = { 0x196, 2 }, |
H Hartley Sweeten | 04b6846 | 2015-05-01 14:59:29 -0700 | [diff] [blame] | 358 | [NISTC_INTB2_ENA_REG] = { 0, 0 }, /* E-Series only */ |
H Hartley Sweeten | c1b7403 | 2015-05-01 14:59:30 -0700 | [diff] [blame] | 359 | [NISTC_AI_PERSONAL_REG] = { 0x19a, 2 }, |
H Hartley Sweeten | 63ff3f2 | 2015-05-01 14:59:31 -0700 | [diff] [blame] | 360 | [NISTC_AO_PERSONAL_REG] = { 0x19c, 2 }, |
H Hartley Sweeten | 390bc6f | 2015-05-01 14:59:32 -0700 | [diff] [blame] | 361 | [NISTC_RTSI_TRIGA_OUT_REG] = { 0x19e, 2 }, |
| 362 | [NISTC_RTSI_TRIGB_OUT_REG] = { 0x1a0, 2 }, |
H Hartley Sweeten | 24a11ba | 2015-05-01 14:59:33 -0700 | [diff] [blame] | 363 | [NISTC_RTSI_BOARD_REG] = { 0, 0 }, /* Unknown */ |
H Hartley Sweeten | 8102f3d | 2015-05-01 14:59:34 -0700 | [diff] [blame] | 364 | [NISTC_CFG_MEM_CLR_REG] = { 0x1a4, 2 }, |
| 365 | [NISTC_ADC_FIFO_CLR_REG] = { 0x1a6, 2 }, |
| 366 | [NISTC_DAC_FIFO_CLR_REG] = { 0x1a8, 2 }, |
H Hartley Sweeten | 5bd1c72 | 2015-05-01 14:59:35 -0700 | [diff] [blame] | 367 | [NISTC_AO_OUT_CTRL_REG] = { 0x1ac, 2 }, |
H Hartley Sweeten | c7edadc | 2015-05-01 14:59:36 -0700 | [diff] [blame] | 368 | [NISTC_AI_MODE3_REG] = { 0x1ae, 2 }, |
H Hartley Sweeten | 05dd0c9 | 2015-05-01 14:58:26 -0700 | [diff] [blame] | 369 | }; |
| 370 | |
| 371 | static void m_series_stc_write(struct comedi_device *dev, |
| 372 | unsigned int data, unsigned int reg) |
| 373 | { |
| 374 | const struct mio_regmap *regmap; |
| 375 | |
| 376 | if (reg < ARRAY_SIZE(m_series_stc_write_regmap)) { |
| 377 | regmap = &m_series_stc_write_regmap[reg]; |
| 378 | } else { |
| 379 | dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n", |
H Hartley Sweeten | b30f0d0 | 2014-06-19 10:20:37 -0700 | [diff] [blame] | 380 | __func__, reg); |
| 381 | return; |
| 382 | } |
H Hartley Sweeten | b30f0d0 | 2014-06-19 10:20:37 -0700 | [diff] [blame] | 383 | |
H Hartley Sweeten | 05dd0c9 | 2015-05-01 14:58:26 -0700 | [diff] [blame] | 384 | switch (regmap->size) { |
| 385 | case 4: |
| 386 | ni_writel(dev, data, regmap->mio_reg); |
H Hartley Sweeten | b30f0d0 | 2014-06-19 10:20:37 -0700 | [diff] [blame] | 387 | break; |
H Hartley Sweeten | 05dd0c9 | 2015-05-01 14:58:26 -0700 | [diff] [blame] | 388 | case 2: |
| 389 | ni_writew(dev, data, regmap->mio_reg); |
H Hartley Sweeten | b30f0d0 | 2014-06-19 10:20:37 -0700 | [diff] [blame] | 390 | break; |
H Hartley Sweeten | b30f0d0 | 2014-06-19 10:20:37 -0700 | [diff] [blame] | 391 | default: |
H Hartley Sweeten | 05dd0c9 | 2015-05-01 14:58:26 -0700 | [diff] [blame] | 392 | dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n", |
H Hartley Sweeten | b30f0d0 | 2014-06-19 10:20:37 -0700 | [diff] [blame] | 393 | __func__, reg); |
H Hartley Sweeten | 05dd0c9 | 2015-05-01 14:58:26 -0700 | [diff] [blame] | 394 | break; |
H Hartley Sweeten | b30f0d0 | 2014-06-19 10:20:37 -0700 | [diff] [blame] | 395 | } |
H Hartley Sweeten | b30f0d0 | 2014-06-19 10:20:37 -0700 | [diff] [blame] | 396 | } |
| 397 | |
H Hartley Sweeten | 05dd0c9 | 2015-05-01 14:58:26 -0700 | [diff] [blame] | 398 | static const struct mio_regmap m_series_stc_read_regmap[] = { |
H Hartley Sweeten | 7b14fff | 2015-05-01 14:59:37 -0700 | [diff] [blame] | 399 | [NISTC_AI_STATUS1_REG] = { 0x104, 2 }, |
H Hartley Sweeten | d123ee3 | 2015-05-01 14:59:38 -0700 | [diff] [blame] | 400 | [NISTC_AO_STATUS1_REG] = { 0x106, 2 }, |
H Hartley Sweeten | 7f0e1ba | 2015-05-01 14:59:39 -0700 | [diff] [blame] | 401 | [NISTC_G01_STATUS_REG] = { 0x108, 2 }, |
H Hartley Sweeten | 3ca18fe | 2015-05-01 14:59:40 -0700 | [diff] [blame] | 402 | [NISTC_AI_STATUS2_REG] = { 0, 0 }, /* Unknown */ |
H Hartley Sweeten | 63b2bb0 | 2015-05-01 14:59:41 -0700 | [diff] [blame] | 403 | [NISTC_AO_STATUS2_REG] = { 0x10c, 2 }, |
H Hartley Sweeten | 6f764a4 | 2015-05-01 14:59:42 -0700 | [diff] [blame] | 404 | [NISTC_DIO_IN_REG] = { 0, 0 }, /* Unknown */ |
H Hartley Sweeten | 27650d9 | 2015-05-01 14:59:43 -0700 | [diff] [blame] | 405 | [NISTC_G0_HW_SAVE_REG] = { 0x110, 4 }, |
| 406 | [NISTC_G1_HW_SAVE_REG] = { 0x114, 4 }, |
H Hartley Sweeten | d9c4115 | 2015-05-01 14:59:44 -0700 | [diff] [blame] | 407 | [NISTC_G0_SAVE_REG] = { 0x118, 4 }, |
| 408 | [NISTC_G1_SAVE_REG] = { 0x11c, 4 }, |
H Hartley Sweeten | 2c090ac | 2015-05-01 14:59:45 -0700 | [diff] [blame] | 409 | [NISTC_AO_UI_SAVE_REG] = { 0x120, 4 }, |
| 410 | [NISTC_AO_BC_SAVE_REG] = { 0x124, 4 }, |
| 411 | [NISTC_AO_UC_SAVE_REG] = { 0x128, 4 }, |
H Hartley Sweeten | d3fed08 | 2015-05-01 14:59:46 -0700 | [diff] [blame] | 412 | [NISTC_STATUS1_REG] = { 0x136, 2 }, |
H Hartley Sweeten | 8fbb015 | 2015-05-01 14:59:47 -0700 | [diff] [blame] | 413 | [NISTC_DIO_SERIAL_IN_REG] = { 0x009, 1 }, |
H Hartley Sweeten | bab382e | 2015-05-01 14:59:48 -0700 | [diff] [blame] | 414 | [NISTC_STATUS2_REG] = { 0x13a, 2 }, |
H Hartley Sweeten | 549835c | 2015-05-01 14:59:49 -0700 | [diff] [blame] | 415 | [NISTC_AI_SI_SAVE_REG] = { 0x180, 4 }, |
| 416 | [NISTC_AI_SC_SAVE_REG] = { 0x184, 4 }, |
H Hartley Sweeten | 05dd0c9 | 2015-05-01 14:58:26 -0700 | [diff] [blame] | 417 | }; |
H Hartley Sweeten | b30f0d0 | 2014-06-19 10:20:37 -0700 | [diff] [blame] | 418 | |
H Hartley Sweeten | 05dd0c9 | 2015-05-01 14:58:26 -0700 | [diff] [blame] | 419 | static unsigned int m_series_stc_read(struct comedi_device *dev, |
| 420 | unsigned int reg) |
| 421 | { |
| 422 | const struct mio_regmap *regmap; |
| 423 | |
| 424 | if (reg < ARRAY_SIZE(m_series_stc_read_regmap)) { |
| 425 | regmap = &m_series_stc_read_regmap[reg]; |
| 426 | } else { |
| 427 | dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n", |
H Hartley Sweeten | b30f0d0 | 2014-06-19 10:20:37 -0700 | [diff] [blame] | 428 | __func__, reg); |
| 429 | return 0; |
| 430 | } |
H Hartley Sweeten | b30f0d0 | 2014-06-19 10:20:37 -0700 | [diff] [blame] | 431 | |
H Hartley Sweeten | 05dd0c9 | 2015-05-01 14:58:26 -0700 | [diff] [blame] | 432 | switch (regmap->size) { |
| 433 | case 4: |
| 434 | return ni_readl(dev, regmap->mio_reg); |
| 435 | case 2: |
| 436 | return ni_readw(dev, regmap->mio_reg); |
| 437 | case 1: |
| 438 | return ni_readb(dev, regmap->mio_reg); |
H Hartley Sweeten | b30f0d0 | 2014-06-19 10:20:37 -0700 | [diff] [blame] | 439 | default: |
H Hartley Sweeten | 05dd0c9 | 2015-05-01 14:58:26 -0700 | [diff] [blame] | 440 | dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n", |
H Hartley Sweeten | b30f0d0 | 2014-06-19 10:20:37 -0700 | [diff] [blame] | 441 | __func__, reg); |
| 442 | return 0; |
| 443 | } |
H Hartley Sweeten | 00b14b1 | 2014-06-19 10:20:34 -0700 | [diff] [blame] | 444 | } |
| 445 | |
H Hartley Sweeten | 546615f | 2016-04-14 09:57:54 -0700 | [diff] [blame] | 446 | static void ni_stc_writew(struct comedi_device *dev, |
| 447 | unsigned int data, int reg) |
H Hartley Sweeten | 00b14b1 | 2014-06-19 10:20:34 -0700 | [diff] [blame] | 448 | { |
| 449 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | b30f0d0 | 2014-06-19 10:20:37 -0700 | [diff] [blame] | 450 | unsigned long flags; |
H Hartley Sweeten | 00b14b1 | 2014-06-19 10:20:34 -0700 | [diff] [blame] | 451 | |
H Hartley Sweeten | b30f0d0 | 2014-06-19 10:20:37 -0700 | [diff] [blame] | 452 | if (devpriv->is_m_series) { |
H Hartley Sweeten | 05dd0c9 | 2015-05-01 14:58:26 -0700 | [diff] [blame] | 453 | m_series_stc_write(dev, data, reg); |
H Hartley Sweeten | b30f0d0 | 2014-06-19 10:20:37 -0700 | [diff] [blame] | 454 | } else { |
| 455 | spin_lock_irqsave(&devpriv->window_lock, flags); |
| 456 | if (!devpriv->mite && reg < 8) { |
| 457 | ni_writew(dev, data, reg * 2); |
| 458 | } else { |
H Hartley Sweeten | 4f809ff | 2015-05-01 14:59:51 -0700 | [diff] [blame] | 459 | ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG); |
| 460 | ni_writew(dev, data, NI_E_STC_WINDOW_DATA_REG); |
H Hartley Sweeten | b30f0d0 | 2014-06-19 10:20:37 -0700 | [diff] [blame] | 461 | } |
| 462 | spin_unlock_irqrestore(&devpriv->window_lock, flags); |
| 463 | } |
H Hartley Sweeten | 00b14b1 | 2014-06-19 10:20:34 -0700 | [diff] [blame] | 464 | } |
| 465 | |
H Hartley Sweeten | 546615f | 2016-04-14 09:57:54 -0700 | [diff] [blame] | 466 | static void ni_stc_writel(struct comedi_device *dev, |
| 467 | unsigned int data, int reg) |
H Hartley Sweeten | 00b14b1 | 2014-06-19 10:20:34 -0700 | [diff] [blame] | 468 | { |
| 469 | struct ni_private *devpriv = dev->private; |
| 470 | |
H Hartley Sweeten | b30f0d0 | 2014-06-19 10:20:37 -0700 | [diff] [blame] | 471 | if (devpriv->is_m_series) { |
H Hartley Sweeten | 05dd0c9 | 2015-05-01 14:58:26 -0700 | [diff] [blame] | 472 | m_series_stc_write(dev, data, reg); |
H Hartley Sweeten | b30f0d0 | 2014-06-19 10:20:37 -0700 | [diff] [blame] | 473 | } else { |
| 474 | ni_stc_writew(dev, data >> 16, reg); |
| 475 | ni_stc_writew(dev, data & 0xffff, reg + 1); |
| 476 | } |
H Hartley Sweeten | 00b14b1 | 2014-06-19 10:20:34 -0700 | [diff] [blame] | 477 | } |
| 478 | |
H Hartley Sweeten | 546615f | 2016-04-14 09:57:54 -0700 | [diff] [blame] | 479 | static unsigned int ni_stc_readw(struct comedi_device *dev, int reg) |
H Hartley Sweeten | 00b14b1 | 2014-06-19 10:20:34 -0700 | [diff] [blame] | 480 | { |
| 481 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | b30f0d0 | 2014-06-19 10:20:37 -0700 | [diff] [blame] | 482 | unsigned long flags; |
H Hartley Sweeten | 546615f | 2016-04-14 09:57:54 -0700 | [diff] [blame] | 483 | unsigned int val; |
H Hartley Sweeten | 00b14b1 | 2014-06-19 10:20:34 -0700 | [diff] [blame] | 484 | |
H Hartley Sweeten | b30f0d0 | 2014-06-19 10:20:37 -0700 | [diff] [blame] | 485 | if (devpriv->is_m_series) { |
H Hartley Sweeten | 05dd0c9 | 2015-05-01 14:58:26 -0700 | [diff] [blame] | 486 | val = m_series_stc_read(dev, reg); |
H Hartley Sweeten | b30f0d0 | 2014-06-19 10:20:37 -0700 | [diff] [blame] | 487 | } else { |
| 488 | spin_lock_irqsave(&devpriv->window_lock, flags); |
| 489 | if (!devpriv->mite && reg < 8) { |
| 490 | val = ni_readw(dev, reg * 2); |
| 491 | } else { |
H Hartley Sweeten | 4f809ff | 2015-05-01 14:59:51 -0700 | [diff] [blame] | 492 | ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG); |
| 493 | val = ni_readw(dev, NI_E_STC_WINDOW_DATA_REG); |
H Hartley Sweeten | b30f0d0 | 2014-06-19 10:20:37 -0700 | [diff] [blame] | 494 | } |
| 495 | spin_unlock_irqrestore(&devpriv->window_lock, flags); |
| 496 | } |
| 497 | return val; |
| 498 | } |
| 499 | |
H Hartley Sweeten | 546615f | 2016-04-14 09:57:54 -0700 | [diff] [blame] | 500 | static unsigned int ni_stc_readl(struct comedi_device *dev, int reg) |
H Hartley Sweeten | b30f0d0 | 2014-06-19 10:20:37 -0700 | [diff] [blame] | 501 | { |
| 502 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | 546615f | 2016-04-14 09:57:54 -0700 | [diff] [blame] | 503 | unsigned int val; |
H Hartley Sweeten | b30f0d0 | 2014-06-19 10:20:37 -0700 | [diff] [blame] | 504 | |
| 505 | if (devpriv->is_m_series) { |
H Hartley Sweeten | 05dd0c9 | 2015-05-01 14:58:26 -0700 | [diff] [blame] | 506 | val = m_series_stc_read(dev, reg); |
H Hartley Sweeten | b30f0d0 | 2014-06-19 10:20:37 -0700 | [diff] [blame] | 507 | } else { |
| 508 | val = ni_stc_readw(dev, reg) << 16; |
| 509 | val |= ni_stc_readw(dev, reg + 1); |
| 510 | } |
| 511 | return val; |
H Hartley Sweeten | 00b14b1 | 2014-06-19 10:20:34 -0700 | [diff] [blame] | 512 | } |
| 513 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 514 | static inline void ni_set_bitfield(struct comedi_device *dev, int reg, |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 515 | unsigned int bit_mask, |
| 516 | unsigned int bit_values) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 517 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 518 | struct ni_private *devpriv = dev->private; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 519 | unsigned long flags; |
| 520 | |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 521 | spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 522 | switch (reg) { |
H Hartley Sweeten | 5cca26a | 2015-05-01 14:59:26 -0700 | [diff] [blame] | 523 | case NISTC_INTA_ENA_REG: |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 524 | devpriv->int_a_enable_reg &= ~bit_mask; |
| 525 | devpriv->int_a_enable_reg |= bit_values & bit_mask; |
H Hartley Sweeten | f1618db | 2015-05-01 14:59:11 -0700 | [diff] [blame] | 526 | ni_stc_writew(dev, devpriv->int_a_enable_reg, reg); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 527 | break; |
H Hartley Sweeten | 4c9c1d2 | 2015-05-01 14:59:28 -0700 | [diff] [blame] | 528 | case NISTC_INTB_ENA_REG: |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 529 | devpriv->int_b_enable_reg &= ~bit_mask; |
| 530 | devpriv->int_b_enable_reg |= bit_values & bit_mask; |
H Hartley Sweeten | f1618db | 2015-05-01 14:59:11 -0700 | [diff] [blame] | 531 | ni_stc_writew(dev, devpriv->int_b_enable_reg, reg); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 532 | break; |
H Hartley Sweeten | 5ecadf8 | 2015-05-01 14:59:12 -0700 | [diff] [blame] | 533 | case NISTC_IO_BIDIR_PIN_REG: |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 534 | devpriv->io_bidirection_pin_reg &= ~bit_mask; |
| 535 | devpriv->io_bidirection_pin_reg |= bit_values & bit_mask; |
H Hartley Sweeten | f1618db | 2015-05-01 14:59:11 -0700 | [diff] [blame] | 536 | ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, reg); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 537 | break; |
H Hartley Sweeten | a4b7ef9 | 2015-05-01 15:00:03 -0700 | [diff] [blame] | 538 | case NI_E_DMA_AI_AO_SEL_REG: |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 539 | devpriv->ai_ao_select_reg &= ~bit_mask; |
| 540 | devpriv->ai_ao_select_reg |= bit_values & bit_mask; |
H Hartley Sweeten | f1618db | 2015-05-01 14:59:11 -0700 | [diff] [blame] | 541 | ni_writeb(dev, devpriv->ai_ao_select_reg, reg); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 542 | break; |
H Hartley Sweeten | 7d6f3aa | 2015-05-01 15:00:04 -0700 | [diff] [blame] | 543 | case NI_E_DMA_G0_G1_SEL_REG: |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 544 | devpriv->g0_g1_select_reg &= ~bit_mask; |
| 545 | devpriv->g0_g1_select_reg |= bit_values & bit_mask; |
H Hartley Sweeten | f1618db | 2015-05-01 14:59:11 -0700 | [diff] [blame] | 546 | ni_writeb(dev, devpriv->g0_g1_select_reg, reg); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 547 | break; |
H Hartley Sweeten | 38b81a7 | 2016-04-14 09:57:50 -0700 | [diff] [blame] | 548 | case NI_M_CDIO_DMA_SEL_REG: |
| 549 | devpriv->cdio_dma_select_reg &= ~bit_mask; |
| 550 | devpriv->cdio_dma_select_reg |= bit_values & bit_mask; |
| 551 | ni_writeb(dev, devpriv->cdio_dma_select_reg, reg); |
| 552 | break; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 553 | default: |
Haneen Mohammed | ce82410 | 2015-03-06 22:01:38 +0300 | [diff] [blame] | 554 | dev_err(dev->class_dev, "called with invalid register %d\n", |
| 555 | reg); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 556 | break; |
| 557 | } |
| 558 | mmiowb(); |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 559 | spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 560 | } |
| 561 | |
| 562 | #ifdef PCIDMA |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 563 | |
H Hartley Sweeten | 6f7fa70 | 2016-04-14 09:58:07 -0700 | [diff] [blame] | 564 | /* selects the MITE channel to use for DMA */ |
| 565 | #define NI_STC_DMA_CHAN_SEL(x) (((x) < 4) ? BIT(x) : \ |
| 566 | ((x) == 4) ? 0x3 : \ |
| 567 | ((x) == 5) ? 0x5 : 0x0) |
| 568 | |
| 569 | /* DMA channel setup */ |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 570 | static int ni_request_ai_mite_channel(struct comedi_device *dev) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 571 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 572 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | 38b81a7 | 2016-04-14 09:57:50 -0700 | [diff] [blame] | 573 | struct mite_channel *mite_chan; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 574 | unsigned long flags; |
H Hartley Sweeten | 38b81a7 | 2016-04-14 09:57:50 -0700 | [diff] [blame] | 575 | unsigned int bits; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 576 | |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 577 | spin_lock_irqsave(&devpriv->mite_channel_lock, flags); |
H Hartley Sweeten | 38b81a7 | 2016-04-14 09:57:50 -0700 | [diff] [blame] | 578 | mite_chan = mite_request_channel(devpriv->mite, devpriv->ai_mite_ring); |
| 579 | if (!mite_chan) { |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 580 | spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); |
H Hartley Sweeten | 5ac1d82 | 2014-07-17 11:57:33 -0700 | [diff] [blame] | 581 | dev_err(dev->class_dev, |
| 582 | "failed to reserve mite dma channel for analog input\n"); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 583 | return -EBUSY; |
| 584 | } |
H Hartley Sweeten | 38b81a7 | 2016-04-14 09:57:50 -0700 | [diff] [blame] | 585 | mite_chan->dir = COMEDI_INPUT; |
| 586 | devpriv->ai_mite_chan = mite_chan; |
| 587 | |
H Hartley Sweeten | 6f7fa70 | 2016-04-14 09:58:07 -0700 | [diff] [blame] | 588 | bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel); |
H Hartley Sweeten | 38b81a7 | 2016-04-14 09:57:50 -0700 | [diff] [blame] | 589 | ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG, |
| 590 | NI_E_DMA_AI_SEL_MASK, NI_E_DMA_AI_SEL(bits)); |
| 591 | |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 592 | spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 593 | return 0; |
| 594 | } |
| 595 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 596 | static int ni_request_ao_mite_channel(struct comedi_device *dev) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 597 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 598 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | 38b81a7 | 2016-04-14 09:57:50 -0700 | [diff] [blame] | 599 | struct mite_channel *mite_chan; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 600 | unsigned long flags; |
H Hartley Sweeten | 38b81a7 | 2016-04-14 09:57:50 -0700 | [diff] [blame] | 601 | unsigned int bits; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 602 | |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 603 | spin_lock_irqsave(&devpriv->mite_channel_lock, flags); |
H Hartley Sweeten | 38b81a7 | 2016-04-14 09:57:50 -0700 | [diff] [blame] | 604 | mite_chan = mite_request_channel(devpriv->mite, devpriv->ao_mite_ring); |
| 605 | if (!mite_chan) { |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 606 | spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); |
H Hartley Sweeten | 5ac1d82 | 2014-07-17 11:57:33 -0700 | [diff] [blame] | 607 | dev_err(dev->class_dev, |
| 608 | "failed to reserve mite dma channel for analog outut\n"); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 609 | return -EBUSY; |
| 610 | } |
H Hartley Sweeten | 38b81a7 | 2016-04-14 09:57:50 -0700 | [diff] [blame] | 611 | mite_chan->dir = COMEDI_OUTPUT; |
| 612 | devpriv->ao_mite_chan = mite_chan; |
| 613 | |
H Hartley Sweeten | 6f7fa70 | 2016-04-14 09:58:07 -0700 | [diff] [blame] | 614 | bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel); |
H Hartley Sweeten | 38b81a7 | 2016-04-14 09:57:50 -0700 | [diff] [blame] | 615 | ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG, |
| 616 | NI_E_DMA_AO_SEL_MASK, NI_E_DMA_AO_SEL(bits)); |
| 617 | |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 618 | spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 619 | return 0; |
| 620 | } |
| 621 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 622 | static int ni_request_gpct_mite_channel(struct comedi_device *dev, |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 623 | unsigned int gpct_index, |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 624 | enum comedi_io_direction direction) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 625 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 626 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | 38b81a7 | 2016-04-14 09:57:50 -0700 | [diff] [blame] | 627 | struct ni_gpct *counter = &devpriv->counter_dev->counters[gpct_index]; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 628 | struct mite_channel *mite_chan; |
H Hartley Sweeten | 38b81a7 | 2016-04-14 09:57:50 -0700 | [diff] [blame] | 629 | unsigned long flags; |
| 630 | unsigned int bits; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 631 | |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 632 | spin_lock_irqsave(&devpriv->mite_channel_lock, flags); |
H Hartley Sweeten | 38b81a7 | 2016-04-14 09:57:50 -0700 | [diff] [blame] | 633 | mite_chan = mite_request_channel(devpriv->mite, |
| 634 | devpriv->gpct_mite_ring[gpct_index]); |
H Hartley Sweeten | c6be154 | 2015-03-04 12:15:40 -0700 | [diff] [blame] | 635 | if (!mite_chan) { |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 636 | spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); |
H Hartley Sweeten | 5ac1d82 | 2014-07-17 11:57:33 -0700 | [diff] [blame] | 637 | dev_err(dev->class_dev, |
| 638 | "failed to reserve mite dma channel for counter\n"); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 639 | return -EBUSY; |
| 640 | } |
| 641 | mite_chan->dir = direction; |
H Hartley Sweeten | 38b81a7 | 2016-04-14 09:57:50 -0700 | [diff] [blame] | 642 | ni_tio_set_mite_channel(counter, mite_chan); |
| 643 | |
H Hartley Sweeten | 6f7fa70 | 2016-04-14 09:58:07 -0700 | [diff] [blame] | 644 | bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel); |
H Hartley Sweeten | 38b81a7 | 2016-04-14 09:57:50 -0700 | [diff] [blame] | 645 | ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG, |
| 646 | NI_E_DMA_G0_G1_SEL_MASK(gpct_index), |
| 647 | NI_E_DMA_G0_G1_SEL(gpct_index, bits)); |
| 648 | |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 649 | spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 650 | return 0; |
| 651 | } |
| 652 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 653 | static int ni_request_cdo_mite_channel(struct comedi_device *dev) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 654 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 655 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | 38b81a7 | 2016-04-14 09:57:50 -0700 | [diff] [blame] | 656 | struct mite_channel *mite_chan; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 657 | unsigned long flags; |
H Hartley Sweeten | 38b81a7 | 2016-04-14 09:57:50 -0700 | [diff] [blame] | 658 | unsigned int bits; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 659 | |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 660 | spin_lock_irqsave(&devpriv->mite_channel_lock, flags); |
H Hartley Sweeten | 38b81a7 | 2016-04-14 09:57:50 -0700 | [diff] [blame] | 661 | mite_chan = mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring); |
| 662 | if (!mite_chan) { |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 663 | spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); |
H Hartley Sweeten | 5ac1d82 | 2014-07-17 11:57:33 -0700 | [diff] [blame] | 664 | dev_err(dev->class_dev, |
| 665 | "failed to reserve mite dma channel for correlated digital output\n"); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 666 | return -EBUSY; |
| 667 | } |
H Hartley Sweeten | 38b81a7 | 2016-04-14 09:57:50 -0700 | [diff] [blame] | 668 | mite_chan->dir = COMEDI_OUTPUT; |
| 669 | devpriv->cdo_mite_chan = mite_chan; |
| 670 | |
| 671 | /* |
H Hartley Sweeten | 6f7fa70 | 2016-04-14 09:58:07 -0700 | [diff] [blame] | 672 | * XXX just guessing NI_STC_DMA_CHAN_SEL() |
H Hartley Sweeten | 38b81a7 | 2016-04-14 09:57:50 -0700 | [diff] [blame] | 673 | * returns the right bits, under the assumption the cdio dma |
| 674 | * selection works just like ai/ao/gpct. |
| 675 | * Definitely works for dma channels 0 and 1. |
| 676 | */ |
H Hartley Sweeten | 6f7fa70 | 2016-04-14 09:58:07 -0700 | [diff] [blame] | 677 | bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel); |
H Hartley Sweeten | 38b81a7 | 2016-04-14 09:57:50 -0700 | [diff] [blame] | 678 | ni_set_bitfield(dev, NI_M_CDIO_DMA_SEL_REG, |
| 679 | NI_M_CDIO_DMA_SEL_CDO_MASK, |
| 680 | NI_M_CDIO_DMA_SEL_CDO(bits)); |
| 681 | |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 682 | spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 683 | return 0; |
| 684 | } |
H Hartley Sweeten | cf122bb | 2016-04-14 09:57:52 -0700 | [diff] [blame] | 685 | #endif /* PCIDMA */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 686 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 687 | static void ni_release_ai_mite_channel(struct comedi_device *dev) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 688 | { |
| 689 | #ifdef PCIDMA |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 690 | struct ni_private *devpriv = dev->private; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 691 | unsigned long flags; |
| 692 | |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 693 | spin_lock_irqsave(&devpriv->mite_channel_lock, flags); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 694 | if (devpriv->ai_mite_chan) { |
H Hartley Sweeten | b7cd3f6 | 2016-04-14 09:57:51 -0700 | [diff] [blame] | 695 | ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG, |
| 696 | NI_E_DMA_AI_SEL_MASK, 0); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 697 | mite_release_channel(devpriv->ai_mite_chan); |
| 698 | devpriv->ai_mite_chan = NULL; |
| 699 | } |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 700 | spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); |
Bill Pemberton | 2696fb5 | 2009-03-27 11:29:34 -0400 | [diff] [blame] | 701 | #endif /* PCIDMA */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 702 | } |
| 703 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 704 | static void ni_release_ao_mite_channel(struct comedi_device *dev) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 705 | { |
| 706 | #ifdef PCIDMA |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 707 | struct ni_private *devpriv = dev->private; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 708 | unsigned long flags; |
| 709 | |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 710 | spin_lock_irqsave(&devpriv->mite_channel_lock, flags); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 711 | if (devpriv->ao_mite_chan) { |
H Hartley Sweeten | b7cd3f6 | 2016-04-14 09:57:51 -0700 | [diff] [blame] | 712 | ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG, |
| 713 | NI_E_DMA_AO_SEL_MASK, 0); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 714 | mite_release_channel(devpriv->ao_mite_chan); |
| 715 | devpriv->ao_mite_chan = NULL; |
| 716 | } |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 717 | spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); |
Bill Pemberton | 2696fb5 | 2009-03-27 11:29:34 -0400 | [diff] [blame] | 718 | #endif /* PCIDMA */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 719 | } |
| 720 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 721 | #ifdef PCIDMA |
H Hartley Sweeten | 29aba763 | 2012-09-17 13:13:32 -0700 | [diff] [blame] | 722 | static void ni_release_gpct_mite_channel(struct comedi_device *dev, |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 723 | unsigned int gpct_index) |
H Hartley Sweeten | 29aba763 | 2012-09-17 13:13:32 -0700 | [diff] [blame] | 724 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 725 | struct ni_private *devpriv = dev->private; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 726 | unsigned long flags; |
| 727 | |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 728 | spin_lock_irqsave(&devpriv->mite_channel_lock, flags); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 729 | if (devpriv->counter_dev->counters[gpct_index].mite_chan) { |
| 730 | struct mite_channel *mite_chan = |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 731 | devpriv->counter_dev->counters[gpct_index].mite_chan; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 732 | |
H Hartley Sweeten | b7cd3f6 | 2016-04-14 09:57:51 -0700 | [diff] [blame] | 733 | ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG, |
| 734 | NI_E_DMA_G0_G1_SEL_MASK(gpct_index), 0); |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 735 | ni_tio_set_mite_channel(&devpriv-> |
| 736 | counter_dev->counters[gpct_index], |
| 737 | NULL); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 738 | mite_release_channel(mite_chan); |
| 739 | } |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 740 | spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 741 | } |
| 742 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 743 | static void ni_release_cdo_mite_channel(struct comedi_device *dev) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 744 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 745 | struct ni_private *devpriv = dev->private; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 746 | unsigned long flags; |
| 747 | |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 748 | spin_lock_irqsave(&devpriv->mite_channel_lock, flags); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 749 | if (devpriv->cdo_mite_chan) { |
H Hartley Sweeten | b7cd3f6 | 2016-04-14 09:57:51 -0700 | [diff] [blame] | 750 | ni_set_bitfield(dev, NI_M_CDIO_DMA_SEL_REG, |
| 751 | NI_M_CDIO_DMA_SEL_CDO_MASK, 0); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 752 | mite_release_channel(devpriv->cdo_mite_chan); |
| 753 | devpriv->cdo_mite_chan = NULL; |
| 754 | } |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 755 | spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 756 | } |
| 757 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 758 | static void ni_e_series_enable_second_irq(struct comedi_device *dev, |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 759 | unsigned int gpct_index, short enable) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 760 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 761 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | 546615f | 2016-04-14 09:57:54 -0700 | [diff] [blame] | 762 | unsigned int val = 0; |
H Hartley Sweeten | 5f31552 | 2014-06-19 10:20:33 -0700 | [diff] [blame] | 763 | int reg; |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 764 | |
H Hartley Sweeten | 5f31552 | 2014-06-19 10:20:33 -0700 | [diff] [blame] | 765 | if (devpriv->is_m_series || gpct_index > 1) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 766 | return; |
H Hartley Sweeten | 5f31552 | 2014-06-19 10:20:33 -0700 | [diff] [blame] | 767 | |
| 768 | /* |
| 769 | * e-series boards use the second irq signals to generate |
| 770 | * dma requests for their counters |
| 771 | */ |
| 772 | if (gpct_index == 0) { |
H Hartley Sweeten | d84e9c3 | 2015-05-01 14:59:27 -0700 | [diff] [blame] | 773 | reg = NISTC_INTA2_ENA_REG; |
H Hartley Sweeten | 5f31552 | 2014-06-19 10:20:33 -0700 | [diff] [blame] | 774 | if (enable) |
H Hartley Sweeten | d84e9c3 | 2015-05-01 14:59:27 -0700 | [diff] [blame] | 775 | val = NISTC_INTA_ENA_G0_GATE; |
H Hartley Sweeten | 5f31552 | 2014-06-19 10:20:33 -0700 | [diff] [blame] | 776 | } else { |
H Hartley Sweeten | 04b6846 | 2015-05-01 14:59:29 -0700 | [diff] [blame] | 777 | reg = NISTC_INTB2_ENA_REG; |
H Hartley Sweeten | 5f31552 | 2014-06-19 10:20:33 -0700 | [diff] [blame] | 778 | if (enable) |
H Hartley Sweeten | 04b6846 | 2015-05-01 14:59:29 -0700 | [diff] [blame] | 779 | val = NISTC_INTB_ENA_G1_GATE; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 780 | } |
H Hartley Sweeten | 00b14b1 | 2014-06-19 10:20:34 -0700 | [diff] [blame] | 781 | ni_stc_writew(dev, val, reg); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 782 | } |
Bill Pemberton | 2696fb5 | 2009-03-27 11:29:34 -0400 | [diff] [blame] | 783 | #endif /* PCIDMA */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 784 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 785 | static void ni_clear_ai_fifo(struct comedi_device *dev) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 786 | { |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 787 | struct ni_private *devpriv = dev->private; |
Chase Southwood | 60738f6 | 2014-01-16 12:27:29 -0600 | [diff] [blame] | 788 | static const int timeout = 10000; |
| 789 | int i; |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 790 | |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 791 | if (devpriv->is_6143) { |
Bill Pemberton | 2696fb5 | 2009-03-27 11:29:34 -0400 | [diff] [blame] | 792 | /* Flush the 6143 data FIFO */ |
H Hartley Sweeten | ee3e21a | 2015-05-01 15:00:08 -0700 | [diff] [blame] | 793 | ni_writel(dev, 0x10, NI6143_AI_FIFO_CTRL_REG); |
| 794 | ni_writel(dev, 0x00, NI6143_AI_FIFO_CTRL_REG); |
Chase Southwood | 60738f6 | 2014-01-16 12:27:29 -0600 | [diff] [blame] | 795 | /* Wait for complete */ |
| 796 | for (i = 0; i < timeout; i++) { |
H Hartley Sweeten | ee3e21a | 2015-05-01 15:00:08 -0700 | [diff] [blame] | 797 | if (!(ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x10)) |
Chase Southwood | 60738f6 | 2014-01-16 12:27:29 -0600 | [diff] [blame] | 798 | break; |
| 799 | udelay(1); |
| 800 | } |
H Hartley Sweeten | a626697 | 2014-07-16 11:22:56 -0700 | [diff] [blame] | 801 | if (i == timeout) |
H Hartley Sweeten | 5ac1d82 | 2014-07-17 11:57:33 -0700 | [diff] [blame] | 802 | dev_err(dev->class_dev, "FIFO flush timeout\n"); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 803 | } else { |
H Hartley Sweeten | 8102f3d | 2015-05-01 14:59:34 -0700 | [diff] [blame] | 804 | ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG); |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 805 | if (devpriv->is_625x) { |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 806 | ni_writeb(dev, 0, NI_M_STATIC_AI_CTRL_REG(0)); |
| 807 | ni_writeb(dev, 1, NI_M_STATIC_AI_CTRL_REG(0)); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 808 | #if 0 |
H Hartley Sweeten | bd474a0 | 2016-04-14 09:57:55 -0700 | [diff] [blame] | 809 | /* |
| 810 | * The NI example code does 3 convert pulses for 625x |
| 811 | * boards, But that appears to be wrong in practice. |
| 812 | */ |
H Hartley Sweeten | 4c4d715 | 2015-05-01 14:58:59 -0700 | [diff] [blame] | 813 | ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, |
| 814 | NISTC_AI_CMD1_REG); |
| 815 | ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, |
| 816 | NISTC_AI_CMD1_REG); |
| 817 | ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, |
| 818 | NISTC_AI_CMD1_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 819 | #endif |
| 820 | } |
| 821 | } |
| 822 | } |
| 823 | |
H Hartley Sweeten | 546615f | 2016-04-14 09:57:54 -0700 | [diff] [blame] | 824 | static inline void ni_ao_win_outw(struct comedi_device *dev, |
| 825 | unsigned int data, int addr) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 826 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 827 | struct ni_private *devpriv = dev->private; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 828 | unsigned long flags; |
| 829 | |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 830 | spin_lock_irqsave(&devpriv->window_lock, flags); |
H Hartley Sweeten | 0418da5 | 2015-05-01 15:00:07 -0700 | [diff] [blame] | 831 | ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG); |
| 832 | ni_writew(dev, data, NI611X_AO_WINDOW_DATA_REG); |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 833 | spin_unlock_irqrestore(&devpriv->window_lock, flags); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 834 | } |
| 835 | |
H Hartley Sweeten | 546615f | 2016-04-14 09:57:54 -0700 | [diff] [blame] | 836 | static inline void ni_ao_win_outl(struct comedi_device *dev, |
| 837 | unsigned int data, int addr) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 838 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 839 | struct ni_private *devpriv = dev->private; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 840 | unsigned long flags; |
| 841 | |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 842 | spin_lock_irqsave(&devpriv->window_lock, flags); |
H Hartley Sweeten | 0418da5 | 2015-05-01 15:00:07 -0700 | [diff] [blame] | 843 | ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG); |
| 844 | ni_writel(dev, data, NI611X_AO_WINDOW_DATA_REG); |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 845 | spin_unlock_irqrestore(&devpriv->window_lock, flags); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 846 | } |
| 847 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 848 | static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 849 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 850 | struct ni_private *devpriv = dev->private; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 851 | unsigned long flags; |
| 852 | unsigned short data; |
| 853 | |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 854 | spin_lock_irqsave(&devpriv->window_lock, flags); |
H Hartley Sweeten | 0418da5 | 2015-05-01 15:00:07 -0700 | [diff] [blame] | 855 | ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG); |
| 856 | data = ni_readw(dev, NI611X_AO_WINDOW_DATA_REG); |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 857 | spin_unlock_irqrestore(&devpriv->window_lock, flags); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 858 | return data; |
| 859 | } |
| 860 | |
H Hartley Sweeten | b6a0e5b | 2016-04-14 09:57:56 -0700 | [diff] [blame] | 861 | /* |
| 862 | * ni_set_bits( ) allows different parts of the ni_mio_common driver to |
| 863 | * share registers (such as Interrupt_A_Register) without interfering with |
| 864 | * each other. |
| 865 | * |
| 866 | * NOTE: the switch/case statements are optimized out for a constant argument |
| 867 | * so this is actually quite fast--- If you must wrap another function around |
| 868 | * this make it inline to avoid a large speed penalty. |
| 869 | * |
| 870 | * value should only be 1 or 0. |
| 871 | */ |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 872 | static inline void ni_set_bits(struct comedi_device *dev, int reg, |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 873 | unsigned int bits, unsigned int value) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 874 | { |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 875 | unsigned int bit_values; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 876 | |
| 877 | if (value) |
| 878 | bit_values = bits; |
| 879 | else |
| 880 | bit_values = 0; |
| 881 | ni_set_bitfield(dev, reg, bits, bit_values); |
| 882 | } |
| 883 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 884 | #ifdef PCIDMA |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 885 | static void ni_sync_ai_dma(struct comedi_device *dev) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 886 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 887 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | 5dce16e | 2014-05-28 16:26:50 -0700 | [diff] [blame] | 888 | struct comedi_subdevice *s = dev->read_subdev; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 889 | unsigned long flags; |
| 890 | |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 891 | spin_lock_irqsave(&devpriv->mite_channel_lock, flags); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 892 | if (devpriv->ai_mite_chan) |
H Hartley Sweeten | 51d4300 | 2016-04-20 10:36:39 -0700 | [diff] [blame] | 893 | mite_sync_dma(devpriv->ai_mite_chan, s); |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 894 | spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 895 | } |
| 896 | |
H Hartley Sweeten | 2655c8a | 2014-05-28 16:26:41 -0700 | [diff] [blame] | 897 | static int ni_ai_drain_dma(struct comedi_device *dev) |
| 898 | { |
| 899 | struct ni_private *devpriv = dev->private; |
| 900 | int i; |
| 901 | static const int timeout = 10000; |
| 902 | unsigned long flags; |
| 903 | int retval = 0; |
| 904 | |
| 905 | spin_lock_irqsave(&devpriv->mite_channel_lock, flags); |
| 906 | if (devpriv->ai_mite_chan) { |
| 907 | for (i = 0; i < timeout; i++) { |
H Hartley Sweeten | 7b14fff | 2015-05-01 14:59:37 -0700 | [diff] [blame] | 908 | if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) & |
H Hartley Sweeten | 7389498 | 2016-04-14 09:57:58 -0700 | [diff] [blame] | 909 | NISTC_AI_STATUS1_FIFO_E) && |
| 910 | mite_bytes_in_transit(devpriv->ai_mite_chan) == 0) |
H Hartley Sweeten | 2655c8a | 2014-05-28 16:26:41 -0700 | [diff] [blame] | 911 | break; |
| 912 | udelay(5); |
| 913 | } |
| 914 | if (i == timeout) { |
Haneen Mohammed | cd25503 | 2015-03-05 13:01:49 +0300 | [diff] [blame] | 915 | dev_err(dev->class_dev, "timed out\n"); |
H Hartley Sweeten | 89c4695e | 2014-07-18 13:29:52 -0700 | [diff] [blame] | 916 | dev_err(dev->class_dev, |
| 917 | "mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n", |
| 918 | mite_bytes_in_transit(devpriv->ai_mite_chan), |
H Hartley Sweeten | 7b14fff | 2015-05-01 14:59:37 -0700 | [diff] [blame] | 919 | ni_stc_readw(dev, NISTC_AI_STATUS1_REG)); |
H Hartley Sweeten | 2655c8a | 2014-05-28 16:26:41 -0700 | [diff] [blame] | 920 | retval = -1; |
| 921 | } |
| 922 | } |
| 923 | spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); |
| 924 | |
| 925 | ni_sync_ai_dma(dev); |
| 926 | |
| 927 | return retval; |
| 928 | } |
| 929 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 930 | static int ni_ao_wait_for_dma_load(struct comedi_device *dev) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 931 | { |
| 932 | static const int timeout = 10000; |
| 933 | int i; |
H Hartley Sweeten | f740197 | 2014-07-16 11:02:08 -0700 | [diff] [blame] | 934 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 935 | for (i = 0; i < timeout; i++) { |
| 936 | unsigned short b_status; |
| 937 | |
H Hartley Sweeten | d123ee3 | 2015-05-01 14:59:38 -0700 | [diff] [blame] | 938 | b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG); |
| 939 | if (b_status & NISTC_AO_STATUS1_FIFO_HF) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 940 | break; |
H Hartley Sweeten | bd474a0 | 2016-04-14 09:57:55 -0700 | [diff] [blame] | 941 | /* |
| 942 | * If we poll too often, the pci bus activity seems |
| 943 | * to slow the dma transfer down. |
| 944 | */ |
H Hartley Sweeten | 8a5b817 | 2016-04-14 09:58:03 -0700 | [diff] [blame] | 945 | usleep_range(10, 100); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 946 | } |
| 947 | if (i == timeout) { |
H Hartley Sweeten | 5ac1d82 | 2014-07-17 11:57:33 -0700 | [diff] [blame] | 948 | dev_err(dev->class_dev, "timed out waiting for dma load\n"); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 949 | return -EPIPE; |
| 950 | } |
| 951 | return 0; |
| 952 | } |
Bill Pemberton | 2696fb5 | 2009-03-27 11:29:34 -0400 | [diff] [blame] | 953 | #endif /* PCIDMA */ |
H Hartley Sweeten | f8246df | 2014-05-28 16:26:37 -0700 | [diff] [blame] | 954 | |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 955 | #ifndef PCIDMA |
| 956 | |
| 957 | static void ni_ao_fifo_load(struct comedi_device *dev, |
| 958 | struct comedi_subdevice *s, int n) |
| 959 | { |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 960 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 961 | int i; |
| 962 | unsigned short d; |
H Hartley Sweeten | 546615f | 2016-04-14 09:57:54 -0700 | [diff] [blame] | 963 | unsigned int packed_data; |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 964 | |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 965 | for (i = 0; i < n; i++) { |
H Hartley Sweeten | e14c6a6 | 2014-10-22 14:36:43 -0700 | [diff] [blame] | 966 | comedi_buf_read_samples(s, &d, 1); |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 967 | |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 968 | if (devpriv->is_6xxx) { |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 969 | packed_data = d & 0xffff; |
| 970 | /* 6711 only has 16 bit wide ao fifo */ |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 971 | if (!devpriv->is_6711) { |
H Hartley Sweeten | e14c6a6 | 2014-10-22 14:36:43 -0700 | [diff] [blame] | 972 | comedi_buf_read_samples(s, &d, 1); |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 973 | i++; |
| 974 | packed_data |= (d << 16) & 0xffff0000; |
| 975 | } |
H Hartley Sweeten | 0418da5 | 2015-05-01 15:00:07 -0700 | [diff] [blame] | 976 | ni_writel(dev, packed_data, NI611X_AO_FIFO_DATA_REG); |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 977 | } else { |
H Hartley Sweeten | 9e0ad6f | 2015-05-01 15:00:00 -0700 | [diff] [blame] | 978 | ni_writew(dev, d, NI_E_AO_FIFO_DATA_REG); |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 979 | } |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 980 | } |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 981 | } |
| 982 | |
| 983 | /* |
| 984 | * There's a small problem if the FIFO gets really low and we |
| 985 | * don't have the data to fill it. Basically, if after we fill |
| 986 | * the FIFO with all the data available, the FIFO is _still_ |
| 987 | * less than half full, we never clear the interrupt. If the |
| 988 | * IRQ is in edge mode, we never get another interrupt, because |
| 989 | * this one wasn't cleared. If in level mode, we get flooded |
| 990 | * with interrupts that we can't fulfill, because nothing ever |
| 991 | * gets put into the buffer. |
| 992 | * |
| 993 | * This kind of situation is recoverable, but it is easier to |
| 994 | * just pretend we had a FIFO underrun, since there is a good |
| 995 | * chance it will happen anyway. This is _not_ the case for |
| 996 | * RT code, as RT code might purposely be running close to the |
| 997 | * metal. Needs to be fixed eventually. |
| 998 | */ |
| 999 | static int ni_ao_fifo_half_empty(struct comedi_device *dev, |
| 1000 | struct comedi_subdevice *s) |
| 1001 | { |
Ian Abbott | 7cf94ad | 2014-09-09 11:26:44 +0100 | [diff] [blame] | 1002 | const struct ni_board_struct *board = dev->board_ptr; |
H Hartley Sweeten | 836b571 | 2014-10-31 12:04:29 -0700 | [diff] [blame] | 1003 | unsigned int nbytes; |
| 1004 | unsigned int nsamples; |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1005 | |
H Hartley Sweeten | 836b571 | 2014-10-31 12:04:29 -0700 | [diff] [blame] | 1006 | nbytes = comedi_buf_read_n_available(s); |
| 1007 | if (nbytes == 0) { |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1008 | s->async->events |= COMEDI_CB_OVERFLOW; |
| 1009 | return 0; |
| 1010 | } |
| 1011 | |
H Hartley Sweeten | 836b571 | 2014-10-31 12:04:29 -0700 | [diff] [blame] | 1012 | nsamples = comedi_bytes_to_samples(s, nbytes); |
| 1013 | if (nsamples > board->ao_fifo_depth / 2) |
| 1014 | nsamples = board->ao_fifo_depth / 2; |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1015 | |
H Hartley Sweeten | 836b571 | 2014-10-31 12:04:29 -0700 | [diff] [blame] | 1016 | ni_ao_fifo_load(dev, s, nsamples); |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1017 | |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1018 | return 1; |
| 1019 | } |
| 1020 | |
| 1021 | static int ni_ao_prep_fifo(struct comedi_device *dev, |
| 1022 | struct comedi_subdevice *s) |
| 1023 | { |
Ian Abbott | 7cf94ad | 2014-09-09 11:26:44 +0100 | [diff] [blame] | 1024 | const struct ni_board_struct *board = dev->board_ptr; |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1025 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | 836b571 | 2014-10-31 12:04:29 -0700 | [diff] [blame] | 1026 | unsigned int nbytes; |
| 1027 | unsigned int nsamples; |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1028 | |
| 1029 | /* reset fifo */ |
H Hartley Sweeten | 8102f3d | 2015-05-01 14:59:34 -0700 | [diff] [blame] | 1030 | ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG); |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1031 | if (devpriv->is_6xxx) |
H Hartley Sweeten | ef39154 | 2015-05-01 15:00:11 -0700 | [diff] [blame] | 1032 | ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG); |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1033 | |
| 1034 | /* load some data */ |
H Hartley Sweeten | 836b571 | 2014-10-31 12:04:29 -0700 | [diff] [blame] | 1035 | nbytes = comedi_buf_read_n_available(s); |
| 1036 | if (nbytes == 0) |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1037 | return 0; |
| 1038 | |
H Hartley Sweeten | 836b571 | 2014-10-31 12:04:29 -0700 | [diff] [blame] | 1039 | nsamples = comedi_bytes_to_samples(s, nbytes); |
| 1040 | if (nsamples > board->ao_fifo_depth) |
| 1041 | nsamples = board->ao_fifo_depth; |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1042 | |
H Hartley Sweeten | 836b571 | 2014-10-31 12:04:29 -0700 | [diff] [blame] | 1043 | ni_ao_fifo_load(dev, s, nsamples); |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1044 | |
H Hartley Sweeten | 836b571 | 2014-10-31 12:04:29 -0700 | [diff] [blame] | 1045 | return nsamples; |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1046 | } |
| 1047 | |
| 1048 | static void ni_ai_fifo_read(struct comedi_device *dev, |
| 1049 | struct comedi_subdevice *s, int n) |
| 1050 | { |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1051 | struct ni_private *devpriv = dev->private; |
| 1052 | struct comedi_async *async = s->async; |
H Hartley Sweeten | 546615f | 2016-04-14 09:57:54 -0700 | [diff] [blame] | 1053 | unsigned int dl; |
H Hartley Sweeten | 9caba32 | 2014-10-22 15:36:36 -0700 | [diff] [blame] | 1054 | unsigned short data; |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1055 | int i; |
| 1056 | |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1057 | if (devpriv->is_611x) { |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1058 | for (i = 0; i < n / 2; i++) { |
H Hartley Sweeten | 0418da5 | 2015-05-01 15:00:07 -0700 | [diff] [blame] | 1059 | dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG); |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1060 | /* This may get the hi/lo data in the wrong order */ |
H Hartley Sweeten | 9caba32 | 2014-10-22 15:36:36 -0700 | [diff] [blame] | 1061 | data = (dl >> 16) & 0xffff; |
| 1062 | comedi_buf_write_samples(s, &data, 1); |
| 1063 | data = dl & 0xffff; |
| 1064 | comedi_buf_write_samples(s, &data, 1); |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1065 | } |
| 1066 | /* Check if there's a single sample stuck in the FIFO */ |
| 1067 | if (n % 2) { |
H Hartley Sweeten | 0418da5 | 2015-05-01 15:00:07 -0700 | [diff] [blame] | 1068 | dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG); |
H Hartley Sweeten | 9caba32 | 2014-10-22 15:36:36 -0700 | [diff] [blame] | 1069 | data = dl & 0xffff; |
| 1070 | comedi_buf_write_samples(s, &data, 1); |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1071 | } |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1072 | } else if (devpriv->is_6143) { |
H Hartley Sweeten | b6a0e5b | 2016-04-14 09:57:56 -0700 | [diff] [blame] | 1073 | /* |
| 1074 | * This just reads the FIFO assuming the data is present, |
| 1075 | * no checks on the FIFO status are performed. |
| 1076 | */ |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1077 | for (i = 0; i < n / 2; i++) { |
H Hartley Sweeten | ee3e21a | 2015-05-01 15:00:08 -0700 | [diff] [blame] | 1078 | dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG); |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1079 | |
H Hartley Sweeten | 9caba32 | 2014-10-22 15:36:36 -0700 | [diff] [blame] | 1080 | data = (dl >> 16) & 0xffff; |
| 1081 | comedi_buf_write_samples(s, &data, 1); |
| 1082 | data = dl & 0xffff; |
| 1083 | comedi_buf_write_samples(s, &data, 1); |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1084 | } |
| 1085 | if (n % 2) { |
| 1086 | /* Assume there is a single sample stuck in the FIFO */ |
H Hartley Sweeten | 9c340ac | 2014-05-29 10:56:32 -0700 | [diff] [blame] | 1087 | /* Get stranded sample into FIFO */ |
H Hartley Sweeten | ee3e21a | 2015-05-01 15:00:08 -0700 | [diff] [blame] | 1088 | ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG); |
| 1089 | dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG); |
H Hartley Sweeten | 9caba32 | 2014-10-22 15:36:36 -0700 | [diff] [blame] | 1090 | data = (dl >> 16) & 0xffff; |
| 1091 | comedi_buf_write_samples(s, &data, 1); |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1092 | } |
| 1093 | } else { |
Janani Ravichandran | e563637 | 2016-02-11 19:07:48 -0500 | [diff] [blame] | 1094 | if (n > ARRAY_SIZE(devpriv->ai_fifo_buffer)) { |
H Hartley Sweeten | 5ac1d82 | 2014-07-17 11:57:33 -0700 | [diff] [blame] | 1095 | dev_err(dev->class_dev, |
| 1096 | "bug! ai_fifo_buffer too small\n"); |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1097 | async->events |= COMEDI_CB_ERROR; |
| 1098 | return; |
| 1099 | } |
| 1100 | for (i = 0; i < n; i++) { |
| 1101 | devpriv->ai_fifo_buffer[i] = |
H Hartley Sweeten | 363f570 | 2015-05-01 14:59:56 -0700 | [diff] [blame] | 1102 | ni_readw(dev, NI_E_AI_FIFO_DATA_REG); |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1103 | } |
H Hartley Sweeten | 9caba32 | 2014-10-22 15:36:36 -0700 | [diff] [blame] | 1104 | comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, n); |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1105 | } |
| 1106 | } |
| 1107 | |
| 1108 | static void ni_handle_fifo_half_full(struct comedi_device *dev) |
| 1109 | { |
Ian Abbott | 7cf94ad | 2014-09-09 11:26:44 +0100 | [diff] [blame] | 1110 | const struct ni_board_struct *board = dev->board_ptr; |
H Hartley Sweeten | 5dce16e | 2014-05-28 16:26:50 -0700 | [diff] [blame] | 1111 | struct comedi_subdevice *s = dev->read_subdev; |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1112 | int n; |
| 1113 | |
| 1114 | n = board->ai_fifo_depth / 2; |
| 1115 | |
| 1116 | ni_ai_fifo_read(dev, s, n); |
| 1117 | } |
| 1118 | #endif |
| 1119 | |
H Hartley Sweeten | bd474a0 | 2016-04-14 09:57:55 -0700 | [diff] [blame] | 1120 | /* Empties the AI fifo */ |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1121 | static void ni_handle_fifo_dregs(struct comedi_device *dev) |
| 1122 | { |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1123 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | 5dce16e | 2014-05-28 16:26:50 -0700 | [diff] [blame] | 1124 | struct comedi_subdevice *s = dev->read_subdev; |
H Hartley Sweeten | 546615f | 2016-04-14 09:57:54 -0700 | [diff] [blame] | 1125 | unsigned int dl; |
H Hartley Sweeten | 9caba32 | 2014-10-22 15:36:36 -0700 | [diff] [blame] | 1126 | unsigned short data; |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1127 | int i; |
| 1128 | |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1129 | if (devpriv->is_611x) { |
H Hartley Sweeten | 7b14fff | 2015-05-01 14:59:37 -0700 | [diff] [blame] | 1130 | while ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) & |
| 1131 | NISTC_AI_STATUS1_FIFO_E) == 0) { |
H Hartley Sweeten | 0418da5 | 2015-05-01 15:00:07 -0700 | [diff] [blame] | 1132 | dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG); |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1133 | |
| 1134 | /* This may get the hi/lo data in the wrong order */ |
H Hartley Sweeten | 9caba32 | 2014-10-22 15:36:36 -0700 | [diff] [blame] | 1135 | data = dl >> 16; |
| 1136 | comedi_buf_write_samples(s, &data, 1); |
| 1137 | data = dl & 0xffff; |
| 1138 | comedi_buf_write_samples(s, &data, 1); |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1139 | } |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1140 | } else if (devpriv->is_6143) { |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1141 | i = 0; |
H Hartley Sweeten | ee3e21a | 2015-05-01 15:00:08 -0700 | [diff] [blame] | 1142 | while (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x04) { |
| 1143 | dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG); |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1144 | |
| 1145 | /* This may get the hi/lo data in the wrong order */ |
H Hartley Sweeten | 9caba32 | 2014-10-22 15:36:36 -0700 | [diff] [blame] | 1146 | data = dl >> 16; |
| 1147 | comedi_buf_write_samples(s, &data, 1); |
| 1148 | data = dl & 0xffff; |
| 1149 | comedi_buf_write_samples(s, &data, 1); |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1150 | i += 2; |
| 1151 | } |
| 1152 | /* Check if stranded sample is present */ |
H Hartley Sweeten | ee3e21a | 2015-05-01 15:00:08 -0700 | [diff] [blame] | 1153 | if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) { |
H Hartley Sweeten | 9c340ac | 2014-05-29 10:56:32 -0700 | [diff] [blame] | 1154 | /* Get stranded sample into FIFO */ |
H Hartley Sweeten | ee3e21a | 2015-05-01 15:00:08 -0700 | [diff] [blame] | 1155 | ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG); |
| 1156 | dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG); |
H Hartley Sweeten | 9caba32 | 2014-10-22 15:36:36 -0700 | [diff] [blame] | 1157 | data = (dl >> 16) & 0xffff; |
| 1158 | comedi_buf_write_samples(s, &data, 1); |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1159 | } |
| 1160 | |
| 1161 | } else { |
H Hartley Sweeten | b6a0e5b | 2016-04-14 09:57:56 -0700 | [diff] [blame] | 1162 | unsigned short fe; /* fifo empty */ |
| 1163 | |
| 1164 | fe = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) & |
| 1165 | NISTC_AI_STATUS1_FIFO_E; |
| 1166 | while (fe == 0) { |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1167 | for (i = 0; |
Janani Ravichandran | e563637 | 2016-02-11 19:07:48 -0500 | [diff] [blame] | 1168 | i < ARRAY_SIZE(devpriv->ai_fifo_buffer); i++) { |
H Hartley Sweeten | b6a0e5b | 2016-04-14 09:57:56 -0700 | [diff] [blame] | 1169 | fe = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) & |
| 1170 | NISTC_AI_STATUS1_FIFO_E; |
| 1171 | if (fe) |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1172 | break; |
| 1173 | devpriv->ai_fifo_buffer[i] = |
H Hartley Sweeten | 363f570 | 2015-05-01 14:59:56 -0700 | [diff] [blame] | 1174 | ni_readw(dev, NI_E_AI_FIFO_DATA_REG); |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1175 | } |
H Hartley Sweeten | 9caba32 | 2014-10-22 15:36:36 -0700 | [diff] [blame] | 1176 | comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, i); |
H Hartley Sweeten | 2ffb247 | 2014-05-28 16:26:47 -0700 | [diff] [blame] | 1177 | } |
| 1178 | } |
| 1179 | } |
| 1180 | |
H Hartley Sweeten | f8f6d91 | 2014-05-28 16:26:40 -0700 | [diff] [blame] | 1181 | static void get_last_sample_611x(struct comedi_device *dev) |
| 1182 | { |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1183 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | 5dce16e | 2014-05-28 16:26:50 -0700 | [diff] [blame] | 1184 | struct comedi_subdevice *s = dev->read_subdev; |
H Hartley Sweeten | f8f6d91 | 2014-05-28 16:26:40 -0700 | [diff] [blame] | 1185 | unsigned short data; |
H Hartley Sweeten | 546615f | 2016-04-14 09:57:54 -0700 | [diff] [blame] | 1186 | unsigned int dl; |
H Hartley Sweeten | f8f6d91 | 2014-05-28 16:26:40 -0700 | [diff] [blame] | 1187 | |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1188 | if (!devpriv->is_611x) |
H Hartley Sweeten | f8f6d91 | 2014-05-28 16:26:40 -0700 | [diff] [blame] | 1189 | return; |
| 1190 | |
| 1191 | /* Check if there's a single sample stuck in the FIFO */ |
H Hartley Sweeten | 906170b | 2015-05-01 14:59:52 -0700 | [diff] [blame] | 1192 | if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) { |
H Hartley Sweeten | 0418da5 | 2015-05-01 15:00:07 -0700 | [diff] [blame] | 1193 | dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG); |
Haneen Mohammed | f0dff42 | 2015-03-13 14:29:30 +0300 | [diff] [blame] | 1194 | data = dl & 0xffff; |
H Hartley Sweeten | 9caba32 | 2014-10-22 15:36:36 -0700 | [diff] [blame] | 1195 | comedi_buf_write_samples(s, &data, 1); |
H Hartley Sweeten | f8f6d91 | 2014-05-28 16:26:40 -0700 | [diff] [blame] | 1196 | } |
| 1197 | } |
| 1198 | |
| 1199 | static void get_last_sample_6143(struct comedi_device *dev) |
| 1200 | { |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1201 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | 5dce16e | 2014-05-28 16:26:50 -0700 | [diff] [blame] | 1202 | struct comedi_subdevice *s = dev->read_subdev; |
H Hartley Sweeten | f8f6d91 | 2014-05-28 16:26:40 -0700 | [diff] [blame] | 1203 | unsigned short data; |
H Hartley Sweeten | 546615f | 2016-04-14 09:57:54 -0700 | [diff] [blame] | 1204 | unsigned int dl; |
H Hartley Sweeten | f8f6d91 | 2014-05-28 16:26:40 -0700 | [diff] [blame] | 1205 | |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1206 | if (!devpriv->is_6143) |
H Hartley Sweeten | f8f6d91 | 2014-05-28 16:26:40 -0700 | [diff] [blame] | 1207 | return; |
| 1208 | |
| 1209 | /* Check if there's a single sample stuck in the FIFO */ |
H Hartley Sweeten | ee3e21a | 2015-05-01 15:00:08 -0700 | [diff] [blame] | 1210 | if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) { |
H Hartley Sweeten | 9c340ac | 2014-05-29 10:56:32 -0700 | [diff] [blame] | 1211 | /* Get stranded sample into FIFO */ |
H Hartley Sweeten | ee3e21a | 2015-05-01 15:00:08 -0700 | [diff] [blame] | 1212 | ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG); |
| 1213 | dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG); |
H Hartley Sweeten | f8f6d91 | 2014-05-28 16:26:40 -0700 | [diff] [blame] | 1214 | |
| 1215 | /* This may get the hi/lo data in the wrong order */ |
| 1216 | data = (dl >> 16) & 0xffff; |
H Hartley Sweeten | 9caba32 | 2014-10-22 15:36:36 -0700 | [diff] [blame] | 1217 | comedi_buf_write_samples(s, &data, 1); |
H Hartley Sweeten | f8f6d91 | 2014-05-28 16:26:40 -0700 | [diff] [blame] | 1218 | } |
| 1219 | } |
| 1220 | |
H Hartley Sweeten | f8246df | 2014-05-28 16:26:37 -0700 | [diff] [blame] | 1221 | static void shutdown_ai_command(struct comedi_device *dev) |
| 1222 | { |
H Hartley Sweeten | 5dce16e | 2014-05-28 16:26:50 -0700 | [diff] [blame] | 1223 | struct comedi_subdevice *s = dev->read_subdev; |
H Hartley Sweeten | f8246df | 2014-05-28 16:26:37 -0700 | [diff] [blame] | 1224 | |
| 1225 | #ifdef PCIDMA |
| 1226 | ni_ai_drain_dma(dev); |
| 1227 | #endif |
| 1228 | ni_handle_fifo_dregs(dev); |
| 1229 | get_last_sample_611x(dev); |
| 1230 | get_last_sample_6143(dev); |
| 1231 | |
| 1232 | s->async->events |= COMEDI_CB_EOA; |
| 1233 | } |
| 1234 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 1235 | static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1236 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 1237 | struct ni_private *devpriv = dev->private; |
| 1238 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1239 | if (devpriv->aimode == AIMODE_SCAN) { |
| 1240 | #ifdef PCIDMA |
| 1241 | static const int timeout = 10; |
| 1242 | int i; |
| 1243 | |
| 1244 | for (i = 0; i < timeout; i++) { |
| 1245 | ni_sync_ai_dma(dev); |
| 1246 | if ((s->async->events & COMEDI_CB_EOS)) |
| 1247 | break; |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 1248 | udelay(1); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1249 | } |
| 1250 | #else |
| 1251 | ni_handle_fifo_dregs(dev); |
| 1252 | s->async->events |= COMEDI_CB_EOS; |
| 1253 | #endif |
| 1254 | } |
H Hartley Sweeten | a1da35a | 2015-05-01 14:58:56 -0700 | [diff] [blame] | 1255 | /* handle special case of single scan */ |
| 1256 | if (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1257 | shutdown_ai_command(dev); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1258 | } |
| 1259 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 1260 | static void handle_gpct_interrupt(struct comedi_device *dev, |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 1261 | unsigned short counter_index) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1262 | { |
| 1263 | #ifdef PCIDMA |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 1264 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | f9cd92e | 2012-09-05 18:50:19 -0700 | [diff] [blame] | 1265 | struct comedi_subdevice *s; |
| 1266 | |
| 1267 | s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)]; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1268 | |
| 1269 | ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index], |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 1270 | s); |
H Hartley Sweeten | b9a69a1 | 2014-09-18 11:11:30 -0700 | [diff] [blame] | 1271 | comedi_handle_events(dev, s); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1272 | #endif |
| 1273 | } |
| 1274 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 1275 | static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1276 | { |
| 1277 | unsigned short ack = 0; |
| 1278 | |
H Hartley Sweeten | 7b14fff | 2015-05-01 14:59:37 -0700 | [diff] [blame] | 1279 | if (a_status & NISTC_AI_STATUS1_SC_TC) |
H Hartley Sweeten | 480456d | 2015-05-01 14:58:54 -0700 | [diff] [blame] | 1280 | ack |= NISTC_INTA_ACK_AI_SC_TC; |
H Hartley Sweeten | 7b14fff | 2015-05-01 14:59:37 -0700 | [diff] [blame] | 1281 | if (a_status & NISTC_AI_STATUS1_START1) |
H Hartley Sweeten | 480456d | 2015-05-01 14:58:54 -0700 | [diff] [blame] | 1282 | ack |= NISTC_INTA_ACK_AI_START1; |
H Hartley Sweeten | 7b14fff | 2015-05-01 14:59:37 -0700 | [diff] [blame] | 1283 | if (a_status & NISTC_AI_STATUS1_START) |
H Hartley Sweeten | 480456d | 2015-05-01 14:58:54 -0700 | [diff] [blame] | 1284 | ack |= NISTC_INTA_ACK_AI_START; |
H Hartley Sweeten | 7b14fff | 2015-05-01 14:59:37 -0700 | [diff] [blame] | 1285 | if (a_status & NISTC_AI_STATUS1_STOP) |
H Hartley Sweeten | 480456d | 2015-05-01 14:58:54 -0700 | [diff] [blame] | 1286 | ack |= NISTC_INTA_ACK_AI_STOP; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1287 | if (ack) |
H Hartley Sweeten | 480456d | 2015-05-01 14:58:54 -0700 | [diff] [blame] | 1288 | ni_stc_writew(dev, ack, NISTC_INTA_ACK_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1289 | } |
| 1290 | |
H Hartley Sweeten | ba5c0da | 2016-04-21 12:04:41 -0700 | [diff] [blame] | 1291 | static void handle_a_interrupt(struct comedi_device *dev, |
| 1292 | struct comedi_subdevice *s, |
H Hartley Sweeten | 3da088c | 2016-04-21 12:04:43 -0700 | [diff] [blame] | 1293 | unsigned short status) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1294 | { |
H Hartley Sweeten | 93fac79 | 2014-07-14 12:23:49 -0700 | [diff] [blame] | 1295 | struct comedi_cmd *cmd = &s->async->cmd; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1296 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1297 | /* test for all uncommon interrupt events at the same time */ |
H Hartley Sweeten | 7b14fff | 2015-05-01 14:59:37 -0700 | [diff] [blame] | 1298 | if (status & (NISTC_AI_STATUS1_ERR | |
| 1299 | NISTC_AI_STATUS1_SC_TC | NISTC_AI_STATUS1_START1)) { |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1300 | if (status == 0xffff) { |
H Hartley Sweeten | 89c4695e | 2014-07-18 13:29:52 -0700 | [diff] [blame] | 1301 | dev_err(dev->class_dev, "Card removed?\n"); |
H Hartley Sweeten | bd474a0 | 2016-04-14 09:57:55 -0700 | [diff] [blame] | 1302 | /* |
| 1303 | * We probably aren't even running a command now, |
| 1304 | * so it's a good idea to be careful. |
| 1305 | */ |
H Hartley Sweeten | 3da088c | 2016-04-21 12:04:43 -0700 | [diff] [blame] | 1306 | if (comedi_is_subdevice_running(s)) |
H Hartley Sweeten | 3e6cb74 | 2015-01-20 12:06:02 -0700 | [diff] [blame] | 1307 | s->async->events |= COMEDI_CB_ERROR; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1308 | return; |
| 1309 | } |
H Hartley Sweeten | 7b14fff | 2015-05-01 14:59:37 -0700 | [diff] [blame] | 1310 | if (status & NISTC_AI_STATUS1_ERR) { |
H Hartley Sweeten | 89c4695e | 2014-07-18 13:29:52 -0700 | [diff] [blame] | 1311 | dev_err(dev->class_dev, "ai error a_status=%04x\n", |
| 1312 | status); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1313 | |
| 1314 | shutdown_ai_command(dev); |
| 1315 | |
| 1316 | s->async->events |= COMEDI_CB_ERROR; |
H Hartley Sweeten | 7b14fff | 2015-05-01 14:59:37 -0700 | [diff] [blame] | 1317 | if (status & NISTC_AI_STATUS1_OVER) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1318 | s->async->events |= COMEDI_CB_OVERFLOW; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1319 | return; |
| 1320 | } |
H Hartley Sweeten | 7b14fff | 2015-05-01 14:59:37 -0700 | [diff] [blame] | 1321 | if (status & NISTC_AI_STATUS1_SC_TC) { |
H Hartley Sweeten | 93fac79 | 2014-07-14 12:23:49 -0700 | [diff] [blame] | 1322 | if (cmd->stop_src == TRIG_COUNT) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1323 | shutdown_ai_command(dev); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1324 | } |
| 1325 | } |
| 1326 | #ifndef PCIDMA |
H Hartley Sweeten | 7b14fff | 2015-05-01 14:59:37 -0700 | [diff] [blame] | 1327 | if (status & NISTC_AI_STATUS1_FIFO_HF) { |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1328 | int i; |
| 1329 | static const int timeout = 10; |
H Hartley Sweeten | bd474a0 | 2016-04-14 09:57:55 -0700 | [diff] [blame] | 1330 | /* |
| 1331 | * PCMCIA cards (at least 6036) seem to stop producing |
| 1332 | * interrupts if we fail to get the fifo less than half |
| 1333 | * full, so loop to be sure. |
| 1334 | */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1335 | for (i = 0; i < timeout; ++i) { |
| 1336 | ni_handle_fifo_half_full(dev); |
H Hartley Sweeten | 7b14fff | 2015-05-01 14:59:37 -0700 | [diff] [blame] | 1337 | if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) & |
| 1338 | NISTC_AI_STATUS1_FIFO_HF) == 0) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1339 | break; |
| 1340 | } |
| 1341 | } |
Bill Pemberton | 2696fb5 | 2009-03-27 11:29:34 -0400 | [diff] [blame] | 1342 | #endif /* !PCIDMA */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1343 | |
H Hartley Sweeten | 7b14fff | 2015-05-01 14:59:37 -0700 | [diff] [blame] | 1344 | if (status & NISTC_AI_STATUS1_STOP) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1345 | ni_handle_eos(dev, s); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1346 | } |
| 1347 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 1348 | static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1349 | { |
| 1350 | unsigned short ack = 0; |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 1351 | |
H Hartley Sweeten | d123ee3 | 2015-05-01 14:59:38 -0700 | [diff] [blame] | 1352 | if (b_status & NISTC_AO_STATUS1_BC_TC) |
H Hartley Sweeten | 4a6de832 | 2015-05-01 14:58:55 -0700 | [diff] [blame] | 1353 | ack |= NISTC_INTB_ACK_AO_BC_TC; |
H Hartley Sweeten | d123ee3 | 2015-05-01 14:59:38 -0700 | [diff] [blame] | 1354 | if (b_status & NISTC_AO_STATUS1_OVERRUN) |
H Hartley Sweeten | 4a6de832 | 2015-05-01 14:58:55 -0700 | [diff] [blame] | 1355 | ack |= NISTC_INTB_ACK_AO_ERR; |
H Hartley Sweeten | d123ee3 | 2015-05-01 14:59:38 -0700 | [diff] [blame] | 1356 | if (b_status & NISTC_AO_STATUS1_START) |
H Hartley Sweeten | 4a6de832 | 2015-05-01 14:58:55 -0700 | [diff] [blame] | 1357 | ack |= NISTC_INTB_ACK_AO_START; |
H Hartley Sweeten | d123ee3 | 2015-05-01 14:59:38 -0700 | [diff] [blame] | 1358 | if (b_status & NISTC_AO_STATUS1_START1) |
H Hartley Sweeten | 4a6de832 | 2015-05-01 14:58:55 -0700 | [diff] [blame] | 1359 | ack |= NISTC_INTB_ACK_AO_START1; |
H Hartley Sweeten | d123ee3 | 2015-05-01 14:59:38 -0700 | [diff] [blame] | 1360 | if (b_status & NISTC_AO_STATUS1_UC_TC) |
H Hartley Sweeten | 4a6de832 | 2015-05-01 14:58:55 -0700 | [diff] [blame] | 1361 | ack |= NISTC_INTB_ACK_AO_UC_TC; |
H Hartley Sweeten | d123ee3 | 2015-05-01 14:59:38 -0700 | [diff] [blame] | 1362 | if (b_status & NISTC_AO_STATUS1_UI2_TC) |
H Hartley Sweeten | 4a6de832 | 2015-05-01 14:58:55 -0700 | [diff] [blame] | 1363 | ack |= NISTC_INTB_ACK_AO_UI2_TC; |
H Hartley Sweeten | d123ee3 | 2015-05-01 14:59:38 -0700 | [diff] [blame] | 1364 | if (b_status & NISTC_AO_STATUS1_UPDATE) |
H Hartley Sweeten | 4a6de832 | 2015-05-01 14:58:55 -0700 | [diff] [blame] | 1365 | ack |= NISTC_INTB_ACK_AO_UPDATE; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1366 | if (ack) |
H Hartley Sweeten | 4a6de832 | 2015-05-01 14:58:55 -0700 | [diff] [blame] | 1367 | ni_stc_writew(dev, ack, NISTC_INTB_ACK_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1368 | } |
| 1369 | |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 1370 | static void handle_b_interrupt(struct comedi_device *dev, |
H Hartley Sweeten | 7ef1745 | 2016-04-21 12:04:39 -0700 | [diff] [blame] | 1371 | struct comedi_subdevice *s, |
H Hartley Sweeten | 4b2d738 | 2016-04-21 12:04:40 -0700 | [diff] [blame] | 1372 | unsigned short b_status) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1373 | { |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1374 | if (b_status == 0xffff) |
| 1375 | return; |
H Hartley Sweeten | d123ee3 | 2015-05-01 14:59:38 -0700 | [diff] [blame] | 1376 | if (b_status & NISTC_AO_STATUS1_OVERRUN) { |
H Hartley Sweeten | 89c4695e | 2014-07-18 13:29:52 -0700 | [diff] [blame] | 1377 | dev_err(dev->class_dev, |
| 1378 | "AO FIFO underrun status=0x%04x status2=0x%04x\n", |
H Hartley Sweeten | 63b2bb0 | 2015-05-01 14:59:41 -0700 | [diff] [blame] | 1379 | b_status, ni_stc_readw(dev, NISTC_AO_STATUS2_REG)); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1380 | s->async->events |= COMEDI_CB_OVERFLOW; |
| 1381 | } |
| 1382 | |
Spencer E. Olson | 6aab7fe | 2016-01-27 14:28:28 -0700 | [diff] [blame] | 1383 | if (s->async->cmd.stop_src != TRIG_NONE && |
| 1384 | b_status & NISTC_AO_STATUS1_BC_TC) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1385 | s->async->events |= COMEDI_CB_EOA; |
H Hartley Sweeten | a7866a6 | 2013-11-26 10:21:16 -0700 | [diff] [blame] | 1386 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1387 | #ifndef PCIDMA |
H Hartley Sweeten | d123ee3 | 2015-05-01 14:59:38 -0700 | [diff] [blame] | 1388 | if (b_status & NISTC_AO_STATUS1_FIFO_REQ) { |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1389 | int ret; |
| 1390 | |
| 1391 | ret = ni_ao_fifo_half_empty(dev, s); |
| 1392 | if (!ret) { |
H Hartley Sweeten | 89c4695e | 2014-07-18 13:29:52 -0700 | [diff] [blame] | 1393 | dev_err(dev->class_dev, "AO buffer underrun\n"); |
H Hartley Sweeten | 4c9c1d2 | 2015-05-01 14:59:28 -0700 | [diff] [blame] | 1394 | ni_set_bits(dev, NISTC_INTB_ENA_REG, |
| 1395 | NISTC_INTB_ENA_AO_FIFO | |
| 1396 | NISTC_INTB_ENA_AO_ERR, 0); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1397 | s->async->events |= COMEDI_CB_OVERFLOW; |
| 1398 | } |
| 1399 | } |
| 1400 | #endif |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1401 | } |
| 1402 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 1403 | static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s, |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 1404 | void *data, unsigned int num_bytes, |
| 1405 | unsigned int chan_index) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1406 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 1407 | struct ni_private *devpriv = dev->private; |
Bill Pemberton | d163679 | 2009-03-16 22:05:20 -0400 | [diff] [blame] | 1408 | struct comedi_async *async = s->async; |
H Hartley Sweeten | 9663ab1 | 2014-05-27 10:31:00 -0700 | [diff] [blame] | 1409 | struct comedi_cmd *cmd = &async->cmd; |
H Hartley Sweeten | c39e050 | 2014-10-31 12:04:28 -0700 | [diff] [blame] | 1410 | unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes); |
Ian Abbott | 3a2b101 | 2013-10-16 14:40:26 +0100 | [diff] [blame] | 1411 | unsigned short *array = data; |
Bill Pemberton | 790c554 | 2009-03-16 22:05:02 -0400 | [diff] [blame] | 1412 | unsigned int *larray = data; |
H Hartley Sweeten | 9663ab1 | 2014-05-27 10:31:00 -0700 | [diff] [blame] | 1413 | unsigned int i; |
Ksenija Stanojevic | 212efdb | 2015-10-31 06:34:29 -0700 | [diff] [blame] | 1414 | #ifdef PCIDMA |
| 1415 | __le16 *barray = data; |
| 1416 | __le32 *blarray = data; |
| 1417 | #endif |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 1418 | |
H Hartley Sweeten | c39e050 | 2014-10-31 12:04:28 -0700 | [diff] [blame] | 1419 | for (i = 0; i < nsamples; i++) { |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1420 | #ifdef PCIDMA |
| 1421 | if (s->subdev_flags & SDF_LSAMPL) |
Ksenija Stanojevic | 212efdb | 2015-10-31 06:34:29 -0700 | [diff] [blame] | 1422 | larray[i] = le32_to_cpu(blarray[i]); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1423 | else |
Ksenija Stanojevic | 212efdb | 2015-10-31 06:34:29 -0700 | [diff] [blame] | 1424 | array[i] = le16_to_cpu(barray[i]); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1425 | #endif |
| 1426 | if (s->subdev_flags & SDF_LSAMPL) |
| 1427 | larray[i] += devpriv->ai_offset[chan_index]; |
| 1428 | else |
| 1429 | array[i] += devpriv->ai_offset[chan_index]; |
| 1430 | chan_index++; |
H Hartley Sweeten | 9663ab1 | 2014-05-27 10:31:00 -0700 | [diff] [blame] | 1431 | chan_index %= cmd->chanlist_len; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1432 | } |
| 1433 | } |
| 1434 | |
| 1435 | #ifdef PCIDMA |
| 1436 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 1437 | static int ni_ai_setup_MITE_dma(struct comedi_device *dev) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1438 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 1439 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | 5dce16e | 2014-05-28 16:26:50 -0700 | [diff] [blame] | 1440 | struct comedi_subdevice *s = dev->read_subdev; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1441 | int retval; |
| 1442 | unsigned long flags; |
| 1443 | |
| 1444 | retval = ni_request_ai_mite_channel(dev); |
| 1445 | if (retval) |
| 1446 | return retval; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1447 | |
| 1448 | /* write alloc the entire buffer */ |
Ian Abbott | 24e894b | 2014-05-06 13:12:04 +0100 | [diff] [blame] | 1449 | comedi_buf_write_alloc(s, s->async->prealloc_bufsz); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1450 | |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 1451 | spin_lock_irqsave(&devpriv->mite_channel_lock, flags); |
H Hartley Sweeten | c6be154 | 2015-03-04 12:15:40 -0700 | [diff] [blame] | 1452 | if (!devpriv->ai_mite_chan) { |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 1453 | spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1454 | return -EIO; |
| 1455 | } |
| 1456 | |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1457 | if (devpriv->is_611x || devpriv->is_6143) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1458 | mite_prep_dma(devpriv->ai_mite_chan, 32, 16); |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1459 | else if (devpriv->is_628x) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1460 | mite_prep_dma(devpriv->ai_mite_chan, 32, 32); |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1461 | else |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1462 | mite_prep_dma(devpriv->ai_mite_chan, 16, 16); |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1463 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1464 | /*start the MITE */ |
| 1465 | mite_dma_arm(devpriv->ai_mite_chan); |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 1466 | spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1467 | |
| 1468 | return 0; |
| 1469 | } |
| 1470 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 1471 | static int ni_ao_setup_MITE_dma(struct comedi_device *dev) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1472 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 1473 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | e879c31 | 2014-05-28 16:26:51 -0700 | [diff] [blame] | 1474 | struct comedi_subdevice *s = dev->write_subdev; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1475 | int retval; |
| 1476 | unsigned long flags; |
| 1477 | |
| 1478 | retval = ni_request_ao_mite_channel(dev); |
| 1479 | if (retval) |
| 1480 | return retval; |
| 1481 | |
| 1482 | /* read alloc the entire buffer */ |
Ian Abbott | d13be55 | 2014-05-06 13:12:07 +0100 | [diff] [blame] | 1483 | comedi_buf_read_alloc(s, s->async->prealloc_bufsz); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1484 | |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 1485 | spin_lock_irqsave(&devpriv->mite_channel_lock, flags); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1486 | if (devpriv->ao_mite_chan) { |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1487 | if (devpriv->is_611x || devpriv->is_6713) { |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1488 | mite_prep_dma(devpriv->ao_mite_chan, 32, 32); |
| 1489 | } else { |
H Hartley Sweeten | bd474a0 | 2016-04-14 09:57:55 -0700 | [diff] [blame] | 1490 | /* |
| 1491 | * Doing 32 instead of 16 bit wide transfers from |
| 1492 | * memory makes the mite do 32 bit pci transfers, |
| 1493 | * doubling pci bandwidth. |
| 1494 | */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1495 | mite_prep_dma(devpriv->ao_mite_chan, 16, 32); |
| 1496 | } |
| 1497 | mite_dma_arm(devpriv->ao_mite_chan); |
H Hartley Sweeten | 6ac986d0 | 2015-03-05 13:21:18 -0700 | [diff] [blame] | 1498 | } else { |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1499 | retval = -EIO; |
H Hartley Sweeten | 6ac986d0 | 2015-03-05 13:21:18 -0700 | [diff] [blame] | 1500 | } |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 1501 | spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1502 | |
| 1503 | return retval; |
| 1504 | } |
| 1505 | |
Bill Pemberton | 2696fb5 | 2009-03-27 11:29:34 -0400 | [diff] [blame] | 1506 | #endif /* PCIDMA */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1507 | |
| 1508 | /* |
H Hartley Sweeten | bd474a0 | 2016-04-14 09:57:55 -0700 | [diff] [blame] | 1509 | * used for both cancel ioctl and board initialization |
| 1510 | * |
| 1511 | * this is pretty harsh for a cancel, but it works... |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1512 | */ |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 1513 | static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1514 | { |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1515 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 1516 | unsigned int ai_personal; |
| 1517 | unsigned int ai_out_ctrl; |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 1518 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1519 | ni_release_ai_mite_channel(dev); |
| 1520 | /* ai configuration */ |
H Hartley Sweeten | 707502f | 2015-05-01 14:59:25 -0700 | [diff] [blame] | 1521 | ni_stc_writew(dev, NISTC_RESET_AI_CFG_START | NISTC_RESET_AI, |
| 1522 | NISTC_RESET_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1523 | |
H Hartley Sweeten | 5cca26a | 2015-05-01 14:59:26 -0700 | [diff] [blame] | 1524 | ni_set_bits(dev, NISTC_INTA_ENA_REG, NISTC_INTA_ENA_AI_MASK, 0); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1525 | |
| 1526 | ni_clear_ai_fifo(dev); |
| 1527 | |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1528 | if (!devpriv->is_6143) |
H Hartley Sweeten | 68885d9 | 2015-05-01 14:59:54 -0700 | [diff] [blame] | 1529 | ni_writeb(dev, NI_E_MISC_CMD_EXT_ATRIG, NI_E_MISC_CMD_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1530 | |
H Hartley Sweeten | 4c4d715 | 2015-05-01 14:58:59 -0700 | [diff] [blame] | 1531 | ni_stc_writew(dev, NISTC_AI_CMD1_DISARM, NISTC_AI_CMD1_REG); |
H Hartley Sweeten | bd358f5 | 2015-05-01 14:59:03 -0700 | [diff] [blame] | 1532 | ni_stc_writew(dev, NISTC_AI_MODE1_START_STOP | |
| 1533 | NISTC_AI_MODE1_RSVD |
| 1534 | /*| NISTC_AI_MODE1_TRIGGER_ONCE */, |
| 1535 | NISTC_AI_MODE1_REG); |
H Hartley Sweeten | b134cc5 | 2015-05-01 14:59:04 -0700 | [diff] [blame] | 1536 | ni_stc_writew(dev, 0, NISTC_AI_MODE2_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1537 | /* generate FIFO interrupts on non-empty */ |
H Hartley Sweeten | c7edadc | 2015-05-01 14:59:36 -0700 | [diff] [blame] | 1538 | ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE, |
| 1539 | NISTC_AI_MODE3_REG); |
H Hartley Sweeten | aa9d73b | 2015-05-01 14:59:16 -0700 | [diff] [blame] | 1540 | |
H Hartley Sweeten | c1b7403 | 2015-05-01 14:59:30 -0700 | [diff] [blame] | 1541 | ai_personal = NISTC_AI_PERSONAL_SHIFTIN_PW | |
| 1542 | NISTC_AI_PERSONAL_SOC_POLARITY | |
| 1543 | NISTC_AI_PERSONAL_LOCALMUX_CLK_PW; |
H Hartley Sweeten | aa9d73b | 2015-05-01 14:59:16 -0700 | [diff] [blame] | 1544 | ai_out_ctrl = NISTC_AI_OUT_CTRL_SCAN_IN_PROG_SEL(3) | |
| 1545 | NISTC_AI_OUT_CTRL_EXTMUX_CLK_SEL(0) | |
| 1546 | NISTC_AI_OUT_CTRL_LOCALMUX_CLK_SEL(2) | |
| 1547 | NISTC_AI_OUT_CTRL_SC_TC_SEL(3); |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1548 | if (devpriv->is_611x) { |
H Hartley Sweeten | aa9d73b | 2015-05-01 14:59:16 -0700 | [diff] [blame] | 1549 | ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH; |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1550 | } else if (devpriv->is_6143) { |
H Hartley Sweeten | aa9d73b | 2015-05-01 14:59:16 -0700 | [diff] [blame] | 1551 | ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1552 | } else { |
H Hartley Sweeten | c1b7403 | 2015-05-01 14:59:30 -0700 | [diff] [blame] | 1553 | ai_personal |= NISTC_AI_PERSONAL_CONVERT_PW; |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1554 | if (devpriv->is_622x) |
H Hartley Sweeten | aa9d73b | 2015-05-01 14:59:16 -0700 | [diff] [blame] | 1555 | ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1556 | else |
H Hartley Sweeten | aa9d73b | 2015-05-01 14:59:16 -0700 | [diff] [blame] | 1557 | ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1558 | } |
H Hartley Sweeten | c1b7403 | 2015-05-01 14:59:30 -0700 | [diff] [blame] | 1559 | ni_stc_writew(dev, ai_personal, NISTC_AI_PERSONAL_REG); |
H Hartley Sweeten | aa9d73b | 2015-05-01 14:59:16 -0700 | [diff] [blame] | 1560 | ni_stc_writew(dev, ai_out_ctrl, NISTC_AI_OUT_CTRL_REG); |
| 1561 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1562 | /* the following registers should not be changed, because there |
| 1563 | * are no backup registers in devpriv. If you want to change |
| 1564 | * any of these, add a backup register and other appropriate code: |
H Hartley Sweeten | bd358f5 | 2015-05-01 14:59:03 -0700 | [diff] [blame] | 1565 | * NISTC_AI_MODE1_REG |
H Hartley Sweeten | c7edadc | 2015-05-01 14:59:36 -0700 | [diff] [blame] | 1566 | * NISTC_AI_MODE3_REG |
H Hartley Sweeten | c1b7403 | 2015-05-01 14:59:30 -0700 | [diff] [blame] | 1567 | * NISTC_AI_PERSONAL_REG |
H Hartley Sweeten | aa9d73b | 2015-05-01 14:59:16 -0700 | [diff] [blame] | 1568 | * NISTC_AI_OUT_CTRL_REG |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1569 | */ |
H Hartley Sweeten | 480456d | 2015-05-01 14:58:54 -0700 | [diff] [blame] | 1570 | |
| 1571 | /* clear interrupts */ |
| 1572 | ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1573 | |
H Hartley Sweeten | 707502f | 2015-05-01 14:59:25 -0700 | [diff] [blame] | 1574 | ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1575 | |
| 1576 | return 0; |
| 1577 | } |
| 1578 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 1579 | static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1580 | { |
Ian Abbott | 3cd73bc | 2012-09-24 16:27:59 +0100 | [diff] [blame] | 1581 | unsigned long flags; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1582 | int count; |
| 1583 | |
Bill Pemberton | 2696fb5 | 2009-03-27 11:29:34 -0400 | [diff] [blame] | 1584 | /* lock to avoid race with interrupt handler */ |
Ian Abbott | 3cd73bc | 2012-09-24 16:27:59 +0100 | [diff] [blame] | 1585 | spin_lock_irqsave(&dev->spinlock, flags); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1586 | #ifndef PCIDMA |
| 1587 | ni_handle_fifo_dregs(dev); |
| 1588 | #else |
| 1589 | ni_sync_ai_dma(dev); |
| 1590 | #endif |
H Hartley Sweeten | f4f3f7c | 2014-06-20 10:58:28 -0700 | [diff] [blame] | 1591 | count = comedi_buf_n_bytes_ready(s); |
Ian Abbott | 3cd73bc | 2012-09-24 16:27:59 +0100 | [diff] [blame] | 1592 | spin_unlock_irqrestore(&dev->spinlock, flags); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1593 | |
| 1594 | return count; |
| 1595 | } |
| 1596 | |
H Hartley Sweeten | 29aba763 | 2012-09-17 13:13:32 -0700 | [diff] [blame] | 1597 | static void ni_prime_channelgain_list(struct comedi_device *dev) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1598 | { |
| 1599 | int i; |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 1600 | |
H Hartley Sweeten | 4c4d715 | 2015-05-01 14:58:59 -0700 | [diff] [blame] | 1601 | ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, NISTC_AI_CMD1_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1602 | for (i = 0; i < NI_TIMEOUT; ++i) { |
H Hartley Sweeten | 7b14fff | 2015-05-01 14:59:37 -0700 | [diff] [blame] | 1603 | if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) & |
| 1604 | NISTC_AI_STATUS1_FIFO_E)) { |
H Hartley Sweeten | 8102f3d | 2015-05-01 14:59:34 -0700 | [diff] [blame] | 1605 | ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1606 | return; |
| 1607 | } |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 1608 | udelay(1); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1609 | } |
H Hartley Sweeten | 89c4695e | 2014-07-18 13:29:52 -0700 | [diff] [blame] | 1610 | dev_err(dev->class_dev, "timeout loading channel/gain list\n"); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1611 | } |
| 1612 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 1613 | static void ni_m_series_load_channelgain_list(struct comedi_device *dev, |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 1614 | unsigned int n_chan, |
| 1615 | unsigned int *list) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1616 | { |
Ian Abbott | 7cf94ad | 2014-09-09 11:26:44 +0100 | [diff] [blame] | 1617 | const struct ni_board_struct *board = dev->board_ptr; |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 1618 | struct ni_private *devpriv = dev->private; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1619 | unsigned int chan, range, aref; |
| 1620 | unsigned int i; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1621 | unsigned int dither; |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 1622 | unsigned int range_code; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1623 | |
H Hartley Sweeten | 8102f3d | 2015-05-01 14:59:34 -0700 | [diff] [blame] | 1624 | ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1625 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1626 | if ((list[0] & CR_ALT_SOURCE)) { |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 1627 | unsigned int bypass_bits; |
H Hartley Sweeten | f740197 | 2014-07-16 11:02:08 -0700 | [diff] [blame] | 1628 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1629 | chan = CR_CHAN(list[0]); |
| 1630 | range = CR_RANGE(list[0]); |
H Hartley Sweeten | 6293e35 | 2013-03-05 10:20:41 -0700 | [diff] [blame] | 1631 | range_code = ni_gainlkup[board->gainlkup][range]; |
Haneen Mohammed | f0dff42 | 2015-03-13 14:29:30 +0300 | [diff] [blame] | 1632 | dither = (list[0] & CR_ALT_FILTER) != 0; |
H Hartley Sweeten | 41f9f0b | 2015-05-01 14:58:39 -0700 | [diff] [blame] | 1633 | bypass_bits = NI_M_CFG_BYPASS_FIFO | |
| 1634 | NI_M_CFG_BYPASS_AI_CHAN(chan) | |
| 1635 | NI_M_CFG_BYPASS_AI_GAIN(range_code) | |
| 1636 | devpriv->ai_calib_source; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1637 | if (dither) |
H Hartley Sweeten | 41f9f0b | 2015-05-01 14:58:39 -0700 | [diff] [blame] | 1638 | bypass_bits |= NI_M_CFG_BYPASS_AI_DITHER; |
Bill Pemberton | 2696fb5 | 2009-03-27 11:29:34 -0400 | [diff] [blame] | 1639 | /* don't use 2's complement encoding */ |
H Hartley Sweeten | 41f9f0b | 2015-05-01 14:58:39 -0700 | [diff] [blame] | 1640 | bypass_bits |= NI_M_CFG_BYPASS_AI_POLARITY; |
| 1641 | ni_writel(dev, bypass_bits, NI_M_CFG_BYPASS_FIFO_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1642 | } else { |
H Hartley Sweeten | 41f9f0b | 2015-05-01 14:58:39 -0700 | [diff] [blame] | 1643 | ni_writel(dev, 0, NI_M_CFG_BYPASS_FIFO_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1644 | } |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1645 | for (i = 0; i < n_chan; i++) { |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 1646 | unsigned int config_bits = 0; |
H Hartley Sweeten | f740197 | 2014-07-16 11:02:08 -0700 | [diff] [blame] | 1647 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1648 | chan = CR_CHAN(list[i]); |
| 1649 | aref = CR_AREF(list[i]); |
| 1650 | range = CR_RANGE(list[i]); |
Haneen Mohammed | f0dff42 | 2015-03-13 14:29:30 +0300 | [diff] [blame] | 1651 | dither = (list[i] & CR_ALT_FILTER) != 0; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1652 | |
H Hartley Sweeten | 6293e35 | 2013-03-05 10:20:41 -0700 | [diff] [blame] | 1653 | range_code = ni_gainlkup[board->gainlkup][range]; |
H Hartley Sweeten | 817144a | 2014-07-14 12:23:51 -0700 | [diff] [blame] | 1654 | devpriv->ai_offset[i] = 0; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1655 | switch (aref) { |
| 1656 | case AREF_DIFF: |
H Hartley Sweeten | 67d2d05 | 2015-05-01 14:58:35 -0700 | [diff] [blame] | 1657 | config_bits |= NI_M_AI_CFG_CHAN_TYPE_DIFF; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1658 | break; |
| 1659 | case AREF_COMMON: |
H Hartley Sweeten | 67d2d05 | 2015-05-01 14:58:35 -0700 | [diff] [blame] | 1660 | config_bits |= NI_M_AI_CFG_CHAN_TYPE_COMMON; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1661 | break; |
| 1662 | case AREF_GROUND: |
H Hartley Sweeten | 67d2d05 | 2015-05-01 14:58:35 -0700 | [diff] [blame] | 1663 | config_bits |= NI_M_AI_CFG_CHAN_TYPE_GROUND; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1664 | break; |
| 1665 | case AREF_OTHER: |
| 1666 | break; |
| 1667 | } |
H Hartley Sweeten | 67d2d05 | 2015-05-01 14:58:35 -0700 | [diff] [blame] | 1668 | config_bits |= NI_M_AI_CFG_CHAN_SEL(chan); |
| 1669 | config_bits |= NI_M_AI_CFG_BANK_SEL(chan); |
| 1670 | config_bits |= NI_M_AI_CFG_GAIN(range_code); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1671 | if (i == n_chan - 1) |
H Hartley Sweeten | 67d2d05 | 2015-05-01 14:58:35 -0700 | [diff] [blame] | 1672 | config_bits |= NI_M_AI_CFG_LAST_CHAN; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1673 | if (dither) |
H Hartley Sweeten | 67d2d05 | 2015-05-01 14:58:35 -0700 | [diff] [blame] | 1674 | config_bits |= NI_M_AI_CFG_DITHER; |
Bill Pemberton | 2696fb5 | 2009-03-27 11:29:34 -0400 | [diff] [blame] | 1675 | /* don't use 2's complement encoding */ |
H Hartley Sweeten | 67d2d05 | 2015-05-01 14:58:35 -0700 | [diff] [blame] | 1676 | config_bits |= NI_M_AI_CFG_POLARITY; |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 1677 | ni_writew(dev, config_bits, NI_M_AI_CFG_FIFO_DATA_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1678 | } |
| 1679 | ni_prime_channelgain_list(dev); |
| 1680 | } |
| 1681 | |
| 1682 | /* |
| 1683 | * Notes on the 6110 and 6111: |
| 1684 | * These boards a slightly different than the rest of the series, since |
| 1685 | * they have multiple A/D converters. |
| 1686 | * From the driver side, the configuration memory is a |
| 1687 | * little different. |
| 1688 | * Configuration Memory Low: |
| 1689 | * bits 15-9: same |
| 1690 | * bit 8: unipolar/bipolar (should be 0 for bipolar) |
| 1691 | * bits 0-3: gain. This is 4 bits instead of 3 for the other boards |
| 1692 | * 1001 gain=0.1 (+/- 50) |
| 1693 | * 1010 0.2 |
| 1694 | * 1011 0.1 |
| 1695 | * 0001 1 |
| 1696 | * 0010 2 |
| 1697 | * 0011 5 |
| 1698 | * 0100 10 |
| 1699 | * 0101 20 |
| 1700 | * 0110 50 |
| 1701 | * Configuration Memory High: |
| 1702 | * bits 12-14: Channel Type |
| 1703 | * 001 for differential |
| 1704 | * 000 for calibration |
| 1705 | * bit 11: coupling (this is not currently handled) |
| 1706 | * 1 AC coupling |
| 1707 | * 0 DC coupling |
| 1708 | * bits 0-2: channel |
| 1709 | * valid channels are 0-3 |
| 1710 | */ |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 1711 | static void ni_load_channelgain_list(struct comedi_device *dev, |
H Hartley Sweeten | 817144a | 2014-07-14 12:23:51 -0700 | [diff] [blame] | 1712 | struct comedi_subdevice *s, |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 1713 | unsigned int n_chan, unsigned int *list) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1714 | { |
Ian Abbott | 7cf94ad | 2014-09-09 11:26:44 +0100 | [diff] [blame] | 1715 | const struct ni_board_struct *board = dev->board_ptr; |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 1716 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | 817144a | 2014-07-14 12:23:51 -0700 | [diff] [blame] | 1717 | unsigned int offset = (s->maxdata + 1) >> 1; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1718 | unsigned int chan, range, aref; |
| 1719 | unsigned int i; |
| 1720 | unsigned int hi, lo; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1721 | unsigned int dither; |
| 1722 | |
H Hartley Sweeten | 1773321 | 2014-06-19 10:20:32 -0700 | [diff] [blame] | 1723 | if (devpriv->is_m_series) { |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1724 | ni_m_series_load_channelgain_list(dev, n_chan, list); |
| 1725 | return; |
| 1726 | } |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1727 | if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) { |
H Hartley Sweeten | 7389498 | 2016-04-14 09:57:58 -0700 | [diff] [blame] | 1728 | if (devpriv->changain_state && |
| 1729 | devpriv->changain_spec == list[0]) { |
Bill Pemberton | 2696fb5 | 2009-03-27 11:29:34 -0400 | [diff] [blame] | 1730 | /* ready to go. */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1731 | return; |
| 1732 | } |
| 1733 | devpriv->changain_state = 1; |
| 1734 | devpriv->changain_spec = list[0]; |
| 1735 | } else { |
| 1736 | devpriv->changain_state = 0; |
| 1737 | } |
| 1738 | |
H Hartley Sweeten | 8102f3d | 2015-05-01 14:59:34 -0700 | [diff] [blame] | 1739 | ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1740 | |
Bill Pemberton | 2696fb5 | 2009-03-27 11:29:34 -0400 | [diff] [blame] | 1741 | /* Set up Calibration mode if required */ |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1742 | if (devpriv->is_6143) { |
H Hartley Sweeten | 7389498 | 2016-04-14 09:57:58 -0700 | [diff] [blame] | 1743 | if ((list[0] & CR_ALT_SOURCE) && |
| 1744 | !devpriv->ai_calib_source_enabled) { |
Bill Pemberton | 2696fb5 | 2009-03-27 11:29:34 -0400 | [diff] [blame] | 1745 | /* Strobe Relay enable bit */ |
H Hartley Sweeten | 5a92cac | 2014-06-19 10:20:35 -0700 | [diff] [blame] | 1746 | ni_writew(dev, devpriv->ai_calib_source | |
H Hartley Sweeten | ee3e21a | 2015-05-01 15:00:08 -0700 | [diff] [blame] | 1747 | NI6143_CALIB_CHAN_RELAY_ON, |
| 1748 | NI6143_CALIB_CHAN_REG); |
H Hartley Sweeten | 5a92cac | 2014-06-19 10:20:35 -0700 | [diff] [blame] | 1749 | ni_writew(dev, devpriv->ai_calib_source, |
H Hartley Sweeten | ee3e21a | 2015-05-01 15:00:08 -0700 | [diff] [blame] | 1750 | NI6143_CALIB_CHAN_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1751 | devpriv->ai_calib_source_enabled = 1; |
H Hartley Sweeten | b6a0e5b | 2016-04-14 09:57:56 -0700 | [diff] [blame] | 1752 | /* Allow relays to change */ |
| 1753 | msleep_interruptible(100); |
H Hartley Sweeten | 7389498 | 2016-04-14 09:57:58 -0700 | [diff] [blame] | 1754 | } else if (!(list[0] & CR_ALT_SOURCE) && |
| 1755 | devpriv->ai_calib_source_enabled) { |
Bill Pemberton | 2696fb5 | 2009-03-27 11:29:34 -0400 | [diff] [blame] | 1756 | /* Strobe Relay disable bit */ |
H Hartley Sweeten | 5a92cac | 2014-06-19 10:20:35 -0700 | [diff] [blame] | 1757 | ni_writew(dev, devpriv->ai_calib_source | |
H Hartley Sweeten | ee3e21a | 2015-05-01 15:00:08 -0700 | [diff] [blame] | 1758 | NI6143_CALIB_CHAN_RELAY_OFF, |
| 1759 | NI6143_CALIB_CHAN_REG); |
H Hartley Sweeten | 5a92cac | 2014-06-19 10:20:35 -0700 | [diff] [blame] | 1760 | ni_writew(dev, devpriv->ai_calib_source, |
H Hartley Sweeten | ee3e21a | 2015-05-01 15:00:08 -0700 | [diff] [blame] | 1761 | NI6143_CALIB_CHAN_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1762 | devpriv->ai_calib_source_enabled = 0; |
H Hartley Sweeten | b6a0e5b | 2016-04-14 09:57:56 -0700 | [diff] [blame] | 1763 | /* Allow relays to change */ |
| 1764 | msleep_interruptible(100); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1765 | } |
| 1766 | } |
| 1767 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1768 | for (i = 0; i < n_chan; i++) { |
H Hartley Sweeten | a626697 | 2014-07-16 11:22:56 -0700 | [diff] [blame] | 1769 | if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE)) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1770 | chan = devpriv->ai_calib_source; |
H Hartley Sweeten | a626697 | 2014-07-16 11:22:56 -0700 | [diff] [blame] | 1771 | else |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1772 | chan = CR_CHAN(list[i]); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1773 | aref = CR_AREF(list[i]); |
| 1774 | range = CR_RANGE(list[i]); |
Haneen Mohammed | f0dff42 | 2015-03-13 14:29:30 +0300 | [diff] [blame] | 1775 | dither = (list[i] & CR_ALT_FILTER) != 0; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1776 | |
| 1777 | /* fix the external/internal range differences */ |
H Hartley Sweeten | 6293e35 | 2013-03-05 10:20:41 -0700 | [diff] [blame] | 1778 | range = ni_gainlkup[board->gainlkup][range]; |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1779 | if (devpriv->is_611x) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1780 | devpriv->ai_offset[i] = offset; |
| 1781 | else |
| 1782 | devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset; |
| 1783 | |
| 1784 | hi = 0; |
| 1785 | if ((list[i] & CR_ALT_SOURCE)) { |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1786 | if (devpriv->is_611x) |
H Hartley Sweeten | 5a92cac | 2014-06-19 10:20:35 -0700 | [diff] [blame] | 1787 | ni_writew(dev, CR_CHAN(list[i]) & 0x0003, |
H Hartley Sweeten | 0418da5 | 2015-05-01 15:00:07 -0700 | [diff] [blame] | 1788 | NI611X_CALIB_CHAN_SEL_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1789 | } else { |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1790 | if (devpriv->is_611x) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1791 | aref = AREF_DIFF; |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1792 | else if (devpriv->is_6143) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1793 | aref = AREF_OTHER; |
| 1794 | switch (aref) { |
| 1795 | case AREF_DIFF: |
H Hartley Sweeten | d504a6e | 2015-05-01 14:59:58 -0700 | [diff] [blame] | 1796 | hi |= NI_E_AI_CFG_HI_TYPE_DIFF; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1797 | break; |
| 1798 | case AREF_COMMON: |
H Hartley Sweeten | d504a6e | 2015-05-01 14:59:58 -0700 | [diff] [blame] | 1799 | hi |= NI_E_AI_CFG_HI_TYPE_COMMON; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1800 | break; |
| 1801 | case AREF_GROUND: |
H Hartley Sweeten | d504a6e | 2015-05-01 14:59:58 -0700 | [diff] [blame] | 1802 | hi |= NI_E_AI_CFG_HI_TYPE_GROUND; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1803 | break; |
| 1804 | case AREF_OTHER: |
| 1805 | break; |
| 1806 | } |
| 1807 | } |
H Hartley Sweeten | d504a6e | 2015-05-01 14:59:58 -0700 | [diff] [blame] | 1808 | hi |= NI_E_AI_CFG_HI_CHAN(chan); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1809 | |
H Hartley Sweeten | d504a6e | 2015-05-01 14:59:58 -0700 | [diff] [blame] | 1810 | ni_writew(dev, hi, NI_E_AI_CFG_HI_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1811 | |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1812 | if (!devpriv->is_6143) { |
H Hartley Sweeten | 76efac7 | 2015-05-01 14:59:57 -0700 | [diff] [blame] | 1813 | lo = NI_E_AI_CFG_LO_GAIN(range); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1814 | |
H Hartley Sweeten | 76efac7 | 2015-05-01 14:59:57 -0700 | [diff] [blame] | 1815 | if (i == n_chan - 1) |
| 1816 | lo |= NI_E_AI_CFG_LO_LAST_CHAN; |
| 1817 | if (dither) |
| 1818 | lo |= NI_E_AI_CFG_LO_DITHER; |
| 1819 | |
| 1820 | ni_writew(dev, lo, NI_E_AI_CFG_LO_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1821 | } |
| 1822 | } |
| 1823 | |
| 1824 | /* prime the channel/gain list */ |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1825 | if (!devpriv->is_611x && !devpriv->is_6143) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1826 | ni_prime_channelgain_list(dev); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1827 | } |
| 1828 | |
H Hartley Sweeten | 3d129c3 | 2014-05-28 16:26:43 -0700 | [diff] [blame] | 1829 | static int ni_ai_insn_read(struct comedi_device *dev, |
| 1830 | struct comedi_subdevice *s, |
| 1831 | struct comedi_insn *insn, |
| 1832 | unsigned int *data) |
| 1833 | { |
H Hartley Sweeten | 3d129c3 | 2014-05-28 16:26:43 -0700 | [diff] [blame] | 1834 | struct ni_private *devpriv = dev->private; |
Ian Abbott | bd1692b | 2016-11-14 20:16:21 +0000 | [diff] [blame] | 1835 | unsigned int mask = s->maxdata; |
H Hartley Sweeten | 3d129c3 | 2014-05-28 16:26:43 -0700 | [diff] [blame] | 1836 | int i, n; |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 1837 | unsigned int signbits; |
H Hartley Sweeten | 0557344 | 2014-08-25 15:23:50 -0700 | [diff] [blame] | 1838 | unsigned int d; |
H Hartley Sweeten | 3d129c3 | 2014-05-28 16:26:43 -0700 | [diff] [blame] | 1839 | unsigned long dl; |
| 1840 | |
H Hartley Sweeten | 817144a | 2014-07-14 12:23:51 -0700 | [diff] [blame] | 1841 | ni_load_channelgain_list(dev, s, 1, &insn->chanspec); |
H Hartley Sweeten | 3d129c3 | 2014-05-28 16:26:43 -0700 | [diff] [blame] | 1842 | |
| 1843 | ni_clear_ai_fifo(dev); |
| 1844 | |
| 1845 | signbits = devpriv->ai_offset[0]; |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1846 | if (devpriv->is_611x) { |
H Hartley Sweeten | 3d129c3 | 2014-05-28 16:26:43 -0700 | [diff] [blame] | 1847 | for (n = 0; n < num_adc_stages_611x; n++) { |
H Hartley Sweeten | 4c4d715 | 2015-05-01 14:58:59 -0700 | [diff] [blame] | 1848 | ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, |
| 1849 | NISTC_AI_CMD1_REG); |
H Hartley Sweeten | 3d129c3 | 2014-05-28 16:26:43 -0700 | [diff] [blame] | 1850 | udelay(1); |
| 1851 | } |
| 1852 | for (n = 0; n < insn->n; n++) { |
H Hartley Sweeten | 4c4d715 | 2015-05-01 14:58:59 -0700 | [diff] [blame] | 1853 | ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, |
| 1854 | NISTC_AI_CMD1_REG); |
H Hartley Sweeten | 3d129c3 | 2014-05-28 16:26:43 -0700 | [diff] [blame] | 1855 | /* The 611x has screwy 32-bit FIFOs. */ |
| 1856 | d = 0; |
| 1857 | for (i = 0; i < NI_TIMEOUT; i++) { |
H Hartley Sweeten | 906170b | 2015-05-01 14:59:52 -0700 | [diff] [blame] | 1858 | if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) { |
H Hartley Sweeten | 0418da5 | 2015-05-01 15:00:07 -0700 | [diff] [blame] | 1859 | d = ni_readl(dev, |
| 1860 | NI611X_AI_FIFO_DATA_REG); |
H Hartley Sweeten | 9c340ac | 2014-05-29 10:56:32 -0700 | [diff] [blame] | 1861 | d >>= 16; |
| 1862 | d &= 0xffff; |
H Hartley Sweeten | 3d129c3 | 2014-05-28 16:26:43 -0700 | [diff] [blame] | 1863 | break; |
| 1864 | } |
H Hartley Sweeten | 7b14fff | 2015-05-01 14:59:37 -0700 | [diff] [blame] | 1865 | if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) & |
| 1866 | NISTC_AI_STATUS1_FIFO_E)) { |
H Hartley Sweeten | 0418da5 | 2015-05-01 15:00:07 -0700 | [diff] [blame] | 1867 | d = ni_readl(dev, |
| 1868 | NI611X_AI_FIFO_DATA_REG); |
H Hartley Sweeten | 9c340ac | 2014-05-29 10:56:32 -0700 | [diff] [blame] | 1869 | d &= 0xffff; |
H Hartley Sweeten | 3d129c3 | 2014-05-28 16:26:43 -0700 | [diff] [blame] | 1870 | break; |
| 1871 | } |
| 1872 | } |
| 1873 | if (i == NI_TIMEOUT) { |
Haneen Mohammed | cd25503 | 2015-03-05 13:01:49 +0300 | [diff] [blame] | 1874 | dev_err(dev->class_dev, "timeout\n"); |
H Hartley Sweeten | 3d129c3 | 2014-05-28 16:26:43 -0700 | [diff] [blame] | 1875 | return -ETIME; |
| 1876 | } |
| 1877 | d += signbits; |
Ian Abbott | 745f7d0 | 2016-11-14 20:16:22 +0000 | [diff] [blame] | 1878 | data[n] = d & 0xffff; |
H Hartley Sweeten | 3d129c3 | 2014-05-28 16:26:43 -0700 | [diff] [blame] | 1879 | } |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1880 | } else if (devpriv->is_6143) { |
H Hartley Sweeten | 3d129c3 | 2014-05-28 16:26:43 -0700 | [diff] [blame] | 1881 | for (n = 0; n < insn->n; n++) { |
H Hartley Sweeten | 4c4d715 | 2015-05-01 14:58:59 -0700 | [diff] [blame] | 1882 | ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, |
| 1883 | NISTC_AI_CMD1_REG); |
H Hartley Sweeten | 3d129c3 | 2014-05-28 16:26:43 -0700 | [diff] [blame] | 1884 | |
H Hartley Sweeten | b6a0e5b | 2016-04-14 09:57:56 -0700 | [diff] [blame] | 1885 | /* |
| 1886 | * The 6143 has 32-bit FIFOs. You need to strobe a |
| 1887 | * bit to move a single 16bit stranded sample into |
| 1888 | * the FIFO. |
| 1889 | */ |
H Hartley Sweeten | 3d129c3 | 2014-05-28 16:26:43 -0700 | [diff] [blame] | 1890 | dl = 0; |
| 1891 | for (i = 0; i < NI_TIMEOUT; i++) { |
H Hartley Sweeten | ee3e21a | 2015-05-01 15:00:08 -0700 | [diff] [blame] | 1892 | if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & |
| 1893 | 0x01) { |
H Hartley Sweeten | 9c340ac | 2014-05-29 10:56:32 -0700 | [diff] [blame] | 1894 | /* Get stranded sample into FIFO */ |
H Hartley Sweeten | 5a92cac | 2014-06-19 10:20:35 -0700 | [diff] [blame] | 1895 | ni_writel(dev, 0x01, |
H Hartley Sweeten | ee3e21a | 2015-05-01 15:00:08 -0700 | [diff] [blame] | 1896 | NI6143_AI_FIFO_CTRL_REG); |
| 1897 | dl = ni_readl(dev, |
| 1898 | NI6143_AI_FIFO_DATA_REG); |
H Hartley Sweeten | 3d129c3 | 2014-05-28 16:26:43 -0700 | [diff] [blame] | 1899 | break; |
| 1900 | } |
| 1901 | } |
| 1902 | if (i == NI_TIMEOUT) { |
Haneen Mohammed | cd25503 | 2015-03-05 13:01:49 +0300 | [diff] [blame] | 1903 | dev_err(dev->class_dev, "timeout\n"); |
H Hartley Sweeten | 3d129c3 | 2014-05-28 16:26:43 -0700 | [diff] [blame] | 1904 | return -ETIME; |
| 1905 | } |
| 1906 | data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF; |
| 1907 | } |
| 1908 | } else { |
| 1909 | for (n = 0; n < insn->n; n++) { |
H Hartley Sweeten | 4c4d715 | 2015-05-01 14:58:59 -0700 | [diff] [blame] | 1910 | ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, |
| 1911 | NISTC_AI_CMD1_REG); |
H Hartley Sweeten | 3d129c3 | 2014-05-28 16:26:43 -0700 | [diff] [blame] | 1912 | for (i = 0; i < NI_TIMEOUT; i++) { |
H Hartley Sweeten | 7b14fff | 2015-05-01 14:59:37 -0700 | [diff] [blame] | 1913 | if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) & |
| 1914 | NISTC_AI_STATUS1_FIFO_E)) |
H Hartley Sweeten | 3d129c3 | 2014-05-28 16:26:43 -0700 | [diff] [blame] | 1915 | break; |
| 1916 | } |
| 1917 | if (i == NI_TIMEOUT) { |
Haneen Mohammed | cd25503 | 2015-03-05 13:01:49 +0300 | [diff] [blame] | 1918 | dev_err(dev->class_dev, "timeout\n"); |
H Hartley Sweeten | 3d129c3 | 2014-05-28 16:26:43 -0700 | [diff] [blame] | 1919 | return -ETIME; |
| 1920 | } |
H Hartley Sweeten | 1773321 | 2014-06-19 10:20:32 -0700 | [diff] [blame] | 1921 | if (devpriv->is_m_series) { |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 1922 | dl = ni_readl(dev, NI_M_AI_FIFO_DATA_REG); |
H Hartley Sweeten | 9c340ac | 2014-05-29 10:56:32 -0700 | [diff] [blame] | 1923 | dl &= mask; |
| 1924 | data[n] = dl; |
H Hartley Sweeten | 3d129c3 | 2014-05-28 16:26:43 -0700 | [diff] [blame] | 1925 | } else { |
H Hartley Sweeten | 363f570 | 2015-05-01 14:59:56 -0700 | [diff] [blame] | 1926 | d = ni_readw(dev, NI_E_AI_FIFO_DATA_REG); |
H Hartley Sweeten | b6a0e5b | 2016-04-14 09:57:56 -0700 | [diff] [blame] | 1927 | d += signbits; |
Ian Abbott | 745f7d0 | 2016-11-14 20:16:22 +0000 | [diff] [blame] | 1928 | data[n] = d & 0xffff; |
H Hartley Sweeten | 3d129c3 | 2014-05-28 16:26:43 -0700 | [diff] [blame] | 1929 | } |
| 1930 | } |
| 1931 | } |
| 1932 | return insn->n; |
| 1933 | } |
| 1934 | |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 1935 | static int ni_ns_to_timer(const struct comedi_device *dev, |
| 1936 | unsigned int nanosec, unsigned int flags) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1937 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 1938 | struct ni_private *devpriv = dev->private; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1939 | int divider; |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 1940 | |
Ian Abbott | 3280c2d | 2014-09-03 13:45:57 +0100 | [diff] [blame] | 1941 | switch (flags & CMDF_ROUND_MASK) { |
| 1942 | case CMDF_ROUND_NEAREST: |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1943 | default: |
Bhaktipriya Shridhar | 1e5a05d | 2016-02-21 16:13:01 +0530 | [diff] [blame] | 1944 | divider = DIV_ROUND_CLOSEST(nanosec, devpriv->clock_ns); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1945 | break; |
Ian Abbott | 3280c2d | 2014-09-03 13:45:57 +0100 | [diff] [blame] | 1946 | case CMDF_ROUND_DOWN: |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1947 | divider = (nanosec) / devpriv->clock_ns; |
| 1948 | break; |
Ian Abbott | 3280c2d | 2014-09-03 13:45:57 +0100 | [diff] [blame] | 1949 | case CMDF_ROUND_UP: |
Bhaktipriya Shridhar | 7f9d2b1 | 2016-03-10 00:05:16 +0530 | [diff] [blame] | 1950 | divider = DIV_ROUND_UP(nanosec, devpriv->clock_ns); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1951 | break; |
| 1952 | } |
| 1953 | return divider - 1; |
| 1954 | } |
| 1955 | |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 1956 | static unsigned int ni_timer_to_ns(const struct comedi_device *dev, int timer) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1957 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 1958 | struct ni_private *devpriv = dev->private; |
| 1959 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1960 | return devpriv->clock_ns * (timer + 1); |
| 1961 | } |
| 1962 | |
H Hartley Sweeten | 19d9212 | 2016-05-02 10:11:36 -0700 | [diff] [blame] | 1963 | static void ni_cmd_set_mite_transfer(struct mite_ring *ring, |
Spencer E. Olson | 6aab7fe | 2016-01-27 14:28:28 -0700 | [diff] [blame] | 1964 | struct comedi_subdevice *sdev, |
| 1965 | const struct comedi_cmd *cmd, |
| 1966 | unsigned int max_count) { |
| 1967 | #ifdef PCIDMA |
| 1968 | unsigned int nbytes = max_count; |
| 1969 | |
| 1970 | if (cmd->stop_arg > 0 && cmd->stop_arg < max_count) |
| 1971 | nbytes = cmd->stop_arg; |
| 1972 | nbytes *= comedi_bytes_per_scan(sdev); |
| 1973 | |
| 1974 | if (nbytes > sdev->async->prealloc_bufsz) { |
| 1975 | if (cmd->stop_arg > 0) |
| 1976 | dev_err(sdev->device->class_dev, |
| 1977 | "ni_cmd_set_mite_transfer: tried exact data transfer limits greater than buffer size\n"); |
| 1978 | |
| 1979 | /* |
| 1980 | * we can only transfer up to the size of the buffer. In this |
| 1981 | * case, the user is expected to continue to write into the |
| 1982 | * comedi buffer (already implemented as a ring buffer). |
| 1983 | */ |
| 1984 | nbytes = sdev->async->prealloc_bufsz; |
| 1985 | } |
| 1986 | |
| 1987 | mite_init_ring_descriptors(ring, sdev, nbytes); |
| 1988 | #else |
| 1989 | dev_err(sdev->device->class_dev, |
| 1990 | "ni_cmd_set_mite_transfer: exact data transfer limits not implemented yet without DMA\n"); |
| 1991 | #endif |
| 1992 | } |
| 1993 | |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 1994 | static unsigned int ni_min_ai_scan_period_ns(struct comedi_device *dev, |
| 1995 | unsigned int num_channels) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 1996 | { |
Ian Abbott | 7cf94ad | 2014-09-09 11:26:44 +0100 | [diff] [blame] | 1997 | const struct ni_board_struct *board = dev->board_ptr; |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 1998 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | 6293e35 | 2013-03-05 10:20:41 -0700 | [diff] [blame] | 1999 | |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 2000 | /* simultaneously-sampled inputs */ |
| 2001 | if (devpriv->is_611x || devpriv->is_6143) |
H Hartley Sweeten | 6293e35 | 2013-03-05 10:20:41 -0700 | [diff] [blame] | 2002 | return board->ai_speed; |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 2003 | |
| 2004 | /* multiplexed inputs */ |
H Hartley Sweeten | 6293e35 | 2013-03-05 10:20:41 -0700 | [diff] [blame] | 2005 | return board->ai_speed * num_channels; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2006 | } |
| 2007 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 2008 | static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 2009 | struct comedi_cmd *cmd) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2010 | { |
Ian Abbott | 7cf94ad | 2014-09-09 11:26:44 +0100 | [diff] [blame] | 2011 | const struct ni_board_struct *board = dev->board_ptr; |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 2012 | struct ni_private *devpriv = dev->private; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2013 | int err = 0; |
H Hartley Sweeten | ebb657b | 2014-04-17 10:08:11 -0700 | [diff] [blame] | 2014 | unsigned int tmp; |
H Hartley Sweeten | 27020ff | 2012-09-26 14:11:10 -0700 | [diff] [blame] | 2015 | unsigned int sources; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2016 | |
H Hartley Sweeten | 27020ff | 2012-09-26 14:11:10 -0700 | [diff] [blame] | 2017 | /* Step 1 : check if triggers are trivially valid */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2018 | |
Ian Abbott | 311fd9b | 2015-03-27 19:14:24 +0000 | [diff] [blame] | 2019 | err |= comedi_check_trigger_src(&cmd->start_src, |
H Hartley Sweeten | 27020ff | 2012-09-26 14:11:10 -0700 | [diff] [blame] | 2020 | TRIG_NOW | TRIG_INT | TRIG_EXT); |
Ian Abbott | 311fd9b | 2015-03-27 19:14:24 +0000 | [diff] [blame] | 2021 | err |= comedi_check_trigger_src(&cmd->scan_begin_src, |
H Hartley Sweeten | 27020ff | 2012-09-26 14:11:10 -0700 | [diff] [blame] | 2022 | TRIG_TIMER | TRIG_EXT); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2023 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2024 | sources = TRIG_TIMER | TRIG_EXT; |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 2025 | if (devpriv->is_611x || devpriv->is_6143) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2026 | sources |= TRIG_NOW; |
Ian Abbott | 311fd9b | 2015-03-27 19:14:24 +0000 | [diff] [blame] | 2027 | err |= comedi_check_trigger_src(&cmd->convert_src, sources); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2028 | |
Ian Abbott | 311fd9b | 2015-03-27 19:14:24 +0000 | [diff] [blame] | 2029 | err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); |
| 2030 | err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2031 | |
| 2032 | if (err) |
| 2033 | return 1; |
| 2034 | |
H Hartley Sweeten | 27020ff | 2012-09-26 14:11:10 -0700 | [diff] [blame] | 2035 | /* Step 2a : make sure trigger sources are unique */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2036 | |
Ian Abbott | 311fd9b | 2015-03-27 19:14:24 +0000 | [diff] [blame] | 2037 | err |= comedi_check_trigger_is_unique(cmd->start_src); |
| 2038 | err |= comedi_check_trigger_is_unique(cmd->scan_begin_src); |
| 2039 | err |= comedi_check_trigger_is_unique(cmd->convert_src); |
| 2040 | err |= comedi_check_trigger_is_unique(cmd->stop_src); |
H Hartley Sweeten | 27020ff | 2012-09-26 14:11:10 -0700 | [diff] [blame] | 2041 | |
| 2042 | /* Step 2b : and mutually compatible */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2043 | |
| 2044 | if (err) |
| 2045 | return 2; |
| 2046 | |
H Hartley Sweeten | c3be5c7 | 2012-11-13 18:00:36 -0700 | [diff] [blame] | 2047 | /* Step 3: check if arguments are trivially valid */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2048 | |
H Hartley Sweeten | ebb657b | 2014-04-17 10:08:11 -0700 | [diff] [blame] | 2049 | switch (cmd->start_src) { |
| 2050 | case TRIG_NOW: |
| 2051 | case TRIG_INT: |
Ian Abbott | 311fd9b | 2015-03-27 19:14:24 +0000 | [diff] [blame] | 2052 | err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0); |
H Hartley Sweeten | ebb657b | 2014-04-17 10:08:11 -0700 | [diff] [blame] | 2053 | break; |
| 2054 | case TRIG_EXT: |
| 2055 | tmp = CR_CHAN(cmd->start_arg); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2056 | |
| 2057 | if (tmp > 16) |
| 2058 | tmp = 16; |
| 2059 | tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE)); |
Ian Abbott | 311fd9b | 2015-03-27 19:14:24 +0000 | [diff] [blame] | 2060 | err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp); |
H Hartley Sweeten | ebb657b | 2014-04-17 10:08:11 -0700 | [diff] [blame] | 2061 | break; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2062 | } |
H Hartley Sweeten | c3be5c7 | 2012-11-13 18:00:36 -0700 | [diff] [blame] | 2063 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2064 | if (cmd->scan_begin_src == TRIG_TIMER) { |
Ian Abbott | 311fd9b | 2015-03-27 19:14:24 +0000 | [diff] [blame] | 2065 | err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg, |
H Hartley Sweeten | c3be5c7 | 2012-11-13 18:00:36 -0700 | [diff] [blame] | 2066 | ni_min_ai_scan_period_ns(dev, cmd->chanlist_len)); |
Ian Abbott | 311fd9b | 2015-03-27 19:14:24 +0000 | [diff] [blame] | 2067 | err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, |
| 2068 | devpriv->clock_ns * |
| 2069 | 0xffffff); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2070 | } else if (cmd->scan_begin_src == TRIG_EXT) { |
| 2071 | /* external trigger */ |
| 2072 | unsigned int tmp = CR_CHAN(cmd->scan_begin_arg); |
| 2073 | |
| 2074 | if (tmp > 16) |
| 2075 | tmp = 16; |
| 2076 | tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE)); |
Ian Abbott | 311fd9b | 2015-03-27 19:14:24 +0000 | [diff] [blame] | 2077 | err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, tmp); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2078 | } else { /* TRIG_OTHER */ |
Ian Abbott | 311fd9b | 2015-03-27 19:14:24 +0000 | [diff] [blame] | 2079 | err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2080 | } |
H Hartley Sweeten | c3be5c7 | 2012-11-13 18:00:36 -0700 | [diff] [blame] | 2081 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2082 | if (cmd->convert_src == TRIG_TIMER) { |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 2083 | if (devpriv->is_611x || devpriv->is_6143) { |
Ian Abbott | 311fd9b | 2015-03-27 19:14:24 +0000 | [diff] [blame] | 2084 | err |= comedi_check_trigger_arg_is(&cmd->convert_arg, |
| 2085 | 0); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2086 | } else { |
Ian Abbott | 311fd9b | 2015-03-27 19:14:24 +0000 | [diff] [blame] | 2087 | err |= comedi_check_trigger_arg_min(&cmd->convert_arg, |
| 2088 | board->ai_speed); |
| 2089 | err |= comedi_check_trigger_arg_max(&cmd->convert_arg, |
| 2090 | devpriv->clock_ns * |
| 2091 | 0xffff); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2092 | } |
| 2093 | } else if (cmd->convert_src == TRIG_EXT) { |
| 2094 | /* external trigger */ |
| 2095 | unsigned int tmp = CR_CHAN(cmd->convert_arg); |
| 2096 | |
| 2097 | if (tmp > 16) |
| 2098 | tmp = 16; |
| 2099 | tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT)); |
Ian Abbott | 311fd9b | 2015-03-27 19:14:24 +0000 | [diff] [blame] | 2100 | err |= comedi_check_trigger_arg_is(&cmd->convert_arg, tmp); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2101 | } else if (cmd->convert_src == TRIG_NOW) { |
Ian Abbott | 311fd9b | 2015-03-27 19:14:24 +0000 | [diff] [blame] | 2102 | err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2103 | } |
| 2104 | |
Ian Abbott | 311fd9b | 2015-03-27 19:14:24 +0000 | [diff] [blame] | 2105 | err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg, |
| 2106 | cmd->chanlist_len); |
H Hartley Sweeten | c3be5c7 | 2012-11-13 18:00:36 -0700 | [diff] [blame] | 2107 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2108 | if (cmd->stop_src == TRIG_COUNT) { |
| 2109 | unsigned int max_count = 0x01000000; |
| 2110 | |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 2111 | if (devpriv->is_611x) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2112 | max_count -= num_adc_stages_611x; |
Ian Abbott | 311fd9b | 2015-03-27 19:14:24 +0000 | [diff] [blame] | 2113 | err |= comedi_check_trigger_arg_max(&cmd->stop_arg, max_count); |
| 2114 | err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2115 | } else { |
| 2116 | /* TRIG_NONE */ |
Ian Abbott | 311fd9b | 2015-03-27 19:14:24 +0000 | [diff] [blame] | 2117 | err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2118 | } |
| 2119 | |
| 2120 | if (err) |
| 2121 | return 3; |
| 2122 | |
| 2123 | /* step 4: fix up any arguments */ |
| 2124 | |
| 2125 | if (cmd->scan_begin_src == TRIG_TIMER) { |
| 2126 | tmp = cmd->scan_begin_arg; |
| 2127 | cmd->scan_begin_arg = |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 2128 | ni_timer_to_ns(dev, ni_ns_to_timer(dev, |
| 2129 | cmd->scan_begin_arg, |
H Hartley Sweeten | a207c12 | 2014-07-18 17:01:16 -0700 | [diff] [blame] | 2130 | cmd->flags)); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2131 | if (tmp != cmd->scan_begin_arg) |
| 2132 | err++; |
| 2133 | } |
| 2134 | if (cmd->convert_src == TRIG_TIMER) { |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 2135 | if (!devpriv->is_611x && !devpriv->is_6143) { |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2136 | tmp = cmd->convert_arg; |
| 2137 | cmd->convert_arg = |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 2138 | ni_timer_to_ns(dev, ni_ns_to_timer(dev, |
| 2139 | cmd->convert_arg, |
H Hartley Sweeten | a207c12 | 2014-07-18 17:01:16 -0700 | [diff] [blame] | 2140 | cmd->flags)); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2141 | if (tmp != cmd->convert_arg) |
| 2142 | err++; |
| 2143 | if (cmd->scan_begin_src == TRIG_TIMER && |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 2144 | cmd->scan_begin_arg < |
| 2145 | cmd->convert_arg * cmd->scan_end_arg) { |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2146 | cmd->scan_begin_arg = |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 2147 | cmd->convert_arg * cmd->scan_end_arg; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2148 | err++; |
| 2149 | } |
| 2150 | } |
| 2151 | } |
| 2152 | |
| 2153 | if (err) |
| 2154 | return 4; |
| 2155 | |
| 2156 | return 0; |
| 2157 | } |
| 2158 | |
H Hartley Sweeten | 8511b85 | 2014-05-28 16:26:38 -0700 | [diff] [blame] | 2159 | static int ni_ai_inttrig(struct comedi_device *dev, |
| 2160 | struct comedi_subdevice *s, |
| 2161 | unsigned int trig_num) |
| 2162 | { |
| 2163 | struct ni_private *devpriv = dev->private; |
| 2164 | struct comedi_cmd *cmd = &s->async->cmd; |
| 2165 | |
| 2166 | if (trig_num != cmd->start_arg) |
| 2167 | return -EINVAL; |
| 2168 | |
H Hartley Sweeten | a1da35a | 2015-05-01 14:58:56 -0700 | [diff] [blame] | 2169 | ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | devpriv->ai_cmd2, |
| 2170 | NISTC_AI_CMD2_REG); |
H Hartley Sweeten | 8511b85 | 2014-05-28 16:26:38 -0700 | [diff] [blame] | 2171 | s->async->inttrig = NULL; |
| 2172 | |
| 2173 | return 1; |
| 2174 | } |
| 2175 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 2176 | static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2177 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 2178 | struct ni_private *devpriv = dev->private; |
Bill Pemberton | ea6d0d4 | 2009-03-16 22:05:47 -0400 | [diff] [blame] | 2179 | const struct comedi_cmd *cmd = &s->async->cmd; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2180 | int timer; |
| 2181 | int mode1 = 0; /* mode1 is needed for both stop and convert */ |
| 2182 | int mode2 = 0; |
| 2183 | int start_stop_select = 0; |
| 2184 | unsigned int stop_count; |
| 2185 | int interrupt_a_enable = 0; |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 2186 | unsigned int ai_trig; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2187 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2188 | if (dev->irq == 0) { |
H Hartley Sweeten | 5ac1d82 | 2014-07-17 11:57:33 -0700 | [diff] [blame] | 2189 | dev_err(dev->class_dev, "cannot run command without an irq\n"); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2190 | return -EIO; |
| 2191 | } |
| 2192 | ni_clear_ai_fifo(dev); |
| 2193 | |
H Hartley Sweeten | 817144a | 2014-07-14 12:23:51 -0700 | [diff] [blame] | 2194 | ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2195 | |
| 2196 | /* start configuration */ |
H Hartley Sweeten | 707502f | 2015-05-01 14:59:25 -0700 | [diff] [blame] | 2197 | ni_stc_writew(dev, NISTC_RESET_AI_CFG_START, NISTC_RESET_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2198 | |
H Hartley Sweeten | bd474a0 | 2016-04-14 09:57:55 -0700 | [diff] [blame] | 2199 | /* |
| 2200 | * Disable analog triggering for now, since it interferes |
| 2201 | * with the use of pfi0. |
| 2202 | */ |
H Hartley Sweeten | 27cf6c0 | 2015-05-01 14:59:17 -0700 | [diff] [blame] | 2203 | devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_ENA; |
| 2204 | ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2205 | |
H Hartley Sweeten | f878071 | 2015-05-01 14:59:19 -0700 | [diff] [blame] | 2206 | ai_trig = NISTC_AI_TRIG_START2_SEL(0) | NISTC_AI_TRIG_START1_SYNC; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2207 | switch (cmd->start_src) { |
| 2208 | case TRIG_INT: |
| 2209 | case TRIG_NOW: |
H Hartley Sweeten | f878071 | 2015-05-01 14:59:19 -0700 | [diff] [blame] | 2210 | ai_trig |= NISTC_AI_TRIG_START1_EDGE | |
H Hartley Sweeten | 1645b55 | 2015-05-11 10:22:45 -0700 | [diff] [blame] | 2211 | NISTC_AI_TRIG_START1_SEL(0); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2212 | break; |
| 2213 | case TRIG_EXT: |
H Hartley Sweeten | f878071 | 2015-05-01 14:59:19 -0700 | [diff] [blame] | 2214 | ai_trig |= NISTC_AI_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) + |
| 2215 | 1); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2216 | |
H Hartley Sweeten | f878071 | 2015-05-01 14:59:19 -0700 | [diff] [blame] | 2217 | if (cmd->start_arg & CR_INVERT) |
| 2218 | ai_trig |= NISTC_AI_TRIG_START1_POLARITY; |
| 2219 | if (cmd->start_arg & CR_EDGE) |
| 2220 | ai_trig |= NISTC_AI_TRIG_START1_EDGE; |
| 2221 | break; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2222 | } |
H Hartley Sweeten | f878071 | 2015-05-01 14:59:19 -0700 | [diff] [blame] | 2223 | ni_stc_writew(dev, ai_trig, NISTC_AI_TRIG_SEL_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2224 | |
H Hartley Sweeten | b134cc5 | 2015-05-01 14:59:04 -0700 | [diff] [blame] | 2225 | mode2 &= ~NISTC_AI_MODE2_PRE_TRIGGER; |
| 2226 | mode2 &= ~NISTC_AI_MODE2_SC_INIT_LOAD_SRC; |
| 2227 | mode2 &= ~NISTC_AI_MODE2_SC_RELOAD_MODE; |
| 2228 | ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2229 | |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 2230 | if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) { |
H Hartley Sweeten | 3e90889 | 2015-05-01 14:59:18 -0700 | [diff] [blame] | 2231 | /* logic low */ |
| 2232 | start_stop_select |= NISTC_AI_STOP_POLARITY | |
| 2233 | NISTC_AI_STOP_SEL(31) | |
| 2234 | NISTC_AI_STOP_SYNC; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2235 | } else { |
H Hartley Sweeten | 3e90889 | 2015-05-01 14:59:18 -0700 | [diff] [blame] | 2236 | /* ai configuration memory */ |
| 2237 | start_stop_select |= NISTC_AI_STOP_SEL(19); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2238 | } |
H Hartley Sweeten | 3e90889 | 2015-05-01 14:59:18 -0700 | [diff] [blame] | 2239 | ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2240 | |
| 2241 | devpriv->ai_cmd2 = 0; |
| 2242 | switch (cmd->stop_src) { |
| 2243 | case TRIG_COUNT: |
| 2244 | stop_count = cmd->stop_arg - 1; |
| 2245 | |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 2246 | if (devpriv->is_611x) { |
Bill Pemberton | 2696fb5 | 2009-03-27 11:29:34 -0400 | [diff] [blame] | 2247 | /* have to take 3 stage adc pipeline into account */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2248 | stop_count += num_adc_stages_611x; |
| 2249 | } |
| 2250 | /* stage number of scans */ |
H Hartley Sweeten | a2c5373 | 2015-05-01 14:59:05 -0700 | [diff] [blame] | 2251 | ni_stc_writel(dev, stop_count, NISTC_AI_SC_LOADA_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2252 | |
H Hartley Sweeten | bd358f5 | 2015-05-01 14:59:03 -0700 | [diff] [blame] | 2253 | mode1 |= NISTC_AI_MODE1_START_STOP | |
| 2254 | NISTC_AI_MODE1_RSVD | |
| 2255 | NISTC_AI_MODE1_TRIGGER_ONCE; |
| 2256 | ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2257 | /* load SC (Scan Count) */ |
H Hartley Sweeten | 4c4d715 | 2015-05-01 14:58:59 -0700 | [diff] [blame] | 2258 | ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2259 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2260 | if (stop_count == 0) { |
H Hartley Sweeten | a1da35a | 2015-05-01 14:58:56 -0700 | [diff] [blame] | 2261 | devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS; |
H Hartley Sweeten | 5cca26a | 2015-05-01 14:59:26 -0700 | [diff] [blame] | 2262 | interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP; |
H Hartley Sweeten | b6a0e5b | 2016-04-14 09:57:56 -0700 | [diff] [blame] | 2263 | /* |
| 2264 | * This is required to get the last sample for |
| 2265 | * chanlist_len > 1, not sure why. |
| 2266 | */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2267 | if (cmd->chanlist_len > 1) |
H Hartley Sweeten | 3e90889 | 2015-05-01 14:59:18 -0700 | [diff] [blame] | 2268 | start_stop_select |= NISTC_AI_STOP_POLARITY | |
| 2269 | NISTC_AI_STOP_EDGE; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2270 | } |
| 2271 | break; |
| 2272 | case TRIG_NONE: |
| 2273 | /* stage number of scans */ |
H Hartley Sweeten | a2c5373 | 2015-05-01 14:59:05 -0700 | [diff] [blame] | 2274 | ni_stc_writel(dev, 0, NISTC_AI_SC_LOADA_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2275 | |
H Hartley Sweeten | bd358f5 | 2015-05-01 14:59:03 -0700 | [diff] [blame] | 2276 | mode1 |= NISTC_AI_MODE1_START_STOP | |
| 2277 | NISTC_AI_MODE1_RSVD | |
| 2278 | NISTC_AI_MODE1_CONTINUOUS; |
| 2279 | ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2280 | |
| 2281 | /* load SC (Scan Count) */ |
H Hartley Sweeten | 4c4d715 | 2015-05-01 14:58:59 -0700 | [diff] [blame] | 2282 | ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2283 | break; |
| 2284 | } |
| 2285 | |
| 2286 | switch (cmd->scan_begin_src) { |
| 2287 | case TRIG_TIMER: |
| 2288 | /* |
H Hartley Sweeten | 3e90889 | 2015-05-01 14:59:18 -0700 | [diff] [blame] | 2289 | * stop bits for non 611x boards |
H Hartley Sweeten | c7edadc | 2015-05-01 14:59:36 -0700 | [diff] [blame] | 2290 | * NISTC_AI_MODE3_SI_TRIG_DELAY=0 |
H Hartley Sweeten | 3e90889 | 2015-05-01 14:59:18 -0700 | [diff] [blame] | 2291 | * NISTC_AI_MODE2_PRE_TRIGGER=0 |
| 2292 | * NISTC_AI_START_STOP_REG: |
| 2293 | * NISTC_AI_START_POLARITY=0 (?) rising edge |
| 2294 | * NISTC_AI_START_EDGE=1 edge triggered |
| 2295 | * NISTC_AI_START_SYNC=1 (?) |
| 2296 | * NISTC_AI_START_SEL=0 SI_TC |
| 2297 | * NISTC_AI_STOP_POLARITY=0 rising edge |
| 2298 | * NISTC_AI_STOP_EDGE=0 level |
| 2299 | * NISTC_AI_STOP_SYNC=1 |
| 2300 | * NISTC_AI_STOP_SEL=19 external pin (configuration mem) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2301 | */ |
H Hartley Sweeten | 3e90889 | 2015-05-01 14:59:18 -0700 | [diff] [blame] | 2302 | start_stop_select |= NISTC_AI_START_EDGE | NISTC_AI_START_SYNC; |
| 2303 | ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2304 | |
H Hartley Sweeten | b134cc5 | 2015-05-01 14:59:04 -0700 | [diff] [blame] | 2305 | mode2 &= ~NISTC_AI_MODE2_SI_INIT_LOAD_SRC; /* A */ |
| 2306 | mode2 |= NISTC_AI_MODE2_SI_RELOAD_MODE(0); |
| 2307 | /* mode2 |= NISTC_AI_MODE2_SC_RELOAD_MODE; */ |
| 2308 | ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2309 | |
| 2310 | /* load SI */ |
| 2311 | timer = ni_ns_to_timer(dev, cmd->scan_begin_arg, |
Ian Abbott | 3280c2d | 2014-09-03 13:45:57 +0100 | [diff] [blame] | 2312 | CMDF_ROUND_NEAREST); |
H Hartley Sweeten | a2c5373 | 2015-05-01 14:59:05 -0700 | [diff] [blame] | 2313 | ni_stc_writel(dev, timer, NISTC_AI_SI_LOADA_REG); |
H Hartley Sweeten | 4c4d715 | 2015-05-01 14:58:59 -0700 | [diff] [blame] | 2314 | ni_stc_writew(dev, NISTC_AI_CMD1_SI_LOAD, NISTC_AI_CMD1_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2315 | break; |
| 2316 | case TRIG_EXT: |
| 2317 | if (cmd->scan_begin_arg & CR_EDGE) |
H Hartley Sweeten | 3e90889 | 2015-05-01 14:59:18 -0700 | [diff] [blame] | 2318 | start_stop_select |= NISTC_AI_START_EDGE; |
| 2319 | if (cmd->scan_begin_arg & CR_INVERT) /* falling edge */ |
| 2320 | start_stop_select |= NISTC_AI_START_POLARITY; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2321 | if (cmd->scan_begin_src != cmd->convert_src || |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 2322 | (cmd->scan_begin_arg & ~CR_EDGE) != |
| 2323 | (cmd->convert_arg & ~CR_EDGE)) |
H Hartley Sweeten | 3e90889 | 2015-05-01 14:59:18 -0700 | [diff] [blame] | 2324 | start_stop_select |= NISTC_AI_START_SYNC; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2325 | start_stop_select |= |
H Hartley Sweeten | 3e90889 | 2015-05-01 14:59:18 -0700 | [diff] [blame] | 2326 | NISTC_AI_START_SEL(1 + CR_CHAN(cmd->scan_begin_arg)); |
| 2327 | ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2328 | break; |
| 2329 | } |
| 2330 | |
| 2331 | switch (cmd->convert_src) { |
| 2332 | case TRIG_TIMER: |
| 2333 | case TRIG_NOW: |
| 2334 | if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW) |
| 2335 | timer = 1; |
| 2336 | else |
| 2337 | timer = ni_ns_to_timer(dev, cmd->convert_arg, |
Ian Abbott | 3280c2d | 2014-09-03 13:45:57 +0100 | [diff] [blame] | 2338 | CMDF_ROUND_NEAREST); |
H Hartley Sweeten | 00b14b1 | 2014-06-19 10:20:34 -0700 | [diff] [blame] | 2339 | /* 0,0 does not work */ |
H Hartley Sweeten | a2c5373 | 2015-05-01 14:59:05 -0700 | [diff] [blame] | 2340 | ni_stc_writew(dev, 1, NISTC_AI_SI2_LOADA_REG); |
| 2341 | ni_stc_writew(dev, timer, NISTC_AI_SI2_LOADB_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2342 | |
H Hartley Sweeten | b134cc5 | 2015-05-01 14:59:04 -0700 | [diff] [blame] | 2343 | mode2 &= ~NISTC_AI_MODE2_SI2_INIT_LOAD_SRC; /* A */ |
| 2344 | mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE; /* alternate */ |
| 2345 | ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2346 | |
H Hartley Sweeten | 4c4d715 | 2015-05-01 14:58:59 -0700 | [diff] [blame] | 2347 | ni_stc_writew(dev, NISTC_AI_CMD1_SI2_LOAD, NISTC_AI_CMD1_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2348 | |
H Hartley Sweeten | b134cc5 | 2015-05-01 14:59:04 -0700 | [diff] [blame] | 2349 | mode2 |= NISTC_AI_MODE2_SI2_INIT_LOAD_SRC; /* B */ |
| 2350 | mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE; /* alternate */ |
| 2351 | ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2352 | break; |
| 2353 | case TRIG_EXT: |
Spencer E. Olson | f08a28e | 2016-01-12 11:05:10 -0700 | [diff] [blame] | 2354 | mode1 |= NISTC_AI_MODE1_CONVERT_SRC(1 + |
| 2355 | CR_CHAN(cmd->convert_arg)); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2356 | if ((cmd->convert_arg & CR_INVERT) == 0) |
H Hartley Sweeten | bd358f5 | 2015-05-01 14:59:03 -0700 | [diff] [blame] | 2357 | mode1 |= NISTC_AI_MODE1_CONVERT_POLARITY; |
| 2358 | ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2359 | |
H Hartley Sweeten | b134cc5 | 2015-05-01 14:59:04 -0700 | [diff] [blame] | 2360 | mode2 |= NISTC_AI_MODE2_SC_GATE_ENA | |
| 2361 | NISTC_AI_MODE2_START_STOP_GATE_ENA; |
| 2362 | ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2363 | |
| 2364 | break; |
| 2365 | } |
| 2366 | |
| 2367 | if (dev->irq) { |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2368 | /* interrupt on FIFO, errors, SC_TC */ |
H Hartley Sweeten | 5cca26a | 2015-05-01 14:59:26 -0700 | [diff] [blame] | 2369 | interrupt_a_enable |= NISTC_INTA_ENA_AI_ERR | |
| 2370 | NISTC_INTA_ENA_AI_SC_TC; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2371 | |
| 2372 | #ifndef PCIDMA |
H Hartley Sweeten | 5cca26a | 2015-05-01 14:59:26 -0700 | [diff] [blame] | 2373 | interrupt_a_enable |= NISTC_INTA_ENA_AI_FIFO; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2374 | #endif |
| 2375 | |
H Hartley Sweeten | a1da35a | 2015-05-01 14:58:56 -0700 | [diff] [blame] | 2376 | if ((cmd->flags & CMDF_WAKE_EOS) || |
| 2377 | (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)) { |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2378 | /* wake on end-of-scan */ |
| 2379 | devpriv->aimode = AIMODE_SCAN; |
| 2380 | } else { |
| 2381 | devpriv->aimode = AIMODE_HALF_FULL; |
| 2382 | } |
| 2383 | |
| 2384 | switch (devpriv->aimode) { |
| 2385 | case AIMODE_HALF_FULL: |
H Hartley Sweeten | b6a0e5b | 2016-04-14 09:57:56 -0700 | [diff] [blame] | 2386 | /* FIFO interrupts and DMA requests on half-full */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2387 | #ifdef PCIDMA |
H Hartley Sweeten | c7edadc | 2015-05-01 14:59:36 -0700 | [diff] [blame] | 2388 | ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF_E, |
| 2389 | NISTC_AI_MODE3_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2390 | #else |
H Hartley Sweeten | c7edadc | 2015-05-01 14:59:36 -0700 | [diff] [blame] | 2391 | ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF, |
| 2392 | NISTC_AI_MODE3_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2393 | #endif |
| 2394 | break; |
| 2395 | case AIMODE_SAMPLE: |
| 2396 | /*generate FIFO interrupts on non-empty */ |
H Hartley Sweeten | c7edadc | 2015-05-01 14:59:36 -0700 | [diff] [blame] | 2397 | ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE, |
| 2398 | NISTC_AI_MODE3_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2399 | break; |
| 2400 | case AIMODE_SCAN: |
| 2401 | #ifdef PCIDMA |
H Hartley Sweeten | c7edadc | 2015-05-01 14:59:36 -0700 | [diff] [blame] | 2402 | ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE, |
| 2403 | NISTC_AI_MODE3_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2404 | #else |
H Hartley Sweeten | c7edadc | 2015-05-01 14:59:36 -0700 | [diff] [blame] | 2405 | ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF, |
| 2406 | NISTC_AI_MODE3_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2407 | #endif |
H Hartley Sweeten | 5cca26a | 2015-05-01 14:59:26 -0700 | [diff] [blame] | 2408 | interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2409 | break; |
| 2410 | default: |
| 2411 | break; |
| 2412 | } |
| 2413 | |
H Hartley Sweeten | 00b14b1 | 2014-06-19 10:20:34 -0700 | [diff] [blame] | 2414 | /* clear interrupts */ |
H Hartley Sweeten | 480456d | 2015-05-01 14:58:54 -0700 | [diff] [blame] | 2415 | ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2416 | |
H Hartley Sweeten | 5cca26a | 2015-05-01 14:59:26 -0700 | [diff] [blame] | 2417 | ni_set_bits(dev, NISTC_INTA_ENA_REG, interrupt_a_enable, 1); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2418 | } else { |
| 2419 | /* interrupt on nothing */ |
H Hartley Sweeten | 5cca26a | 2015-05-01 14:59:26 -0700 | [diff] [blame] | 2420 | ni_set_bits(dev, NISTC_INTA_ENA_REG, ~0, 0); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2421 | |
| 2422 | /* XXX start polling if necessary */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2423 | } |
| 2424 | |
| 2425 | /* end configuration */ |
H Hartley Sweeten | 707502f | 2015-05-01 14:59:25 -0700 | [diff] [blame] | 2426 | ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2427 | |
| 2428 | switch (cmd->scan_begin_src) { |
| 2429 | case TRIG_TIMER: |
H Hartley Sweeten | 4c4d715 | 2015-05-01 14:58:59 -0700 | [diff] [blame] | 2430 | ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM | |
| 2431 | NISTC_AI_CMD1_SI_ARM | |
| 2432 | NISTC_AI_CMD1_DIV_ARM | |
| 2433 | NISTC_AI_CMD1_SC_ARM, |
| 2434 | NISTC_AI_CMD1_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2435 | break; |
| 2436 | case TRIG_EXT: |
H Hartley Sweeten | 4c4d715 | 2015-05-01 14:58:59 -0700 | [diff] [blame] | 2437 | ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM | |
| 2438 | NISTC_AI_CMD1_SI_ARM | /* XXX ? */ |
| 2439 | NISTC_AI_CMD1_DIV_ARM | |
| 2440 | NISTC_AI_CMD1_SC_ARM, |
| 2441 | NISTC_AI_CMD1_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2442 | break; |
| 2443 | } |
| 2444 | |
| 2445 | #ifdef PCIDMA |
| 2446 | { |
| 2447 | int retval = ni_ai_setup_MITE_dma(dev); |
H Hartley Sweeten | f740197 | 2014-07-16 11:02:08 -0700 | [diff] [blame] | 2448 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2449 | if (retval) |
| 2450 | return retval; |
| 2451 | } |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2452 | #endif |
| 2453 | |
H Hartley Sweeten | ebb657b | 2014-04-17 10:08:11 -0700 | [diff] [blame] | 2454 | if (cmd->start_src == TRIG_NOW) { |
H Hartley Sweeten | a1da35a | 2015-05-01 14:58:56 -0700 | [diff] [blame] | 2455 | ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | |
| 2456 | devpriv->ai_cmd2, |
| 2457 | NISTC_AI_CMD2_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2458 | s->async->inttrig = NULL; |
H Hartley Sweeten | ebb657b | 2014-04-17 10:08:11 -0700 | [diff] [blame] | 2459 | } else if (cmd->start_src == TRIG_EXT) { |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2460 | s->async->inttrig = NULL; |
H Hartley Sweeten | ebb657b | 2014-04-17 10:08:11 -0700 | [diff] [blame] | 2461 | } else { /* TRIG_INT */ |
| 2462 | s->async->inttrig = ni_ai_inttrig; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2463 | } |
| 2464 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2465 | return 0; |
| 2466 | } |
| 2467 | |
H Hartley Sweeten | d2a577c | 2014-05-28 16:26:39 -0700 | [diff] [blame] | 2468 | static int ni_ai_insn_config(struct comedi_device *dev, |
| 2469 | struct comedi_subdevice *s, |
| 2470 | struct comedi_insn *insn, unsigned int *data) |
| 2471 | { |
H Hartley Sweeten | d2a577c | 2014-05-28 16:26:39 -0700 | [diff] [blame] | 2472 | struct ni_private *devpriv = dev->private; |
| 2473 | |
| 2474 | if (insn->n < 1) |
| 2475 | return -EINVAL; |
| 2476 | |
| 2477 | switch (data[0]) { |
H Hartley Sweeten | d2a577c | 2014-05-28 16:26:39 -0700 | [diff] [blame] | 2478 | case INSN_CONFIG_ALT_SOURCE: |
H Hartley Sweeten | 1773321 | 2014-06-19 10:20:32 -0700 | [diff] [blame] | 2479 | if (devpriv->is_m_series) { |
H Hartley Sweeten | 41f9f0b | 2015-05-01 14:58:39 -0700 | [diff] [blame] | 2480 | if (data[1] & ~NI_M_CFG_BYPASS_AI_CAL_MASK) |
H Hartley Sweeten | d2a577c | 2014-05-28 16:26:39 -0700 | [diff] [blame] | 2481 | return -EINVAL; |
H Hartley Sweeten | d2a577c | 2014-05-28 16:26:39 -0700 | [diff] [blame] | 2482 | devpriv->ai_calib_source = data[1]; |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 2483 | } else if (devpriv->is_6143) { |
H Hartley Sweeten | d2a577c | 2014-05-28 16:26:39 -0700 | [diff] [blame] | 2484 | unsigned int calib_source; |
| 2485 | |
| 2486 | calib_source = data[1] & 0xf; |
| 2487 | |
H Hartley Sweeten | d2a577c | 2014-05-28 16:26:39 -0700 | [diff] [blame] | 2488 | devpriv->ai_calib_source = calib_source; |
H Hartley Sweeten | ee3e21a | 2015-05-01 15:00:08 -0700 | [diff] [blame] | 2489 | ni_writew(dev, calib_source, NI6143_CALIB_CHAN_REG); |
H Hartley Sweeten | d2a577c | 2014-05-28 16:26:39 -0700 | [diff] [blame] | 2490 | } else { |
| 2491 | unsigned int calib_source; |
| 2492 | unsigned int calib_source_adjust; |
| 2493 | |
| 2494 | calib_source = data[1] & 0xf; |
| 2495 | calib_source_adjust = (data[1] >> 4) & 0xff; |
| 2496 | |
| 2497 | if (calib_source >= 8) |
| 2498 | return -EINVAL; |
| 2499 | devpriv->ai_calib_source = calib_source; |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 2500 | if (devpriv->is_611x) { |
H Hartley Sweeten | 5a92cac | 2014-06-19 10:20:35 -0700 | [diff] [blame] | 2501 | ni_writeb(dev, calib_source_adjust, |
H Hartley Sweeten | 0418da5 | 2015-05-01 15:00:07 -0700 | [diff] [blame] | 2502 | NI611X_CAL_GAIN_SEL_REG); |
H Hartley Sweeten | d2a577c | 2014-05-28 16:26:39 -0700 | [diff] [blame] | 2503 | } |
| 2504 | } |
| 2505 | return 2; |
| 2506 | default: |
| 2507 | break; |
| 2508 | } |
| 2509 | |
| 2510 | return -EINVAL; |
| 2511 | } |
| 2512 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 2513 | static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s, |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 2514 | void *data, unsigned int num_bytes, |
| 2515 | unsigned int chan_index) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2516 | { |
H Hartley Sweeten | a10817d | 2014-07-14 12:23:45 -0700 | [diff] [blame] | 2517 | struct comedi_cmd *cmd = &s->async->cmd; |
H Hartley Sweeten | c39e050 | 2014-10-31 12:04:28 -0700 | [diff] [blame] | 2518 | unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes); |
H Hartley Sweeten | 9663ab1 | 2014-05-27 10:31:00 -0700 | [diff] [blame] | 2519 | unsigned short *array = data; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2520 | unsigned int i; |
Ksenija Stanojevic | 212efdb | 2015-10-31 06:34:29 -0700 | [diff] [blame] | 2521 | #ifdef PCIDMA |
| 2522 | __le16 buf, *barray = data; |
| 2523 | #endif |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2524 | |
H Hartley Sweeten | c39e050 | 2014-10-31 12:04:28 -0700 | [diff] [blame] | 2525 | for (i = 0; i < nsamples; i++) { |
H Hartley Sweeten | a10817d | 2014-07-14 12:23:45 -0700 | [diff] [blame] | 2526 | unsigned int range = CR_RANGE(cmd->chanlist[chan_index]); |
| 2527 | unsigned short val = array[i]; |
H Hartley Sweeten | fed3c23 | 2014-07-14 12:23:40 -0700 | [diff] [blame] | 2528 | |
H Hartley Sweeten | a10817d | 2014-07-14 12:23:45 -0700 | [diff] [blame] | 2529 | /* |
| 2530 | * Munge data from unsigned to two's complement for |
| 2531 | * bipolar ranges. |
| 2532 | */ |
H Hartley Sweeten | fed3c23 | 2014-07-14 12:23:40 -0700 | [diff] [blame] | 2533 | if (comedi_range_is_bipolar(s, range)) |
H Hartley Sweeten | a10817d | 2014-07-14 12:23:45 -0700 | [diff] [blame] | 2534 | val = comedi_offset_munge(s, val); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2535 | #ifdef PCIDMA |
Ksenija Stanojevic | 212efdb | 2015-10-31 06:34:29 -0700 | [diff] [blame] | 2536 | buf = cpu_to_le16(val); |
| 2537 | barray[i] = buf; |
| 2538 | #else |
H Hartley Sweeten | a10817d | 2014-07-14 12:23:45 -0700 | [diff] [blame] | 2539 | array[i] = val; |
Ksenija Stanojevic | 212efdb | 2015-10-31 06:34:29 -0700 | [diff] [blame] | 2540 | #endif |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2541 | chan_index++; |
H Hartley Sweeten | 9663ab1 | 2014-05-27 10:31:00 -0700 | [diff] [blame] | 2542 | chan_index %= cmd->chanlist_len; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2543 | } |
| 2544 | } |
| 2545 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 2546 | static int ni_m_series_ao_config_chanlist(struct comedi_device *dev, |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 2547 | struct comedi_subdevice *s, |
| 2548 | unsigned int chanspec[], |
| 2549 | unsigned int n_chans, int timed) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2550 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 2551 | struct ni_private *devpriv = dev->private; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2552 | unsigned int range; |
| 2553 | unsigned int chan; |
| 2554 | unsigned int conf; |
| 2555 | int i; |
| 2556 | int invert = 0; |
| 2557 | |
Bill Pemberton | 53106ae | 2009-04-09 16:07:21 -0400 | [diff] [blame] | 2558 | if (timed) { |
H Hartley Sweeten | 4727736 | 2014-07-14 12:23:47 -0700 | [diff] [blame] | 2559 | for (i = 0; i < s->n_chan; ++i) { |
H Hartley Sweeten | bae4530 | 2015-05-01 14:58:40 -0700 | [diff] [blame] | 2560 | devpriv->ao_conf[i] &= ~NI_M_AO_CFG_BANK_UPDATE_TIMED; |
H Hartley Sweeten | 5a92cac | 2014-06-19 10:20:35 -0700 | [diff] [blame] | 2561 | ni_writeb(dev, devpriv->ao_conf[i], |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 2562 | NI_M_AO_CFG_BANK_REG(i)); |
| 2563 | ni_writeb(dev, 0xf, NI_M_AO_WAVEFORM_ORDER_REG(i)); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2564 | } |
| 2565 | } |
| 2566 | for (i = 0; i < n_chans; i++) { |
Bill Pemberton | 1f6325d | 2009-03-16 22:06:31 -0400 | [diff] [blame] | 2567 | const struct comedi_krange *krange; |
H Hartley Sweeten | f740197 | 2014-07-16 11:02:08 -0700 | [diff] [blame] | 2568 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2569 | chan = CR_CHAN(chanspec[i]); |
| 2570 | range = CR_RANGE(chanspec[i]); |
| 2571 | krange = s->range_table->range + range; |
| 2572 | invert = 0; |
| 2573 | conf = 0; |
| 2574 | switch (krange->max - krange->min) { |
| 2575 | case 20000000: |
H Hartley Sweeten | bae4530 | 2015-05-01 14:58:40 -0700 | [diff] [blame] | 2576 | conf |= NI_M_AO_CFG_BANK_REF_INT_10V; |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 2577 | ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan)); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2578 | break; |
| 2579 | case 10000000: |
H Hartley Sweeten | bae4530 | 2015-05-01 14:58:40 -0700 | [diff] [blame] | 2580 | conf |= NI_M_AO_CFG_BANK_REF_INT_5V; |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 2581 | ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan)); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2582 | break; |
| 2583 | case 4000000: |
H Hartley Sweeten | bae4530 | 2015-05-01 14:58:40 -0700 | [diff] [blame] | 2584 | conf |= NI_M_AO_CFG_BANK_REF_INT_10V; |
H Hartley Sweeten | b06afa1 | 2015-05-01 14:58:41 -0700 | [diff] [blame] | 2585 | ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5, |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 2586 | NI_M_AO_REF_ATTENUATION_REG(chan)); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2587 | break; |
| 2588 | case 2000000: |
H Hartley Sweeten | bae4530 | 2015-05-01 14:58:40 -0700 | [diff] [blame] | 2589 | conf |= NI_M_AO_CFG_BANK_REF_INT_5V; |
H Hartley Sweeten | b06afa1 | 2015-05-01 14:58:41 -0700 | [diff] [blame] | 2590 | ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5, |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 2591 | NI_M_AO_REF_ATTENUATION_REG(chan)); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2592 | break; |
| 2593 | default: |
H Hartley Sweeten | 89c4695e | 2014-07-18 13:29:52 -0700 | [diff] [blame] | 2594 | dev_err(dev->class_dev, |
Haneen Mohammed | cd25503 | 2015-03-05 13:01:49 +0300 | [diff] [blame] | 2595 | "bug! unhandled ao reference voltage\n"); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2596 | break; |
| 2597 | } |
| 2598 | switch (krange->max + krange->min) { |
| 2599 | case 0: |
H Hartley Sweeten | bae4530 | 2015-05-01 14:58:40 -0700 | [diff] [blame] | 2600 | conf |= NI_M_AO_CFG_BANK_OFFSET_0V; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2601 | break; |
| 2602 | case 10000000: |
H Hartley Sweeten | bae4530 | 2015-05-01 14:58:40 -0700 | [diff] [blame] | 2603 | conf |= NI_M_AO_CFG_BANK_OFFSET_5V; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2604 | break; |
| 2605 | default: |
H Hartley Sweeten | 89c4695e | 2014-07-18 13:29:52 -0700 | [diff] [blame] | 2606 | dev_err(dev->class_dev, |
Haneen Mohammed | cd25503 | 2015-03-05 13:01:49 +0300 | [diff] [blame] | 2607 | "bug! unhandled ao offset voltage\n"); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2608 | break; |
| 2609 | } |
| 2610 | if (timed) |
H Hartley Sweeten | bae4530 | 2015-05-01 14:58:40 -0700 | [diff] [blame] | 2611 | conf |= NI_M_AO_CFG_BANK_UPDATE_TIMED; |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 2612 | ni_writeb(dev, conf, NI_M_AO_CFG_BANK_REG(chan)); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2613 | devpriv->ao_conf[chan] = conf; |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 2614 | ni_writeb(dev, i, NI_M_AO_WAVEFORM_ORDER_REG(chan)); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2615 | } |
| 2616 | return invert; |
| 2617 | } |
| 2618 | |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 2619 | static int ni_old_ao_config_chanlist(struct comedi_device *dev, |
| 2620 | struct comedi_subdevice *s, |
| 2621 | unsigned int chanspec[], |
| 2622 | unsigned int n_chans) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2623 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 2624 | struct ni_private *devpriv = dev->private; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2625 | unsigned int range; |
| 2626 | unsigned int chan; |
| 2627 | unsigned int conf; |
| 2628 | int i; |
| 2629 | int invert = 0; |
| 2630 | |
| 2631 | for (i = 0; i < n_chans; i++) { |
| 2632 | chan = CR_CHAN(chanspec[i]); |
| 2633 | range = CR_RANGE(chanspec[i]); |
H Hartley Sweeten | b497b8d | 2015-05-01 14:59:59 -0700 | [diff] [blame] | 2634 | conf = NI_E_AO_DACSEL(chan); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2635 | |
H Hartley Sweeten | fed3c23 | 2014-07-14 12:23:40 -0700 | [diff] [blame] | 2636 | if (comedi_range_is_bipolar(s, range)) { |
H Hartley Sweeten | b497b8d | 2015-05-01 14:59:59 -0700 | [diff] [blame] | 2637 | conf |= NI_E_AO_CFG_BIP; |
H Hartley Sweeten | 4727736 | 2014-07-14 12:23:47 -0700 | [diff] [blame] | 2638 | invert = (s->maxdata + 1) >> 1; |
H Hartley Sweeten | fed3c23 | 2014-07-14 12:23:40 -0700 | [diff] [blame] | 2639 | } else { |
| 2640 | invert = 0; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2641 | } |
H Hartley Sweeten | fed3c23 | 2014-07-14 12:23:40 -0700 | [diff] [blame] | 2642 | if (comedi_range_is_external(s, range)) |
H Hartley Sweeten | b497b8d | 2015-05-01 14:59:59 -0700 | [diff] [blame] | 2643 | conf |= NI_E_AO_EXT_REF; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2644 | |
| 2645 | /* not all boards can deglitch, but this shouldn't hurt */ |
| 2646 | if (chanspec[i] & CR_DEGLITCH) |
H Hartley Sweeten | b497b8d | 2015-05-01 14:59:59 -0700 | [diff] [blame] | 2647 | conf |= NI_E_AO_DEGLITCH; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2648 | |
| 2649 | /* analog reference */ |
| 2650 | /* AREF_OTHER connects AO ground to AI ground, i think */ |
H Hartley Sweeten | b497b8d | 2015-05-01 14:59:59 -0700 | [diff] [blame] | 2651 | if (CR_AREF(chanspec[i]) == AREF_OTHER) |
| 2652 | conf |= NI_E_AO_GROUND_REF; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2653 | |
H Hartley Sweeten | b497b8d | 2015-05-01 14:59:59 -0700 | [diff] [blame] | 2654 | ni_writew(dev, conf, NI_E_AO_CFG_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2655 | devpriv->ao_conf[chan] = conf; |
| 2656 | } |
| 2657 | return invert; |
| 2658 | } |
| 2659 | |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 2660 | static int ni_ao_config_chanlist(struct comedi_device *dev, |
| 2661 | struct comedi_subdevice *s, |
| 2662 | unsigned int chanspec[], unsigned int n_chans, |
| 2663 | int timed) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2664 | { |
H Hartley Sweeten | 1773321 | 2014-06-19 10:20:32 -0700 | [diff] [blame] | 2665 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | 6293e35 | 2013-03-05 10:20:41 -0700 | [diff] [blame] | 2666 | |
H Hartley Sweeten | 1773321 | 2014-06-19 10:20:32 -0700 | [diff] [blame] | 2667 | if (devpriv->is_m_series) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2668 | return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans, |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 2669 | timed); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2670 | else |
| 2671 | return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans); |
| 2672 | } |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 2673 | |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 2674 | static int ni_ao_insn_write(struct comedi_device *dev, |
| 2675 | struct comedi_subdevice *s, |
H Hartley Sweeten | bfb0c28 | 2014-07-14 12:23:43 -0700 | [diff] [blame] | 2676 | struct comedi_insn *insn, |
| 2677 | unsigned int *data) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2678 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 2679 | struct ni_private *devpriv = dev->private; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2680 | unsigned int chan = CR_CHAN(insn->chanspec); |
H Hartley Sweeten | bfb0c28 | 2014-07-14 12:23:43 -0700 | [diff] [blame] | 2681 | unsigned int range = CR_RANGE(insn->chanspec); |
| 2682 | int reg; |
| 2683 | int i; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2684 | |
H Hartley Sweeten | 79816da1 | 2014-07-14 12:23:48 -0700 | [diff] [blame] | 2685 | if (devpriv->is_6xxx) { |
H Hartley Sweeten | ef39154 | 2015-05-01 15:00:11 -0700 | [diff] [blame] | 2686 | ni_ao_win_outw(dev, 1 << chan, NI671X_AO_IMMEDIATE_REG); |
H Hartley Sweeten | 79816da1 | 2014-07-14 12:23:48 -0700 | [diff] [blame] | 2687 | |
H Hartley Sweeten | ef39154 | 2015-05-01 15:00:11 -0700 | [diff] [blame] | 2688 | reg = NI671X_DAC_DIRECT_DATA_REG(chan); |
H Hartley Sweeten | 79816da1 | 2014-07-14 12:23:48 -0700 | [diff] [blame] | 2689 | } else if (devpriv->is_m_series) { |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 2690 | reg = NI_M_DAC_DIRECT_DATA_REG(chan); |
H Hartley Sweeten | 79816da1 | 2014-07-14 12:23:48 -0700 | [diff] [blame] | 2691 | } else { |
H Hartley Sweeten | 25e941a | 2015-05-01 15:00:01 -0700 | [diff] [blame] | 2692 | reg = NI_E_DAC_DIRECT_DATA_REG(chan); |
H Hartley Sweeten | 79816da1 | 2014-07-14 12:23:48 -0700 | [diff] [blame] | 2693 | } |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2694 | |
H Hartley Sweeten | bfb0c28 | 2014-07-14 12:23:43 -0700 | [diff] [blame] | 2695 | ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2696 | |
H Hartley Sweeten | bfb0c28 | 2014-07-14 12:23:43 -0700 | [diff] [blame] | 2697 | for (i = 0; i < insn->n; i++) { |
| 2698 | unsigned int val = data[i]; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2699 | |
H Hartley Sweeten | b6d977e | 2014-08-25 16:04:15 -0700 | [diff] [blame] | 2700 | s->readback[chan] = val; |
H Hartley Sweeten | bfb0c28 | 2014-07-14 12:23:43 -0700 | [diff] [blame] | 2701 | |
H Hartley Sweeten | 79816da1 | 2014-07-14 12:23:48 -0700 | [diff] [blame] | 2702 | if (devpriv->is_6xxx) { |
| 2703 | /* |
| 2704 | * 6xxx boards have bipolar outputs, munge the |
| 2705 | * unsigned comedi values to 2's complement |
| 2706 | */ |
| 2707 | val = comedi_offset_munge(s, val); |
| 2708 | |
| 2709 | ni_ao_win_outw(dev, val, reg); |
| 2710 | } else if (devpriv->is_m_series) { |
| 2711 | /* |
| 2712 | * M-series boards use offset binary values for |
| 2713 | * bipolar and uinpolar outputs |
| 2714 | */ |
H Hartley Sweeten | bfb0c28 | 2014-07-14 12:23:43 -0700 | [diff] [blame] | 2715 | ni_writew(dev, val, reg); |
| 2716 | } else { |
| 2717 | /* |
| 2718 | * Non-M series boards need two's complement values |
| 2719 | * for bipolar ranges. |
| 2720 | */ |
| 2721 | if (comedi_range_is_bipolar(s, range)) |
| 2722 | val = comedi_offset_munge(s, val); |
| 2723 | |
| 2724 | ni_writew(dev, val, reg); |
| 2725 | } |
| 2726 | } |
| 2727 | |
| 2728 | return insn->n; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2729 | } |
| 2730 | |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 2731 | static int ni_ao_insn_config(struct comedi_device *dev, |
| 2732 | struct comedi_subdevice *s, |
| 2733 | struct comedi_insn *insn, unsigned int *data) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2734 | { |
Ian Abbott | 7cf94ad | 2014-09-09 11:26:44 +0100 | [diff] [blame] | 2735 | const struct ni_board_struct *board = dev->board_ptr; |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 2736 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | 836b571 | 2014-10-31 12:04:29 -0700 | [diff] [blame] | 2737 | unsigned int nbytes; |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 2738 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2739 | switch (data[0]) { |
| 2740 | case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE: |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 2741 | switch (data[1]) { |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2742 | case COMEDI_OUTPUT: |
H Hartley Sweeten | 836b571 | 2014-10-31 12:04:29 -0700 | [diff] [blame] | 2743 | nbytes = comedi_samples_to_bytes(s, |
| 2744 | board->ao_fifo_depth); |
| 2745 | data[2] = 1 + nbytes; |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 2746 | if (devpriv->mite) |
| 2747 | data[2] += devpriv->mite->fifo_size; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2748 | break; |
| 2749 | case COMEDI_INPUT: |
| 2750 | data[2] = 0; |
| 2751 | break; |
| 2752 | default: |
| 2753 | return -EINVAL; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2754 | } |
| 2755 | return 0; |
| 2756 | default: |
| 2757 | break; |
| 2758 | } |
| 2759 | |
| 2760 | return -EINVAL; |
| 2761 | } |
| 2762 | |
H Hartley Sweeten | ebb657b | 2014-04-17 10:08:11 -0700 | [diff] [blame] | 2763 | static int ni_ao_inttrig(struct comedi_device *dev, |
| 2764 | struct comedi_subdevice *s, |
| 2765 | unsigned int trig_num) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2766 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 2767 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | ebb657b | 2014-04-17 10:08:11 -0700 | [diff] [blame] | 2768 | struct comedi_cmd *cmd = &s->async->cmd; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2769 | int ret; |
| 2770 | int interrupt_b_bits; |
| 2771 | int i; |
| 2772 | static const int timeout = 1000; |
| 2773 | |
Ian Abbott | f0f4b0cc3a | 2016-07-19 12:17:39 +0100 | [diff] [blame] | 2774 | /* |
| 2775 | * Require trig_num == cmd->start_arg when cmd->start_src == TRIG_INT. |
| 2776 | * For backwards compatibility, also allow trig_num == 0 when |
| 2777 | * cmd->start_src != TRIG_INT (i.e. when cmd->start_src == TRIG_EXT); |
| 2778 | * in that case, the internal trigger is being used as a pre-trigger |
| 2779 | * before the external trigger. |
| 2780 | */ |
| 2781 | if (!(trig_num == cmd->start_arg || |
| 2782 | (trig_num == 0 && cmd->start_src != TRIG_INT))) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2783 | return -EINVAL; |
| 2784 | |
H Hartley Sweeten | bd474a0 | 2016-04-14 09:57:55 -0700 | [diff] [blame] | 2785 | /* |
| 2786 | * Null trig at beginning prevent ao start trigger from executing more |
| 2787 | * than once per command (and doing things like trying to allocate the |
| 2788 | * ao dma channel multiple times). |
| 2789 | */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2790 | s->async->inttrig = NULL; |
| 2791 | |
H Hartley Sweeten | 4c9c1d2 | 2015-05-01 14:59:28 -0700 | [diff] [blame] | 2792 | ni_set_bits(dev, NISTC_INTB_ENA_REG, |
| 2793 | NISTC_INTB_ENA_AO_FIFO | NISTC_INTB_ENA_AO_ERR, 0); |
| 2794 | interrupt_b_bits = NISTC_INTB_ENA_AO_ERR; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2795 | #ifdef PCIDMA |
H Hartley Sweeten | 8102f3d | 2015-05-01 14:59:34 -0700 | [diff] [blame] | 2796 | ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG); |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 2797 | if (devpriv->is_6xxx) |
H Hartley Sweeten | ef39154 | 2015-05-01 15:00:11 -0700 | [diff] [blame] | 2798 | ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2799 | ret = ni_ao_setup_MITE_dma(dev); |
| 2800 | if (ret) |
| 2801 | return ret; |
| 2802 | ret = ni_ao_wait_for_dma_load(dev); |
| 2803 | if (ret < 0) |
| 2804 | return ret; |
| 2805 | #else |
| 2806 | ret = ni_ao_prep_fifo(dev, s); |
| 2807 | if (ret == 0) |
| 2808 | return -EPIPE; |
| 2809 | |
H Hartley Sweeten | 4c9c1d2 | 2015-05-01 14:59:28 -0700 | [diff] [blame] | 2810 | interrupt_b_bits |= NISTC_INTB_ENA_AO_FIFO; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2811 | #endif |
| 2812 | |
H Hartley Sweeten | 72bca4f | 2015-05-01 14:59:24 -0700 | [diff] [blame] | 2813 | ni_stc_writew(dev, devpriv->ao_mode3 | NISTC_AO_MODE3_NOT_AN_UPDATE, |
| 2814 | NISTC_AO_MODE3_REG); |
| 2815 | ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2816 | /* wait for DACs to be loaded */ |
| 2817 | for (i = 0; i < timeout; i++) { |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 2818 | udelay(1); |
H Hartley Sweeten | bab382e | 2015-05-01 14:59:48 -0700 | [diff] [blame] | 2819 | if ((ni_stc_readw(dev, NISTC_STATUS2_REG) & |
| 2820 | NISTC_STATUS2_AO_TMRDACWRS_IN_PROGRESS) == 0) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2821 | break; |
| 2822 | } |
| 2823 | if (i == timeout) { |
H Hartley Sweeten | 5ac1d82 | 2014-07-17 11:57:33 -0700 | [diff] [blame] | 2824 | dev_err(dev->class_dev, |
| 2825 | "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear\n"); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2826 | return -EIO; |
| 2827 | } |
H Hartley Sweeten | 00b14b1 | 2014-06-19 10:20:34 -0700 | [diff] [blame] | 2828 | /* |
| 2829 | * stc manual says we are need to clear error interrupt after |
| 2830 | * AO_TMRDACWRs_In_Progress_St clears |
| 2831 | */ |
H Hartley Sweeten | 4a6de832 | 2015-05-01 14:58:55 -0700 | [diff] [blame] | 2832 | ni_stc_writew(dev, NISTC_INTB_ACK_AO_ERR, NISTC_INTB_ACK_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2833 | |
H Hartley Sweeten | 4c9c1d2 | 2015-05-01 14:59:28 -0700 | [diff] [blame] | 2834 | ni_set_bits(dev, NISTC_INTB_ENA_REG, interrupt_b_bits, 1); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2835 | |
H Hartley Sweeten | 7bfcc2d | 2015-05-01 14:59:00 -0700 | [diff] [blame] | 2836 | ni_stc_writew(dev, NISTC_AO_CMD1_UI_ARM | |
| 2837 | NISTC_AO_CMD1_UC_ARM | |
| 2838 | NISTC_AO_CMD1_BC_ARM | |
H Hartley Sweeten | 7bfcc2d | 2015-05-01 14:59:00 -0700 | [diff] [blame] | 2839 | devpriv->ao_cmd1, |
| 2840 | NISTC_AO_CMD1_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2841 | |
H Hartley Sweeten | 382b3c4 | 2015-05-01 14:58:57 -0700 | [diff] [blame] | 2842 | ni_stc_writew(dev, NISTC_AO_CMD2_START1_PULSE | devpriv->ao_cmd2, |
| 2843 | NISTC_AO_CMD2_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2844 | |
| 2845 | return 0; |
| 2846 | } |
| 2847 | |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 2848 | /* |
| 2849 | * begin ni_ao_cmd. |
| 2850 | * Organized similar to NI-STC and MHDDK examples. |
| 2851 | * ni_ao_cmd is broken out into configuration sub-routines for clarity. |
| 2852 | */ |
| 2853 | |
| 2854 | static void ni_ao_cmd_personalize(struct comedi_device *dev, |
| 2855 | const struct comedi_cmd *cmd) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2856 | { |
Ian Abbott | 7cf94ad | 2014-09-09 11:26:44 +0100 | [diff] [blame] | 2857 | const struct ni_board_struct *board = dev->board_ptr; |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 2858 | unsigned int bits; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2859 | |
H Hartley Sweeten | 707502f | 2015-05-01 14:59:25 -0700 | [diff] [blame] | 2860 | ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2861 | |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 2862 | bits = |
| 2863 | /* fast CPU interface--only eseries */ |
| 2864 | /* ((slow CPU interface) ? 0 : AO_Fast_CPU) | */ |
| 2865 | NISTC_AO_PERSONAL_BC_SRC_SEL | |
| 2866 | 0 /* (use_original_pulse ? 0 : NISTC_AO_PERSONAL_UPDATE_TIMEBASE) */ | |
| 2867 | /* |
| 2868 | * FIXME: start setting following bit when appropriate. Need to |
| 2869 | * determine whether board is E4 or E1. |
| 2870 | * FROM MHHDK: |
| 2871 | * if board is E4 or E1 |
| 2872 | * Set bit "NISTC_AO_PERSONAL_UPDATE_PW" to 0 |
| 2873 | * else |
| 2874 | * set it to 1 |
| 2875 | */ |
| 2876 | NISTC_AO_PERSONAL_UPDATE_PW | |
| 2877 | /* FIXME: when should we set following bit to zero? */ |
| 2878 | NISTC_AO_PERSONAL_TMRDACWR_PW | |
| 2879 | (board->ao_fifo_depth ? |
| 2880 | NISTC_AO_PERSONAL_FIFO_ENA : NISTC_AO_PERSONAL_DMA_PIO_CTRL) |
| 2881 | ; |
| 2882 | #if 0 |
| 2883 | /* |
| 2884 | * FIXME: |
| 2885 | * add something like ".has_individual_dacs = 0" to ni_board_struct |
| 2886 | * since, as F Hess pointed out, not all in m series have singles. not |
| 2887 | * sure if e-series all have duals... |
| 2888 | */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2889 | |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 2890 | /* |
| 2891 | * F Hess: windows driver does not set NISTC_AO_PERSONAL_NUM_DAC bit for |
| 2892 | * 6281, verified with bus analyzer. |
| 2893 | */ |
| 2894 | if (devpriv->is_m_series) |
| 2895 | bits |= NISTC_AO_PERSONAL_NUM_DAC; |
| 2896 | #endif |
| 2897 | ni_stc_writew(dev, bits, NISTC_AO_PERSONAL_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2898 | |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 2899 | ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG); |
| 2900 | } |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2901 | |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 2902 | static void ni_ao_cmd_set_trigger(struct comedi_device *dev, |
| 2903 | const struct comedi_cmd *cmd) |
| 2904 | { |
| 2905 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | 55f9e7d | 2016-04-14 09:58:00 -0700 | [diff] [blame] | 2906 | unsigned int trigsel; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2907 | |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 2908 | ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2909 | |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 2910 | /* sync */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2911 | if (cmd->stop_src == TRIG_NONE) { |
H Hartley Sweeten | 4e5ce0a | 2015-05-01 14:59:07 -0700 | [diff] [blame] | 2912 | devpriv->ao_mode1 |= NISTC_AO_MODE1_CONTINUOUS; |
| 2913 | devpriv->ao_mode1 &= ~NISTC_AO_MODE1_TRIGGER_ONCE; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2914 | } else { |
H Hartley Sweeten | 4e5ce0a | 2015-05-01 14:59:07 -0700 | [diff] [blame] | 2915 | devpriv->ao_mode1 &= ~NISTC_AO_MODE1_CONTINUOUS; |
| 2916 | devpriv->ao_mode1 |= NISTC_AO_MODE1_TRIGGER_ONCE; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2917 | } |
H Hartley Sweeten | 4e5ce0a | 2015-05-01 14:59:07 -0700 | [diff] [blame] | 2918 | ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG); |
H Hartley Sweeten | f21844d | 2015-05-01 14:59:22 -0700 | [diff] [blame] | 2919 | |
H Hartley Sweeten | 55f9e7d | 2016-04-14 09:58:00 -0700 | [diff] [blame] | 2920 | if (cmd->start_src == TRIG_INT) { |
| 2921 | trigsel = NISTC_AO_TRIG_START1_EDGE | |
| 2922 | NISTC_AO_TRIG_START1_SYNC; |
| 2923 | } else { /* TRIG_EXT */ |
| 2924 | trigsel = NISTC_AO_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) + 1); |
| 2925 | /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */ |
| 2926 | if (cmd->start_arg & CR_INVERT) |
| 2927 | trigsel |= NISTC_AO_TRIG_START1_POLARITY; |
| 2928 | /* 0=edge detection disabled, 1=enabled */ |
| 2929 | if (cmd->start_arg & CR_EDGE) |
| 2930 | trigsel |= NISTC_AO_TRIG_START1_EDGE; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2931 | } |
H Hartley Sweeten | 55f9e7d | 2016-04-14 09:58:00 -0700 | [diff] [blame] | 2932 | ni_stc_writew(dev, trigsel, NISTC_AO_TRIG_SEL_REG); |
| 2933 | |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 2934 | /* AO_Delayed_START1 = 0, we do not support delayed start...yet */ |
H Hartley Sweeten | f21844d | 2015-05-01 14:59:22 -0700 | [diff] [blame] | 2935 | |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 2936 | /* sync */ |
| 2937 | /* select DA_START1 as PFI6/AO_START1 when configured as an output */ |
H Hartley Sweeten | 72bca4f | 2015-05-01 14:59:24 -0700 | [diff] [blame] | 2938 | devpriv->ao_mode3 &= ~NISTC_AO_MODE3_TRIG_LEN; |
| 2939 | ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 2940 | |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 2941 | ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG); |
| 2942 | } |
| 2943 | |
| 2944 | static void ni_ao_cmd_set_counters(struct comedi_device *dev, |
| 2945 | const struct comedi_cmd *cmd) |
| 2946 | { |
| 2947 | struct ni_private *devpriv = dev->private; |
| 2948 | /* Not supporting 'waveform staging' or 'local buffer with pauses' */ |
| 2949 | |
| 2950 | ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG); |
| 2951 | /* |
| 2952 | * This relies on ao_mode1/(Trigger_Once | Continuous) being set in |
| 2953 | * set_trigger above. It is unclear whether we really need to re-write |
| 2954 | * this register with these values. The mhddk examples for e-series |
| 2955 | * show writing this in both places, but the examples for m-series show |
| 2956 | * a single write in the set_counters function (here). |
| 2957 | */ |
H Hartley Sweeten | 4e5ce0a | 2015-05-01 14:59:07 -0700 | [diff] [blame] | 2958 | ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG); |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 2959 | |
| 2960 | /* sync (upload number of buffer iterations -1) */ |
| 2961 | /* indicate that we want to use BC_Load_A_Register as the source */ |
H Hartley Sweeten | ec8bf72 | 2015-05-01 14:59:08 -0700 | [diff] [blame] | 2962 | devpriv->ao_mode2 &= ~NISTC_AO_MODE2_BC_INIT_LOAD_SRC; |
| 2963 | ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG); |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 2964 | |
| 2965 | /* |
| 2966 | * if the BC_TC interrupt is still issued in spite of UC, BC, UI |
| 2967 | * ignoring BC_TC, then we will need to find a way to ignore that |
| 2968 | * interrupt in continuous mode. |
| 2969 | */ |
| 2970 | ni_stc_writel(dev, 0, NISTC_AO_BC_LOADA_REG); /* iter once */ |
| 2971 | |
| 2972 | /* sync (issue command to load number of buffer iterations -1) */ |
H Hartley Sweeten | 7bfcc2d | 2015-05-01 14:59:00 -0700 | [diff] [blame] | 2973 | ni_stc_writew(dev, NISTC_AO_CMD1_BC_LOAD, NISTC_AO_CMD1_REG); |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 2974 | |
| 2975 | /* sync (upload number of updates in buffer) */ |
| 2976 | /* indicate that we want to use UC_Load_A_Register as the source */ |
H Hartley Sweeten | ec8bf72 | 2015-05-01 14:59:08 -0700 | [diff] [blame] | 2977 | devpriv->ao_mode2 &= ~NISTC_AO_MODE2_UC_INIT_LOAD_SRC; |
| 2978 | ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG); |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 2979 | |
Spencer E. Olson | 6aab7fe | 2016-01-27 14:28:28 -0700 | [diff] [blame] | 2980 | /* |
| 2981 | * if a user specifies '0', this automatically assumes the entire 24bit |
| 2982 | * address space is available for the (multiple iterations of single |
| 2983 | * buffer) MISB. Otherwise, stop_arg specifies the MISB length that |
| 2984 | * will be used, regardless of whether we are in continuous mode or not. |
| 2985 | * In continuous mode, the output will just iterate indefinitely over |
| 2986 | * the MISB. |
| 2987 | */ |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 2988 | { |
Spencer E. Olson | 6aab7fe | 2016-01-27 14:28:28 -0700 | [diff] [blame] | 2989 | unsigned int stop_arg = cmd->stop_arg > 0 ? |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 2990 | (cmd->stop_arg & 0xffffff) : 0xffffff; |
| 2991 | |
H Hartley Sweeten | 1773321 | 2014-06-19 10:20:32 -0700 | [diff] [blame] | 2992 | if (devpriv->is_m_series) { |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 2993 | /* |
| 2994 | * this is how the NI example code does it for m-series |
| 2995 | * boards, verified correct with 6259 |
| 2996 | */ |
| 2997 | ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG); |
| 2998 | |
| 2999 | /* sync (issue cmd to load number of updates in MISB) */ |
H Hartley Sweeten | 7bfcc2d | 2015-05-01 14:59:00 -0700 | [diff] [blame] | 3000 | ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD, |
| 3001 | NISTC_AO_CMD1_REG); |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 3002 | } else { |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 3003 | ni_stc_writel(dev, stop_arg, NISTC_AO_UC_LOADA_REG); |
| 3004 | |
| 3005 | /* sync (issue cmd to load number of updates in MISB) */ |
H Hartley Sweeten | 7bfcc2d | 2015-05-01 14:59:00 -0700 | [diff] [blame] | 3006 | ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD, |
| 3007 | NISTC_AO_CMD1_REG); |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 3008 | |
| 3009 | /* |
| 3010 | * sync (upload number of updates-1 in MISB) |
| 3011 | * --eseries only? |
| 3012 | */ |
| 3013 | ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3014 | } |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3015 | } |
| 3016 | |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 3017 | ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG); |
| 3018 | } |
| 3019 | |
| 3020 | static void ni_ao_cmd_set_update(struct comedi_device *dev, |
| 3021 | const struct comedi_cmd *cmd) |
| 3022 | { |
| 3023 | struct ni_private *devpriv = dev->private; |
| 3024 | |
| 3025 | ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG); |
| 3026 | |
| 3027 | /* |
| 3028 | * zero out these bit fields to be set below. Does an ao-reset do this |
| 3029 | * automatically? |
| 3030 | */ |
| 3031 | devpriv->ao_mode1 &= ~( |
| 3032 | NISTC_AO_MODE1_UI_SRC_MASK | |
| 3033 | NISTC_AO_MODE1_UI_SRC_POLARITY | |
| 3034 | NISTC_AO_MODE1_UPDATE_SRC_MASK | |
| 3035 | NISTC_AO_MODE1_UPDATE_SRC_POLARITY |
| 3036 | ); |
| 3037 | |
H Hartley Sweeten | 1392dcc | 2016-04-14 09:58:01 -0700 | [diff] [blame] | 3038 | if (cmd->scan_begin_src == TRIG_TIMER) { |
| 3039 | unsigned int trigvar; |
| 3040 | |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 3041 | devpriv->ao_cmd2 &= ~NISTC_AO_CMD2_BC_GATE_ENA; |
| 3042 | |
| 3043 | /* |
| 3044 | * NOTE: there are several other ways of configuring internal |
| 3045 | * updates, but we'll only support one for now: using |
| 3046 | * AO_IN_TIMEBASE, w/o waveform staging, w/o a delay between |
| 3047 | * START1 and first update, and also w/o local buffer mode w/ |
| 3048 | * pauses. |
| 3049 | */ |
| 3050 | |
| 3051 | /* |
| 3052 | * This is already done above: |
| 3053 | * devpriv->ao_mode1 &= ~( |
| 3054 | * // set UPDATE_Source to UI_TC: |
| 3055 | * NISTC_AO_MODE1_UPDATE_SRC_MASK | |
| 3056 | * // set UPDATE_Source_Polarity to rising (required?) |
| 3057 | * NISTC_AO_MODE1_UPDATE_SRC_POLARITY | |
| 3058 | * // set UI_Source to AO_IN_TIMEBASE1: |
| 3059 | * NISTC_AO_MODE1_UI_SRC_MASK | |
| 3060 | * // set UI_Source_Polarity to rising (required?) |
| 3061 | * NISTC_AO_MODE1_UI_SRC_POLARITY |
| 3062 | * ); |
| 3063 | */ |
| 3064 | |
| 3065 | /* |
| 3066 | * TODO: use ao_ui_clock_source to allow all possible signals |
| 3067 | * to be routed to UI_Source_Select. See tSTC.h for |
| 3068 | * eseries/ni67xx and tMSeries.h for mseries. |
| 3069 | */ |
| 3070 | |
H Hartley Sweeten | 1392dcc | 2016-04-14 09:58:01 -0700 | [diff] [blame] | 3071 | trigvar = ni_ns_to_timer(dev, cmd->scan_begin_arg, |
| 3072 | CMDF_ROUND_NEAREST); |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 3073 | |
H Hartley Sweeten | 1392dcc | 2016-04-14 09:58:01 -0700 | [diff] [blame] | 3074 | /* |
| 3075 | * Wait N TB3 ticks after the start trigger before |
| 3076 | * clocking (N must be >=2). |
| 3077 | */ |
| 3078 | /* following line: 2-1 per STC */ |
| 3079 | ni_stc_writel(dev, 1, NISTC_AO_UI_LOADA_REG); |
| 3080 | ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD, NISTC_AO_CMD1_REG); |
Ian Abbott | 2bc5240 | 2017-06-30 12:02:18 +0100 | [diff] [blame] | 3081 | ni_stc_writel(dev, trigvar, NISTC_AO_UI_LOADA_REG); |
H Hartley Sweeten | 1392dcc | 2016-04-14 09:58:01 -0700 | [diff] [blame] | 3082 | } else { /* TRIG_EXT */ |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 3083 | /* FIXME: assert scan_begin_arg != 0, ret failure otherwise */ |
| 3084 | devpriv->ao_cmd2 |= NISTC_AO_CMD2_BC_GATE_ENA; |
| 3085 | devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC( |
| 3086 | CR_CHAN(cmd->scan_begin_arg)); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3087 | if (cmd->scan_begin_arg & CR_INVERT) |
H Hartley Sweeten | 4e5ce0a | 2015-05-01 14:59:07 -0700 | [diff] [blame] | 3088 | devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3089 | } |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 3090 | |
H Hartley Sweeten | 382b3c4 | 2015-05-01 14:58:57 -0700 | [diff] [blame] | 3091 | ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG); |
H Hartley Sweeten | 4e5ce0a | 2015-05-01 14:59:07 -0700 | [diff] [blame] | 3092 | ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG); |
H Hartley Sweeten | ec8bf72 | 2015-05-01 14:59:08 -0700 | [diff] [blame] | 3093 | devpriv->ao_mode2 &= ~(NISTC_AO_MODE2_UI_RELOAD_MODE(3) | |
| 3094 | NISTC_AO_MODE2_UI_INIT_LOAD_SRC); |
| 3095 | ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3096 | |
Spencer E. Olson | d2a6c32 | 2016-01-27 14:28:26 -0700 | [diff] [blame] | 3097 | /* Configure DAQ-STC for Timed update mode */ |
| 3098 | devpriv->ao_cmd1 |= NISTC_AO_CMD1_DAC1_UPDATE_MODE | |
| 3099 | NISTC_AO_CMD1_DAC0_UPDATE_MODE; |
| 3100 | /* We are not using UPDATE2-->don't have to set DACx_Source_Select */ |
| 3101 | ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3102 | |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 3103 | ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG); |
| 3104 | } |
| 3105 | |
| 3106 | static void ni_ao_cmd_set_channels(struct comedi_device *dev, |
| 3107 | struct comedi_subdevice *s) |
| 3108 | { |
| 3109 | struct ni_private *devpriv = dev->private; |
| 3110 | const struct comedi_cmd *cmd = &s->async->cmd; |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 3111 | unsigned int bits = 0; |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 3112 | |
| 3113 | ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG); |
| 3114 | |
| 3115 | if (devpriv->is_6xxx) { |
| 3116 | unsigned int i; |
| 3117 | |
| 3118 | bits = 0; |
| 3119 | for (i = 0; i < cmd->chanlist_len; ++i) { |
| 3120 | int chan = CR_CHAN(cmd->chanlist[i]); |
| 3121 | |
| 3122 | bits |= 1 << chan; |
| 3123 | ni_ao_win_outw(dev, chan, NI611X_AO_WAVEFORM_GEN_REG); |
| 3124 | } |
| 3125 | ni_ao_win_outw(dev, bits, NI611X_AO_TIMED_REG); |
| 3126 | } |
| 3127 | |
| 3128 | ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1); |
| 3129 | |
| 3130 | if (cmd->scan_end_arg > 1) { |
| 3131 | devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN; |
| 3132 | bits = NISTC_AO_OUT_CTRL_CHANS(cmd->scan_end_arg - 1) |
| 3133 | | NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ; |
| 3134 | |
| 3135 | } else { |
| 3136 | devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN; |
| 3137 | bits = NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ; |
| 3138 | if (devpriv->is_m_series | devpriv->is_6xxx) |
| 3139 | bits |= NISTC_AO_OUT_CTRL_CHANS(0); |
| 3140 | else |
| 3141 | bits |= NISTC_AO_OUT_CTRL_CHANS( |
| 3142 | CR_CHAN(cmd->chanlist[0])); |
| 3143 | } |
| 3144 | |
| 3145 | ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG); |
| 3146 | ni_stc_writew(dev, bits, NISTC_AO_OUT_CTRL_REG); |
| 3147 | |
| 3148 | ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG); |
| 3149 | } |
| 3150 | |
| 3151 | static void ni_ao_cmd_set_stop_conditions(struct comedi_device *dev, |
| 3152 | const struct comedi_cmd *cmd) |
| 3153 | { |
| 3154 | struct ni_private *devpriv = dev->private; |
| 3155 | |
| 3156 | ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG); |
| 3157 | |
H Hartley Sweeten | 72bca4f | 2015-05-01 14:59:24 -0700 | [diff] [blame] | 3158 | devpriv->ao_mode3 |= NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR; |
| 3159 | ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3160 | |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 3161 | /* |
| 3162 | * Since we are not supporting waveform staging, we ignore these errors: |
| 3163 | * NISTC_AO_MODE3_STOP_ON_BC_TC_ERR, |
| 3164 | * NISTC_AO_MODE3_STOP_ON_BC_TC_TRIG_ERR |
| 3165 | */ |
| 3166 | |
| 3167 | ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG); |
| 3168 | } |
| 3169 | |
| 3170 | static void ni_ao_cmd_set_fifo_mode(struct comedi_device *dev) |
| 3171 | { |
| 3172 | struct ni_private *devpriv = dev->private; |
| 3173 | |
| 3174 | ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG); |
| 3175 | |
H Hartley Sweeten | ec8bf72 | 2015-05-01 14:59:08 -0700 | [diff] [blame] | 3176 | devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_MODE_MASK; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3177 | #ifdef PCIDMA |
H Hartley Sweeten | ec8bf72 | 2015-05-01 14:59:08 -0700 | [diff] [blame] | 3178 | devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF_F; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3179 | #else |
H Hartley Sweeten | ec8bf72 | 2015-05-01 14:59:08 -0700 | [diff] [blame] | 3180 | devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3181 | #endif |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 3182 | /* NOTE: this is where use_onboard_memory=True would be implemented */ |
H Hartley Sweeten | ec8bf72 | 2015-05-01 14:59:08 -0700 | [diff] [blame] | 3183 | devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_REXMIT_ENA; |
| 3184 | ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3185 | |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 3186 | /* enable sending of ao fifo requests (dma request) */ |
H Hartley Sweeten | 2b6285da | 2015-05-01 14:59:21 -0700 | [diff] [blame] | 3187 | ni_stc_writew(dev, NISTC_AO_START_AOFREQ_ENA, NISTC_AO_START_SEL_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3188 | |
H Hartley Sweeten | 707502f | 2015-05-01 14:59:25 -0700 | [diff] [blame] | 3189 | ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3190 | |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 3191 | /* we are not supporting boards with virtual fifos */ |
| 3192 | } |
| 3193 | |
| 3194 | static void ni_ao_cmd_set_interrupts(struct comedi_device *dev, |
| 3195 | struct comedi_subdevice *s) |
| 3196 | { |
| 3197 | if (s->async->cmd.stop_src == TRIG_COUNT) |
H Hartley Sweeten | 4c9c1d2 | 2015-05-01 14:59:28 -0700 | [diff] [blame] | 3198 | ni_set_bits(dev, NISTC_INTB_ENA_REG, |
| 3199 | NISTC_INTB_ENA_AO_BC_TC, 1); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3200 | |
H Hartley Sweeten | ebb657b | 2014-04-17 10:08:11 -0700 | [diff] [blame] | 3201 | s->async->inttrig = ni_ao_inttrig; |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 3202 | } |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3203 | |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 3204 | static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s) |
| 3205 | { |
| 3206 | struct ni_private *devpriv = dev->private; |
| 3207 | const struct comedi_cmd *cmd = &s->async->cmd; |
| 3208 | |
| 3209 | if (dev->irq == 0) { |
| 3210 | dev_err(dev->class_dev, "cannot run command without an irq"); |
| 3211 | return -EIO; |
| 3212 | } |
| 3213 | |
| 3214 | /* ni_ao_reset should have already been done */ |
| 3215 | ni_ao_cmd_personalize(dev, cmd); |
| 3216 | /* clearing fifo and preload happens elsewhere */ |
| 3217 | |
| 3218 | ni_ao_cmd_set_trigger(dev, cmd); |
| 3219 | ni_ao_cmd_set_counters(dev, cmd); |
| 3220 | ni_ao_cmd_set_update(dev, cmd); |
| 3221 | ni_ao_cmd_set_channels(dev, s); |
| 3222 | ni_ao_cmd_set_stop_conditions(dev, cmd); |
| 3223 | ni_ao_cmd_set_fifo_mode(dev); |
Spencer E. Olson | 6aab7fe | 2016-01-27 14:28:28 -0700 | [diff] [blame] | 3224 | ni_cmd_set_mite_transfer(devpriv->ao_mite_ring, s, cmd, 0x00ffffff); |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 3225 | ni_ao_cmd_set_interrupts(dev, s); |
| 3226 | |
| 3227 | /* |
| 3228 | * arm(ing) and star(ting) happen in ni_ao_inttrig, which _must_ be |
| 3229 | * called for ao commands since 1) TRIG_NOW is not supported and 2) DMA |
| 3230 | * must be setup and initially written to before arm/start happen. |
| 3231 | */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3232 | return 0; |
| 3233 | } |
| 3234 | |
Spencer E. Olson | 080e679 | 2016-01-27 14:28:27 -0700 | [diff] [blame] | 3235 | /* end ni_ao_cmd */ |
| 3236 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 3237 | static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 3238 | struct comedi_cmd *cmd) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3239 | { |
Ian Abbott | 7cf94ad | 2014-09-09 11:26:44 +0100 | [diff] [blame] | 3240 | const struct ni_board_struct *board = dev->board_ptr; |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 3241 | struct ni_private *devpriv = dev->private; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3242 | int err = 0; |
H Hartley Sweeten | ebb657b | 2014-04-17 10:08:11 -0700 | [diff] [blame] | 3243 | unsigned int tmp; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3244 | |
H Hartley Sweeten | 27020ff | 2012-09-26 14:11:10 -0700 | [diff] [blame] | 3245 | /* Step 1 : check if triggers are trivially valid */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3246 | |
Ian Abbott | 311fd9b | 2015-03-27 19:14:24 +0000 | [diff] [blame] | 3247 | err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT); |
| 3248 | err |= comedi_check_trigger_src(&cmd->scan_begin_src, |
H Hartley Sweeten | 27020ff | 2012-09-26 14:11:10 -0700 | [diff] [blame] | 3249 | TRIG_TIMER | TRIG_EXT); |
Ian Abbott | 311fd9b | 2015-03-27 19:14:24 +0000 | [diff] [blame] | 3250 | err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW); |
| 3251 | err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); |
| 3252 | err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3253 | |
| 3254 | if (err) |
| 3255 | return 1; |
| 3256 | |
H Hartley Sweeten | 27020ff | 2012-09-26 14:11:10 -0700 | [diff] [blame] | 3257 | /* Step 2a : make sure trigger sources are unique */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3258 | |
Ian Abbott | 311fd9b | 2015-03-27 19:14:24 +0000 | [diff] [blame] | 3259 | err |= comedi_check_trigger_is_unique(cmd->start_src); |
| 3260 | err |= comedi_check_trigger_is_unique(cmd->scan_begin_src); |
| 3261 | err |= comedi_check_trigger_is_unique(cmd->stop_src); |
H Hartley Sweeten | 27020ff | 2012-09-26 14:11:10 -0700 | [diff] [blame] | 3262 | |
| 3263 | /* Step 2b : and mutually compatible */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3264 | |
| 3265 | if (err) |
| 3266 | return 2; |
| 3267 | |
H Hartley Sweeten | c3be5c7 | 2012-11-13 18:00:36 -0700 | [diff] [blame] | 3268 | /* Step 3: check if arguments are trivially valid */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3269 | |
H Hartley Sweeten | ebb657b | 2014-04-17 10:08:11 -0700 | [diff] [blame] | 3270 | switch (cmd->start_src) { |
| 3271 | case TRIG_INT: |
Ian Abbott | 311fd9b | 2015-03-27 19:14:24 +0000 | [diff] [blame] | 3272 | err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0); |
H Hartley Sweeten | ebb657b | 2014-04-17 10:08:11 -0700 | [diff] [blame] | 3273 | break; |
| 3274 | case TRIG_EXT: |
| 3275 | tmp = CR_CHAN(cmd->start_arg); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3276 | |
| 3277 | if (tmp > 18) |
| 3278 | tmp = 18; |
| 3279 | tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE)); |
Ian Abbott | 311fd9b | 2015-03-27 19:14:24 +0000 | [diff] [blame] | 3280 | err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp); |
H Hartley Sweeten | ebb657b | 2014-04-17 10:08:11 -0700 | [diff] [blame] | 3281 | break; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3282 | } |
H Hartley Sweeten | c3be5c7 | 2012-11-13 18:00:36 -0700 | [diff] [blame] | 3283 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3284 | if (cmd->scan_begin_src == TRIG_TIMER) { |
Ian Abbott | 311fd9b | 2015-03-27 19:14:24 +0000 | [diff] [blame] | 3285 | err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg, |
| 3286 | board->ao_speed); |
| 3287 | err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, |
| 3288 | devpriv->clock_ns * |
| 3289 | 0xffffff); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3290 | } |
H Hartley Sweeten | c3be5c7 | 2012-11-13 18:00:36 -0700 | [diff] [blame] | 3291 | |
Ian Abbott | 311fd9b | 2015-03-27 19:14:24 +0000 | [diff] [blame] | 3292 | err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0); |
| 3293 | err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg, |
| 3294 | cmd->chanlist_len); |
Spencer E. Olson | 6aab7fe | 2016-01-27 14:28:28 -0700 | [diff] [blame] | 3295 | err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3296 | |
| 3297 | if (err) |
| 3298 | return 3; |
| 3299 | |
| 3300 | /* step 4: fix up any arguments */ |
| 3301 | if (cmd->scan_begin_src == TRIG_TIMER) { |
| 3302 | tmp = cmd->scan_begin_arg; |
| 3303 | cmd->scan_begin_arg = |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 3304 | ni_timer_to_ns(dev, ni_ns_to_timer(dev, |
| 3305 | cmd->scan_begin_arg, |
H Hartley Sweeten | a207c12 | 2014-07-18 17:01:16 -0700 | [diff] [blame] | 3306 | cmd->flags)); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3307 | if (tmp != cmd->scan_begin_arg) |
| 3308 | err++; |
| 3309 | } |
| 3310 | if (err) |
| 3311 | return 4; |
| 3312 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3313 | return 0; |
| 3314 | } |
| 3315 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 3316 | static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3317 | { |
Spencer E. Olson | 5c93736c | 2016-01-27 14:28:25 -0700 | [diff] [blame] | 3318 | /* See 3.6.1.2 "Resetting", of DAQ-STC Technical Reference Manual */ |
| 3319 | |
| 3320 | /* |
| 3321 | * In the following, the "--sync" comments are meant to denote |
| 3322 | * asynchronous boundaries for setting the registers as described in the |
| 3323 | * DAQ-STC mostly in the order also described in the DAQ-STC. |
| 3324 | */ |
| 3325 | |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 3326 | struct ni_private *devpriv = dev->private; |
| 3327 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3328 | ni_release_ao_mite_channel(dev); |
| 3329 | |
Spencer E. Olson | 5c93736c | 2016-01-27 14:28:25 -0700 | [diff] [blame] | 3330 | /* --sync (reset AO) */ |
| 3331 | if (devpriv->is_m_series) |
| 3332 | /* following example in mhddk for m-series */ |
| 3333 | ni_stc_writew(dev, NISTC_RESET_AO, NISTC_RESET_REG); |
| 3334 | |
| 3335 | /*--sync (start config) */ |
H Hartley Sweeten | 707502f | 2015-05-01 14:59:25 -0700 | [diff] [blame] | 3336 | ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG); |
Spencer E. Olson | 5c93736c | 2016-01-27 14:28:25 -0700 | [diff] [blame] | 3337 | |
| 3338 | /*--sync (Disarm) */ |
H Hartley Sweeten | 7bfcc2d | 2015-05-01 14:59:00 -0700 | [diff] [blame] | 3339 | ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG); |
Spencer E. Olson | 5c93736c | 2016-01-27 14:28:25 -0700 | [diff] [blame] | 3340 | |
| 3341 | /* |
| 3342 | * --sync |
| 3343 | * (clear bunch of registers--mseries mhddk examples do not include |
| 3344 | * this) |
| 3345 | */ |
| 3346 | devpriv->ao_cmd1 = 0; |
| 3347 | devpriv->ao_cmd2 = 0; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3348 | devpriv->ao_mode1 = 0; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3349 | devpriv->ao_mode2 = 0; |
H Hartley Sweeten | 1773321 | 2014-06-19 10:20:32 -0700 | [diff] [blame] | 3350 | if (devpriv->is_m_series) |
H Hartley Sweeten | 72bca4f | 2015-05-01 14:59:24 -0700 | [diff] [blame] | 3351 | devpriv->ao_mode3 = NISTC_AO_MODE3_LAST_GATE_DISABLE; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3352 | else |
| 3353 | devpriv->ao_mode3 = 0; |
H Hartley Sweeten | f740197 | 2014-07-16 11:02:08 -0700 | [diff] [blame] | 3354 | |
Spencer E. Olson | 5c93736c | 2016-01-27 14:28:25 -0700 | [diff] [blame] | 3355 | ni_stc_writew(dev, 0, NISTC_AO_PERSONAL_REG); |
| 3356 | ni_stc_writew(dev, 0, NISTC_AO_CMD1_REG); |
| 3357 | ni_stc_writew(dev, 0, NISTC_AO_CMD2_REG); |
| 3358 | ni_stc_writew(dev, 0, NISTC_AO_MODE1_REG); |
| 3359 | ni_stc_writew(dev, 0, NISTC_AO_MODE2_REG); |
| 3360 | ni_stc_writew(dev, 0, NISTC_AO_OUT_CTRL_REG); |
| 3361 | ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG); |
| 3362 | ni_stc_writew(dev, 0, NISTC_AO_START_SEL_REG); |
| 3363 | ni_stc_writew(dev, 0, NISTC_AO_TRIG_SEL_REG); |
| 3364 | |
| 3365 | /*--sync (disable interrupts) */ |
| 3366 | ni_set_bits(dev, NISTC_INTB_ENA_REG, ~0, 0); |
| 3367 | |
| 3368 | /*--sync (ack) */ |
| 3369 | ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL, NISTC_AO_PERSONAL_REG); |
| 3370 | ni_stc_writew(dev, NISTC_INTB_ACK_AO_ALL, NISTC_INTB_ACK_REG); |
| 3371 | |
| 3372 | /*--not in DAQ-STC. which doc? */ |
| 3373 | if (devpriv->is_6xxx) { |
| 3374 | ni_ao_win_outw(dev, (1u << s->n_chan) - 1u, |
| 3375 | NI671X_AO_IMMEDIATE_REG); |
H Hartley Sweeten | ef39154 | 2015-05-01 15:00:11 -0700 | [diff] [blame] | 3376 | ni_ao_win_outw(dev, NI611X_AO_MISC_CLEAR_WG, |
| 3377 | NI611X_AO_MISC_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3378 | } |
H Hartley Sweeten | 707502f | 2015-05-01 14:59:25 -0700 | [diff] [blame] | 3379 | ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG); |
Spencer E. Olson | 5c93736c | 2016-01-27 14:28:25 -0700 | [diff] [blame] | 3380 | /*--end */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3381 | |
| 3382 | return 0; |
| 3383 | } |
| 3384 | |
Bill Pemberton | 2696fb5 | 2009-03-27 11:29:34 -0400 | [diff] [blame] | 3385 | /* digital io */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3386 | |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 3387 | static int ni_dio_insn_config(struct comedi_device *dev, |
| 3388 | struct comedi_subdevice *s, |
H Hartley Sweeten | ddf62f2 | 2013-08-06 09:32:33 -0700 | [diff] [blame] | 3389 | struct comedi_insn *insn, |
| 3390 | unsigned int *data) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3391 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 3392 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | ddf62f2 | 2013-08-06 09:32:33 -0700 | [diff] [blame] | 3393 | int ret; |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 3394 | |
H Hartley Sweeten | ddf62f2 | 2013-08-06 09:32:33 -0700 | [diff] [blame] | 3395 | ret = comedi_dio_insn_config(dev, s, insn, data, 0); |
| 3396 | if (ret) |
| 3397 | return ret; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3398 | |
H Hartley Sweeten | 59a97c3 | 2015-05-01 14:59:02 -0700 | [diff] [blame] | 3399 | devpriv->dio_control &= ~NISTC_DIO_CTRL_DIR_MASK; |
| 3400 | devpriv->dio_control |= NISTC_DIO_CTRL_DIR(s->io_bits); |
| 3401 | ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3402 | |
H Hartley Sweeten | ddf62f2 | 2013-08-06 09:32:33 -0700 | [diff] [blame] | 3403 | return insn->n; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3404 | } |
| 3405 | |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 3406 | static int ni_dio_insn_bits(struct comedi_device *dev, |
| 3407 | struct comedi_subdevice *s, |
H Hartley Sweeten | 6171667 | 2013-08-30 11:06:38 -0700 | [diff] [blame] | 3408 | struct comedi_insn *insn, |
| 3409 | unsigned int *data) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3410 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 3411 | struct ni_private *devpriv = dev->private; |
| 3412 | |
H Hartley Sweeten | 6171667 | 2013-08-30 11:06:38 -0700 | [diff] [blame] | 3413 | /* Make sure we're not using the serial part of the dio */ |
H Hartley Sweeten | 05aafee | 2015-05-01 14:59:01 -0700 | [diff] [blame] | 3414 | if ((data[0] & (NISTC_DIO_SDIN | NISTC_DIO_SDOUT)) && |
| 3415 | devpriv->serial_interval_ns) |
H Hartley Sweeten | 6171667 | 2013-08-30 11:06:38 -0700 | [diff] [blame] | 3416 | return -EBUSY; |
H Hartley Sweeten | 5207066 | 2012-06-18 11:18:25 -0700 | [diff] [blame] | 3417 | |
H Hartley Sweeten | 6171667 | 2013-08-30 11:06:38 -0700 | [diff] [blame] | 3418 | if (comedi_dio_update_state(s, data)) { |
H Hartley Sweeten | 05aafee | 2015-05-01 14:59:01 -0700 | [diff] [blame] | 3419 | devpriv->dio_output &= ~NISTC_DIO_OUT_PARALLEL_MASK; |
| 3420 | devpriv->dio_output |= NISTC_DIO_OUT_PARALLEL(s->state); |
| 3421 | ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3422 | } |
H Hartley Sweeten | 6171667 | 2013-08-30 11:06:38 -0700 | [diff] [blame] | 3423 | |
H Hartley Sweeten | 6f764a4 | 2015-05-01 14:59:42 -0700 | [diff] [blame] | 3424 | data[1] = ni_stc_readw(dev, NISTC_DIO_IN_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3425 | |
H Hartley Sweeten | a2714e3 | 2012-06-18 13:16:35 -0700 | [diff] [blame] | 3426 | return insn->n; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3427 | } |
| 3428 | |
H Hartley Sweeten | cf122bb | 2016-04-14 09:57:52 -0700 | [diff] [blame] | 3429 | #ifdef PCIDMA |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 3430 | static int ni_m_series_dio_insn_config(struct comedi_device *dev, |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 3431 | struct comedi_subdevice *s, |
| 3432 | struct comedi_insn *insn, |
| 3433 | unsigned int *data) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3434 | { |
H Hartley Sweeten | ddf62f2 | 2013-08-06 09:32:33 -0700 | [diff] [blame] | 3435 | int ret; |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 3436 | |
H Hartley Sweeten | ddf62f2 | 2013-08-06 09:32:33 -0700 | [diff] [blame] | 3437 | ret = comedi_dio_insn_config(dev, s, insn, data, 0); |
| 3438 | if (ret) |
| 3439 | return ret; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3440 | |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 3441 | ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3442 | |
H Hartley Sweeten | ddf62f2 | 2013-08-06 09:32:33 -0700 | [diff] [blame] | 3443 | return insn->n; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3444 | } |
| 3445 | |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 3446 | static int ni_m_series_dio_insn_bits(struct comedi_device *dev, |
| 3447 | struct comedi_subdevice *s, |
| 3448 | struct comedi_insn *insn, |
| 3449 | unsigned int *data) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3450 | { |
H Hartley Sweeten | 6171667 | 2013-08-30 11:06:38 -0700 | [diff] [blame] | 3451 | if (comedi_dio_update_state(s, data)) |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 3452 | ni_writel(dev, s->state, NI_M_DIO_REG); |
H Hartley Sweeten | 6171667 | 2013-08-30 11:06:38 -0700 | [diff] [blame] | 3453 | |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 3454 | data[1] = ni_readl(dev, NI_M_DIO_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3455 | |
H Hartley Sweeten | a2714e3 | 2012-06-18 13:16:35 -0700 | [diff] [blame] | 3456 | return insn->n; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3457 | } |
| 3458 | |
H Hartley Sweeten | 368c2dc | 2014-04-16 14:19:19 -0700 | [diff] [blame] | 3459 | static int ni_cdio_check_chanlist(struct comedi_device *dev, |
| 3460 | struct comedi_subdevice *s, |
| 3461 | struct comedi_cmd *cmd) |
| 3462 | { |
| 3463 | int i; |
| 3464 | |
| 3465 | for (i = 0; i < cmd->chanlist_len; ++i) { |
| 3466 | unsigned int chan = CR_CHAN(cmd->chanlist[i]); |
| 3467 | |
| 3468 | if (chan != i) |
| 3469 | return -EINVAL; |
| 3470 | } |
| 3471 | |
| 3472 | return 0; |
| 3473 | } |
| 3474 | |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 3475 | static int ni_cdio_cmdtest(struct comedi_device *dev, |
| 3476 | struct comedi_subdevice *s, struct comedi_cmd *cmd) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3477 | { |
| 3478 | int err = 0; |
| 3479 | int tmp; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3480 | |
H Hartley Sweeten | 27020ff | 2012-09-26 14:11:10 -0700 | [diff] [blame] | 3481 | /* Step 1 : check if triggers are trivially valid */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3482 | |
Ian Abbott | 311fd9b | 2015-03-27 19:14:24 +0000 | [diff] [blame] | 3483 | err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT); |
| 3484 | err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT); |
| 3485 | err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW); |
| 3486 | err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); |
| 3487 | err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3488 | |
| 3489 | if (err) |
| 3490 | return 1; |
| 3491 | |
H Hartley Sweeten | 27020ff | 2012-09-26 14:11:10 -0700 | [diff] [blame] | 3492 | /* Step 2a : make sure trigger sources are unique */ |
| 3493 | /* Step 2b : and mutually compatible */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3494 | |
H Hartley Sweeten | c3be5c7 | 2012-11-13 18:00:36 -0700 | [diff] [blame] | 3495 | /* Step 3: check if arguments are trivially valid */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3496 | |
Ian Abbott | 311fd9b | 2015-03-27 19:14:24 +0000 | [diff] [blame] | 3497 | err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3498 | |
H Hartley Sweeten | c3be5c7 | 2012-11-13 18:00:36 -0700 | [diff] [blame] | 3499 | tmp = cmd->scan_begin_arg; |
H Hartley Sweeten | 258f004 | 2015-05-01 14:58:50 -0700 | [diff] [blame] | 3500 | tmp &= CR_PACK_FLAGS(NI_M_CDO_MODE_SAMPLE_SRC_MASK, 0, 0, CR_INVERT); |
H Hartley Sweeten | c3be5c7 | 2012-11-13 18:00:36 -0700 | [diff] [blame] | 3501 | if (tmp != cmd->scan_begin_arg) |
| 3502 | err |= -EINVAL; |
| 3503 | |
Ian Abbott | 311fd9b | 2015-03-27 19:14:24 +0000 | [diff] [blame] | 3504 | err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0); |
| 3505 | err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg, |
| 3506 | cmd->chanlist_len); |
Spencer E. Olson | f164cbf | 2016-01-27 14:28:29 -0700 | [diff] [blame] | 3507 | err |= comedi_check_trigger_arg_max(&cmd->stop_arg, |
| 3508 | s->async->prealloc_bufsz / |
| 3509 | comedi_bytes_per_scan(s)); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3510 | |
| 3511 | if (err) |
| 3512 | return 3; |
| 3513 | |
H Hartley Sweeten | b32381c | 2014-08-25 15:23:52 -0700 | [diff] [blame] | 3514 | /* Step 4: fix up any arguments */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3515 | |
H Hartley Sweeten | 368c2dc | 2014-04-16 14:19:19 -0700 | [diff] [blame] | 3516 | /* Step 5: check channel list if it exists */ |
H Hartley Sweeten | b32381c | 2014-08-25 15:23:52 -0700 | [diff] [blame] | 3517 | |
H Hartley Sweeten | 368c2dc | 2014-04-16 14:19:19 -0700 | [diff] [blame] | 3518 | if (cmd->chanlist && cmd->chanlist_len > 0) |
| 3519 | err |= ni_cdio_check_chanlist(dev, s, cmd); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3520 | |
| 3521 | if (err) |
| 3522 | return 5; |
| 3523 | |
| 3524 | return 0; |
| 3525 | } |
| 3526 | |
H Hartley Sweeten | ebb657b | 2014-04-17 10:08:11 -0700 | [diff] [blame] | 3527 | static int ni_cdo_inttrig(struct comedi_device *dev, |
| 3528 | struct comedi_subdevice *s, |
| 3529 | unsigned int trig_num) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3530 | { |
H Hartley Sweeten | ebb657b | 2014-04-17 10:08:11 -0700 | [diff] [blame] | 3531 | struct comedi_cmd *cmd = &s->async->cmd; |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 3532 | const unsigned int timeout = 1000; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3533 | int retval = 0; |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 3534 | unsigned int i; |
H Hartley Sweeten | 5a92cac | 2014-06-19 10:20:35 -0700 | [diff] [blame] | 3535 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | 9c340ac | 2014-05-29 10:56:32 -0700 | [diff] [blame] | 3536 | unsigned long flags; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3537 | |
H Hartley Sweeten | ebb657b | 2014-04-17 10:08:11 -0700 | [diff] [blame] | 3538 | if (trig_num != cmd->start_arg) |
| 3539 | return -EINVAL; |
| 3540 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3541 | s->async->inttrig = NULL; |
| 3542 | |
| 3543 | /* read alloc the entire buffer */ |
Ian Abbott | d13be55 | 2014-05-06 13:12:07 +0100 | [diff] [blame] | 3544 | comedi_buf_read_alloc(s, s->async->prealloc_bufsz); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3545 | |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 3546 | spin_lock_irqsave(&devpriv->mite_channel_lock, flags); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3547 | if (devpriv->cdo_mite_chan) { |
| 3548 | mite_prep_dma(devpriv->cdo_mite_chan, 32, 32); |
| 3549 | mite_dma_arm(devpriv->cdo_mite_chan); |
| 3550 | } else { |
H Hartley Sweeten | 5ac1d82 | 2014-07-17 11:57:33 -0700 | [diff] [blame] | 3551 | dev_err(dev->class_dev, "BUG: no cdo mite channel?\n"); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3552 | retval = -EIO; |
| 3553 | } |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 3554 | spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3555 | if (retval < 0) |
| 3556 | return retval; |
H Hartley Sweeten | cf122bb | 2016-04-14 09:57:52 -0700 | [diff] [blame] | 3557 | |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 3558 | /* |
| 3559 | * XXX not sure what interrupt C group does |
| 3560 | * wait for dma to fill output fifo |
H Hartley Sweeten | 60f078f | 2015-05-01 14:58:51 -0700 | [diff] [blame] | 3561 | * ni_writeb(dev, NI_M_INTC_ENA, NI_M_INTC_ENA_REG); |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 3562 | */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3563 | for (i = 0; i < timeout; ++i) { |
H Hartley Sweeten | d53be92 | 2015-05-01 14:58:46 -0700 | [diff] [blame] | 3564 | if (ni_readl(dev, NI_M_CDIO_STATUS_REG) & |
| 3565 | NI_M_CDIO_STATUS_CDO_FIFO_FULL) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3566 | break; |
H Hartley Sweeten | 8a5b817 | 2016-04-14 09:58:03 -0700 | [diff] [blame] | 3567 | usleep_range(10, 100); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3568 | } |
| 3569 | if (i == timeout) { |
H Hartley Sweeten | 5ac1d82 | 2014-07-17 11:57:33 -0700 | [diff] [blame] | 3570 | dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n"); |
H Hartley Sweeten | fed37a1 | 2014-05-28 16:26:35 -0700 | [diff] [blame] | 3571 | s->cancel(dev, s); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3572 | return -EIO; |
| 3573 | } |
H Hartley Sweeten | 3c3eb8e | 2015-05-01 14:58:47 -0700 | [diff] [blame] | 3574 | ni_writel(dev, NI_M_CDO_CMD_ARM | |
| 3575 | NI_M_CDO_CMD_ERR_INT_ENA_SET | |
| 3576 | NI_M_CDO_CMD_F_E_INT_ENA_SET, |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 3577 | NI_M_CDIO_CMD_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3578 | return retval; |
| 3579 | } |
| 3580 | |
H Hartley Sweeten | 0792928 | 2014-05-28 16:26:34 -0700 | [diff] [blame] | 3581 | static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s) |
| 3582 | { |
Spencer E. Olson | f164cbf | 2016-01-27 14:28:29 -0700 | [diff] [blame] | 3583 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | 0792928 | 2014-05-28 16:26:34 -0700 | [diff] [blame] | 3584 | const struct comedi_cmd *cmd = &s->async->cmd; |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 3585 | unsigned int cdo_mode_bits; |
H Hartley Sweeten | 0792928 | 2014-05-28 16:26:34 -0700 | [diff] [blame] | 3586 | int retval; |
| 3587 | |
H Hartley Sweeten | 3c3eb8e | 2015-05-01 14:58:47 -0700 | [diff] [blame] | 3588 | ni_writel(dev, NI_M_CDO_CMD_RESET, NI_M_CDIO_CMD_REG); |
H Hartley Sweeten | 258f004 | 2015-05-01 14:58:50 -0700 | [diff] [blame] | 3589 | cdo_mode_bits = NI_M_CDO_MODE_FIFO_MODE | |
| 3590 | NI_M_CDO_MODE_HALT_ON_ERROR | |
| 3591 | NI_M_CDO_MODE_SAMPLE_SRC(CR_CHAN(cmd->scan_begin_arg)); |
H Hartley Sweeten | 0792928 | 2014-05-28 16:26:34 -0700 | [diff] [blame] | 3592 | if (cmd->scan_begin_arg & CR_INVERT) |
H Hartley Sweeten | 258f004 | 2015-05-01 14:58:50 -0700 | [diff] [blame] | 3593 | cdo_mode_bits |= NI_M_CDO_MODE_POLARITY; |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 3594 | ni_writel(dev, cdo_mode_bits, NI_M_CDO_MODE_REG); |
H Hartley Sweeten | 0792928 | 2014-05-28 16:26:34 -0700 | [diff] [blame] | 3595 | if (s->io_bits) { |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 3596 | ni_writel(dev, s->state, NI_M_CDO_FIFO_DATA_REG); |
H Hartley Sweeten | 3c3eb8e | 2015-05-01 14:58:47 -0700 | [diff] [blame] | 3597 | ni_writel(dev, NI_M_CDO_CMD_SW_UPDATE, NI_M_CDIO_CMD_REG); |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 3598 | ni_writel(dev, s->io_bits, NI_M_CDO_MASK_ENA_REG); |
H Hartley Sweeten | 0792928 | 2014-05-28 16:26:34 -0700 | [diff] [blame] | 3599 | } else { |
H Hartley Sweeten | 5ac1d82 | 2014-07-17 11:57:33 -0700 | [diff] [blame] | 3600 | dev_err(dev->class_dev, |
| 3601 | "attempted to run digital output command with no lines configured as outputs\n"); |
H Hartley Sweeten | 0792928 | 2014-05-28 16:26:34 -0700 | [diff] [blame] | 3602 | return -EIO; |
| 3603 | } |
| 3604 | retval = ni_request_cdo_mite_channel(dev); |
| 3605 | if (retval < 0) |
| 3606 | return retval; |
| 3607 | |
Spencer E. Olson | f164cbf | 2016-01-27 14:28:29 -0700 | [diff] [blame] | 3608 | ni_cmd_set_mite_transfer(devpriv->cdo_mite_ring, s, cmd, |
| 3609 | s->async->prealloc_bufsz / |
| 3610 | comedi_bytes_per_scan(s)); |
| 3611 | |
H Hartley Sweeten | 0792928 | 2014-05-28 16:26:34 -0700 | [diff] [blame] | 3612 | s->async->inttrig = ni_cdo_inttrig; |
| 3613 | |
| 3614 | return 0; |
| 3615 | } |
| 3616 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 3617 | static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3618 | { |
H Hartley Sweeten | 3c3eb8e | 2015-05-01 14:58:47 -0700 | [diff] [blame] | 3619 | ni_writel(dev, NI_M_CDO_CMD_DISARM | |
| 3620 | NI_M_CDO_CMD_ERR_INT_ENA_CLR | |
| 3621 | NI_M_CDO_CMD_F_E_INT_ENA_CLR | |
| 3622 | NI_M_CDO_CMD_F_REQ_INT_ENA_CLR, |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 3623 | NI_M_CDIO_CMD_REG); |
| 3624 | /* |
| 3625 | * XXX not sure what interrupt C group does |
| 3626 | * ni_writeb(dev, 0, NI_M_INTC_ENA_REG); |
| 3627 | */ |
| 3628 | ni_writel(dev, 0, NI_M_CDO_MASK_ENA_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3629 | ni_release_cdo_mite_channel(dev); |
| 3630 | return 0; |
| 3631 | } |
| 3632 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 3633 | static void handle_cdio_interrupt(struct comedi_device *dev) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3634 | { |
H Hartley Sweeten | 9c340ac | 2014-05-29 10:56:32 -0700 | [diff] [blame] | 3635 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 3636 | unsigned int cdio_status; |
H Hartley Sweeten | f9cd92e | 2012-09-05 18:50:19 -0700 | [diff] [blame] | 3637 | struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV]; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3638 | unsigned long flags; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3639 | |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 3640 | spin_lock_irqsave(&devpriv->mite_channel_lock, flags); |
H Hartley Sweeten | f7d005c | 2016-04-21 12:04:44 -0700 | [diff] [blame] | 3641 | if (devpriv->cdo_mite_chan) |
| 3642 | mite_ack_linkc(devpriv->cdo_mite_chan, s, true); |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 3643 | spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3644 | |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 3645 | cdio_status = ni_readl(dev, NI_M_CDIO_STATUS_REG); |
H Hartley Sweeten | d53be92 | 2015-05-01 14:58:46 -0700 | [diff] [blame] | 3646 | if (cdio_status & NI_M_CDIO_STATUS_CDO_ERROR) { |
H Hartley Sweeten | 9c340ac | 2014-05-29 10:56:32 -0700 | [diff] [blame] | 3647 | /* XXX just guessing this is needed and does something useful */ |
H Hartley Sweeten | 3c3eb8e | 2015-05-01 14:58:47 -0700 | [diff] [blame] | 3648 | ni_writel(dev, NI_M_CDO_CMD_ERR_INT_CONFIRM, |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 3649 | NI_M_CDIO_CMD_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3650 | s->async->events |= COMEDI_CB_OVERFLOW; |
| 3651 | } |
H Hartley Sweeten | d53be92 | 2015-05-01 14:58:46 -0700 | [diff] [blame] | 3652 | if (cdio_status & NI_M_CDIO_STATUS_CDO_FIFO_EMPTY) { |
H Hartley Sweeten | 3c3eb8e | 2015-05-01 14:58:47 -0700 | [diff] [blame] | 3653 | ni_writel(dev, NI_M_CDO_CMD_F_E_INT_ENA_CLR, |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 3654 | NI_M_CDIO_CMD_REG); |
Chase Southwood | b9ede31 | 2014-01-10 22:02:57 -0600 | [diff] [blame] | 3655 | /* s->async->events |= COMEDI_CB_EOA; */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3656 | } |
H Hartley Sweeten | b9a69a1 | 2014-09-18 11:11:30 -0700 | [diff] [blame] | 3657 | comedi_handle_events(dev, s); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3658 | } |
H Hartley Sweeten | cf122bb | 2016-04-14 09:57:52 -0700 | [diff] [blame] | 3659 | #endif /* PCIDMA */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3660 | |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 3661 | static int ni_serial_hw_readwrite8(struct comedi_device *dev, |
| 3662 | struct comedi_subdevice *s, |
| 3663 | unsigned char data_out, |
| 3664 | unsigned char *data_in) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3665 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 3666 | struct ni_private *devpriv = dev->private; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3667 | unsigned int status1; |
| 3668 | int err = 0, count = 20; |
| 3669 | |
H Hartley Sweeten | 05aafee | 2015-05-01 14:59:01 -0700 | [diff] [blame] | 3670 | devpriv->dio_output &= ~NISTC_DIO_OUT_SERIAL_MASK; |
| 3671 | devpriv->dio_output |= NISTC_DIO_OUT_SERIAL(data_out); |
| 3672 | ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3673 | |
H Hartley Sweeten | d3fed08 | 2015-05-01 14:59:46 -0700 | [diff] [blame] | 3674 | status1 = ni_stc_readw(dev, NISTC_STATUS1_REG); |
| 3675 | if (status1 & NISTC_STATUS1_SERIO_IN_PROG) { |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3676 | err = -EBUSY; |
H Hartley Sweeten | b24a3ec | 2016-04-14 09:58:05 -0700 | [diff] [blame] | 3677 | goto error; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3678 | } |
| 3679 | |
H Hartley Sweeten | 59a97c3 | 2015-05-01 14:59:02 -0700 | [diff] [blame] | 3680 | devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_START; |
| 3681 | ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); |
| 3682 | devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_START; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3683 | |
| 3684 | /* Wait until STC says we're done, but don't loop infinitely. */ |
H Hartley Sweeten | d3fed08 | 2015-05-01 14:59:46 -0700 | [diff] [blame] | 3685 | while ((status1 = ni_stc_readw(dev, NISTC_STATUS1_REG)) & |
| 3686 | NISTC_STATUS1_SERIO_IN_PROG) { |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3687 | /* Delay one bit per loop */ |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 3688 | udelay((devpriv->serial_interval_ns + 999) / 1000); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3689 | if (--count < 0) { |
H Hartley Sweeten | 89c4695e | 2014-07-18 13:29:52 -0700 | [diff] [blame] | 3690 | dev_err(dev->class_dev, |
Haneen Mohammed | cd25503 | 2015-03-05 13:01:49 +0300 | [diff] [blame] | 3691 | "SPI serial I/O didn't finish in time!\n"); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3692 | err = -ETIME; |
H Hartley Sweeten | b24a3ec | 2016-04-14 09:58:05 -0700 | [diff] [blame] | 3693 | goto error; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3694 | } |
| 3695 | } |
| 3696 | |
H Hartley Sweeten | d3fed08 | 2015-05-01 14:59:46 -0700 | [diff] [blame] | 3697 | /* |
| 3698 | * Delay for last bit. This delay is absolutely necessary, because |
| 3699 | * NISTC_STATUS1_SERIO_IN_PROG goes high one bit too early. |
| 3700 | */ |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 3701 | udelay((devpriv->serial_interval_ns + 999) / 1000); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3702 | |
H Hartley Sweeten | c6be154 | 2015-03-04 12:15:40 -0700 | [diff] [blame] | 3703 | if (data_in) |
H Hartley Sweeten | 8fbb015 | 2015-05-01 14:59:47 -0700 | [diff] [blame] | 3704 | *data_in = ni_stc_readw(dev, NISTC_DIO_SERIAL_IN_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3705 | |
H Hartley Sweeten | b24a3ec | 2016-04-14 09:58:05 -0700 | [diff] [blame] | 3706 | error: |
H Hartley Sweeten | 59a97c3 | 2015-05-01 14:59:02 -0700 | [diff] [blame] | 3707 | ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3708 | |
| 3709 | return err; |
| 3710 | } |
| 3711 | |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 3712 | static int ni_serial_sw_readwrite8(struct comedi_device *dev, |
| 3713 | struct comedi_subdevice *s, |
| 3714 | unsigned char data_out, |
| 3715 | unsigned char *data_in) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3716 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 3717 | struct ni_private *devpriv = dev->private; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3718 | unsigned char mask, input = 0; |
| 3719 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3720 | /* Wait for one bit before transfer */ |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 3721 | udelay((devpriv->serial_interval_ns + 999) / 1000); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3722 | |
| 3723 | for (mask = 0x80; mask; mask >>= 1) { |
H Hartley Sweeten | bd474a0 | 2016-04-14 09:57:55 -0700 | [diff] [blame] | 3724 | /* |
| 3725 | * Output current bit; note that we cannot touch s->state |
| 3726 | * because it is a per-subdevice field, and serial is |
| 3727 | * a separate subdevice from DIO. |
| 3728 | */ |
H Hartley Sweeten | 05aafee | 2015-05-01 14:59:01 -0700 | [diff] [blame] | 3729 | devpriv->dio_output &= ~NISTC_DIO_SDOUT; |
Chase Southwood | bc46155 | 2014-01-10 22:02:33 -0600 | [diff] [blame] | 3730 | if (data_out & mask) |
H Hartley Sweeten | 05aafee | 2015-05-01 14:59:01 -0700 | [diff] [blame] | 3731 | devpriv->dio_output |= NISTC_DIO_SDOUT; |
| 3732 | ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3733 | |
H Hartley Sweeten | bd474a0 | 2016-04-14 09:57:55 -0700 | [diff] [blame] | 3734 | /* |
| 3735 | * Assert SDCLK (active low, inverted), wait for half of |
| 3736 | * the delay, deassert SDCLK, and wait for the other half. |
| 3737 | */ |
H Hartley Sweeten | 59a97c3 | 2015-05-01 14:59:02 -0700 | [diff] [blame] | 3738 | devpriv->dio_control |= NISTC_DIO_SDCLK; |
| 3739 | ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3740 | |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 3741 | udelay((devpriv->serial_interval_ns + 999) / 2000); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3742 | |
H Hartley Sweeten | 59a97c3 | 2015-05-01 14:59:02 -0700 | [diff] [blame] | 3743 | devpriv->dio_control &= ~NISTC_DIO_SDCLK; |
| 3744 | ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3745 | |
Greg Kroah-Hartman | 5f74ea1 | 2009-04-27 14:44:31 -0700 | [diff] [blame] | 3746 | udelay((devpriv->serial_interval_ns + 999) / 2000); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3747 | |
| 3748 | /* Input current bit */ |
H Hartley Sweeten | 6f764a4 | 2015-05-01 14:59:42 -0700 | [diff] [blame] | 3749 | if (ni_stc_readw(dev, NISTC_DIO_IN_REG) & NISTC_DIO_SDIN) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3750 | input |= mask; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3751 | } |
H Hartley Sweeten | 9d6a0f6 | 2013-11-26 10:21:32 -0700 | [diff] [blame] | 3752 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3753 | if (data_in) |
| 3754 | *data_in = input; |
| 3755 | |
| 3756 | return 0; |
| 3757 | } |
| 3758 | |
H Hartley Sweeten | 189e173 | 2014-05-28 16:26:36 -0700 | [diff] [blame] | 3759 | static int ni_serial_insn_config(struct comedi_device *dev, |
| 3760 | struct comedi_subdevice *s, |
| 3761 | struct comedi_insn *insn, |
| 3762 | unsigned int *data) |
| 3763 | { |
| 3764 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 3765 | unsigned int clk_fout = devpriv->clock_and_fout; |
H Hartley Sweeten | 189e173 | 2014-05-28 16:26:36 -0700 | [diff] [blame] | 3766 | int err = insn->n; |
| 3767 | unsigned char byte_out, byte_in = 0; |
| 3768 | |
| 3769 | if (insn->n != 2) |
| 3770 | return -EINVAL; |
| 3771 | |
| 3772 | switch (data[0]) { |
| 3773 | case INSN_CONFIG_SERIAL_CLOCK: |
| 3774 | devpriv->serial_hw_mode = 1; |
H Hartley Sweeten | 59a97c3 | 2015-05-01 14:59:02 -0700 | [diff] [blame] | 3775 | devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_ENA; |
H Hartley Sweeten | 189e173 | 2014-05-28 16:26:36 -0700 | [diff] [blame] | 3776 | |
| 3777 | if (data[1] == SERIAL_DISABLED) { |
| 3778 | devpriv->serial_hw_mode = 0; |
H Hartley Sweeten | 59a97c3 | 2015-05-01 14:59:02 -0700 | [diff] [blame] | 3779 | devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA | |
| 3780 | NISTC_DIO_SDCLK); |
H Hartley Sweeten | 189e173 | 2014-05-28 16:26:36 -0700 | [diff] [blame] | 3781 | data[1] = SERIAL_DISABLED; |
| 3782 | devpriv->serial_interval_ns = data[1]; |
| 3783 | } else if (data[1] <= SERIAL_600NS) { |
H Hartley Sweeten | bd474a0 | 2016-04-14 09:57:55 -0700 | [diff] [blame] | 3784 | /* |
| 3785 | * Warning: this clock speed is too fast to reliably |
| 3786 | * control SCXI. |
| 3787 | */ |
H Hartley Sweeten | 59a97c3 | 2015-05-01 14:59:02 -0700 | [diff] [blame] | 3788 | devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE; |
H Hartley Sweeten | a47fc02 | 2015-05-01 14:59:10 -0700 | [diff] [blame] | 3789 | clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE; |
| 3790 | clk_fout &= ~NISTC_CLK_FOUT_DIO_SER_OUT_DIV2; |
H Hartley Sweeten | 189e173 | 2014-05-28 16:26:36 -0700 | [diff] [blame] | 3791 | data[1] = SERIAL_600NS; |
| 3792 | devpriv->serial_interval_ns = data[1]; |
| 3793 | } else if (data[1] <= SERIAL_1_2US) { |
H Hartley Sweeten | 59a97c3 | 2015-05-01 14:59:02 -0700 | [diff] [blame] | 3794 | devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE; |
H Hartley Sweeten | a47fc02 | 2015-05-01 14:59:10 -0700 | [diff] [blame] | 3795 | clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE | |
| 3796 | NISTC_CLK_FOUT_DIO_SER_OUT_DIV2; |
H Hartley Sweeten | 189e173 | 2014-05-28 16:26:36 -0700 | [diff] [blame] | 3797 | data[1] = SERIAL_1_2US; |
| 3798 | devpriv->serial_interval_ns = data[1]; |
| 3799 | } else if (data[1] <= SERIAL_10US) { |
H Hartley Sweeten | 59a97c3 | 2015-05-01 14:59:02 -0700 | [diff] [blame] | 3800 | devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_TIMEBASE; |
H Hartley Sweeten | a47fc02 | 2015-05-01 14:59:10 -0700 | [diff] [blame] | 3801 | clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE | |
| 3802 | NISTC_CLK_FOUT_DIO_SER_OUT_DIV2; |
H Hartley Sweeten | bd474a0 | 2016-04-14 09:57:55 -0700 | [diff] [blame] | 3803 | /* |
| 3804 | * Note: NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 only affects |
| 3805 | * 600ns/1.2us. If you turn divide_by_2 off with the |
| 3806 | * slow clock, you will still get 10us, except then |
| 3807 | * all your delays are wrong. |
| 3808 | */ |
H Hartley Sweeten | 189e173 | 2014-05-28 16:26:36 -0700 | [diff] [blame] | 3809 | data[1] = SERIAL_10US; |
| 3810 | devpriv->serial_interval_ns = data[1]; |
| 3811 | } else { |
H Hartley Sweeten | 59a97c3 | 2015-05-01 14:59:02 -0700 | [diff] [blame] | 3812 | devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA | |
| 3813 | NISTC_DIO_SDCLK); |
H Hartley Sweeten | 189e173 | 2014-05-28 16:26:36 -0700 | [diff] [blame] | 3814 | devpriv->serial_hw_mode = 0; |
| 3815 | data[1] = (data[1] / 1000) * 1000; |
| 3816 | devpriv->serial_interval_ns = data[1]; |
| 3817 | } |
H Hartley Sweeten | a47fc02 | 2015-05-01 14:59:10 -0700 | [diff] [blame] | 3818 | devpriv->clock_and_fout = clk_fout; |
H Hartley Sweeten | 189e173 | 2014-05-28 16:26:36 -0700 | [diff] [blame] | 3819 | |
H Hartley Sweeten | 59a97c3 | 2015-05-01 14:59:02 -0700 | [diff] [blame] | 3820 | ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); |
H Hartley Sweeten | a47fc02 | 2015-05-01 14:59:10 -0700 | [diff] [blame] | 3821 | ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG); |
H Hartley Sweeten | 189e173 | 2014-05-28 16:26:36 -0700 | [diff] [blame] | 3822 | return 1; |
| 3823 | |
H Hartley Sweeten | 189e173 | 2014-05-28 16:26:36 -0700 | [diff] [blame] | 3824 | case INSN_CONFIG_BIDIRECTIONAL_DATA: |
| 3825 | |
| 3826 | if (devpriv->serial_interval_ns == 0) |
| 3827 | return -EINVAL; |
| 3828 | |
| 3829 | byte_out = data[1] & 0xFF; |
| 3830 | |
| 3831 | if (devpriv->serial_hw_mode) { |
| 3832 | err = ni_serial_hw_readwrite8(dev, s, byte_out, |
| 3833 | &byte_in); |
| 3834 | } else if (devpriv->serial_interval_ns > 0) { |
| 3835 | err = ni_serial_sw_readwrite8(dev, s, byte_out, |
| 3836 | &byte_in); |
| 3837 | } else { |
Haneen Mohammed | cd25503 | 2015-03-05 13:01:49 +0300 | [diff] [blame] | 3838 | dev_err(dev->class_dev, "serial disabled!\n"); |
H Hartley Sweeten | 189e173 | 2014-05-28 16:26:36 -0700 | [diff] [blame] | 3839 | return -EINVAL; |
| 3840 | } |
| 3841 | if (err < 0) |
| 3842 | return err; |
| 3843 | data[1] = byte_in & 0xFF; |
| 3844 | return insn->n; |
| 3845 | |
| 3846 | break; |
| 3847 | default: |
| 3848 | return -EINVAL; |
| 3849 | } |
H Hartley Sweeten | 189e173 | 2014-05-28 16:26:36 -0700 | [diff] [blame] | 3850 | } |
| 3851 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 3852 | static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3853 | { |
| 3854 | int i; |
| 3855 | |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 3856 | for (i = 0; i < s->n_chan; i++) { |
H Hartley Sweeten | b497b8d | 2015-05-01 14:59:59 -0700 | [diff] [blame] | 3857 | ni_ao_win_outw(dev, NI_E_AO_DACSEL(i) | 0x0, |
H Hartley Sweeten | ef39154 | 2015-05-01 15:00:11 -0700 | [diff] [blame] | 3858 | NI67XX_AO_CFG2_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3859 | } |
H Hartley Sweeten | ef39154 | 2015-05-01 15:00:11 -0700 | [diff] [blame] | 3860 | ni_ao_win_outw(dev, 0x0, NI67XX_AO_SP_UPDATES_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3861 | } |
| 3862 | |
H Hartley Sweeten | cfdb3429 | 2015-05-01 14:58:28 -0700 | [diff] [blame] | 3863 | static const struct mio_regmap ni_gpct_to_stc_regmap[] = { |
H Hartley Sweeten | 38aba4c | 2015-05-01 14:59:23 -0700 | [diff] [blame] | 3864 | [NITIO_G0_AUTO_INC] = { NISTC_G0_AUTOINC_REG, 2 }, |
| 3865 | [NITIO_G1_AUTO_INC] = { NISTC_G1_AUTOINC_REG, 2 }, |
H Hartley Sweeten | 5fa2fa4 | 2015-05-01 14:58:58 -0700 | [diff] [blame] | 3866 | [NITIO_G0_CMD] = { NISTC_G0_CMD_REG, 2 }, |
| 3867 | [NITIO_G1_CMD] = { NISTC_G1_CMD_REG, 2 }, |
H Hartley Sweeten | 27650d9 | 2015-05-01 14:59:43 -0700 | [diff] [blame] | 3868 | [NITIO_G0_HW_SAVE] = { NISTC_G0_HW_SAVE_REG, 4 }, |
| 3869 | [NITIO_G1_HW_SAVE] = { NISTC_G1_HW_SAVE_REG, 4 }, |
H Hartley Sweeten | d9c4115 | 2015-05-01 14:59:44 -0700 | [diff] [blame] | 3870 | [NITIO_G0_SW_SAVE] = { NISTC_G0_SAVE_REG, 4 }, |
| 3871 | [NITIO_G1_SW_SAVE] = { NISTC_G1_SAVE_REG, 4 }, |
H Hartley Sweeten | aff2700 | 2015-05-01 14:59:06 -0700 | [diff] [blame] | 3872 | [NITIO_G0_MODE] = { NISTC_G0_MODE_REG, 2 }, |
| 3873 | [NITIO_G1_MODE] = { NISTC_G1_MODE_REG, 2 }, |
| 3874 | [NITIO_G0_LOADA] = { NISTC_G0_LOADA_REG, 4 }, |
| 3875 | [NITIO_G1_LOADA] = { NISTC_G1_LOADA_REG, 4 }, |
| 3876 | [NITIO_G0_LOADB] = { NISTC_G0_LOADB_REG, 4 }, |
| 3877 | [NITIO_G1_LOADB] = { NISTC_G1_LOADB_REG, 4 }, |
| 3878 | [NITIO_G0_INPUT_SEL] = { NISTC_G0_INPUT_SEL_REG, 2 }, |
| 3879 | [NITIO_G1_INPUT_SEL] = { NISTC_G1_INPUT_SEL_REG, 2 }, |
H Hartley Sweeten | 0a9752d | 2015-05-01 14:58:29 -0700 | [diff] [blame] | 3880 | [NITIO_G0_CNT_MODE] = { 0x1b0, 2 }, /* M-Series only */ |
| 3881 | [NITIO_G1_CNT_MODE] = { 0x1b2, 2 }, /* M-Series only */ |
| 3882 | [NITIO_G0_GATE2] = { 0x1b4, 2 }, /* M-Series only */ |
| 3883 | [NITIO_G1_GATE2] = { 0x1b6, 2 }, /* M-Series only */ |
H Hartley Sweeten | 7f0e1ba | 2015-05-01 14:59:39 -0700 | [diff] [blame] | 3884 | [NITIO_G01_STATUS] = { NISTC_G01_STATUS_REG, 2 }, |
H Hartley Sweeten | 707502f | 2015-05-01 14:59:25 -0700 | [diff] [blame] | 3885 | [NITIO_G01_RESET] = { NISTC_RESET_REG, 2 }, |
H Hartley Sweeten | d3fed08 | 2015-05-01 14:59:46 -0700 | [diff] [blame] | 3886 | [NITIO_G01_STATUS1] = { NISTC_STATUS1_REG, 2 }, |
H Hartley Sweeten | bab382e | 2015-05-01 14:59:48 -0700 | [diff] [blame] | 3887 | [NITIO_G01_STATUS2] = { NISTC_STATUS2_REG, 2 }, |
H Hartley Sweeten | 0a9752d | 2015-05-01 14:58:29 -0700 | [diff] [blame] | 3888 | [NITIO_G0_DMA_CFG] = { 0x1b8, 2 }, /* M-Series only */ |
| 3889 | [NITIO_G1_DMA_CFG] = { 0x1ba, 2 }, /* M-Series only */ |
| 3890 | [NITIO_G0_DMA_STATUS] = { 0x1b8, 2 }, /* M-Series only */ |
| 3891 | [NITIO_G1_DMA_STATUS] = { 0x1ba, 2 }, /* M-Series only */ |
| 3892 | [NITIO_G0_ABZ] = { 0x1c0, 2 }, /* M-Series only */ |
| 3893 | [NITIO_G1_ABZ] = { 0x1c2, 2 }, /* M-Series only */ |
H Hartley Sweeten | 480456d | 2015-05-01 14:58:54 -0700 | [diff] [blame] | 3894 | [NITIO_G0_INT_ACK] = { NISTC_INTA_ACK_REG, 2 }, |
H Hartley Sweeten | 4a6de832 | 2015-05-01 14:58:55 -0700 | [diff] [blame] | 3895 | [NITIO_G1_INT_ACK] = { NISTC_INTB_ACK_REG, 2 }, |
H Hartley Sweeten | 7b14fff | 2015-05-01 14:59:37 -0700 | [diff] [blame] | 3896 | [NITIO_G0_STATUS] = { NISTC_AI_STATUS1_REG, 2 }, |
H Hartley Sweeten | d123ee3 | 2015-05-01 14:59:38 -0700 | [diff] [blame] | 3897 | [NITIO_G1_STATUS] = { NISTC_AO_STATUS1_REG, 2 }, |
H Hartley Sweeten | 5cca26a | 2015-05-01 14:59:26 -0700 | [diff] [blame] | 3898 | [NITIO_G0_INT_ENA] = { NISTC_INTA_ENA_REG, 2 }, |
H Hartley Sweeten | 4c9c1d2 | 2015-05-01 14:59:28 -0700 | [diff] [blame] | 3899 | [NITIO_G1_INT_ENA] = { NISTC_INTB_ENA_REG, 2 }, |
H Hartley Sweeten | cfdb3429 | 2015-05-01 14:58:28 -0700 | [diff] [blame] | 3900 | }; |
H Hartley Sweeten | f740197 | 2014-07-16 11:02:08 -0700 | [diff] [blame] | 3901 | |
H Hartley Sweeten | cfdb3429 | 2015-05-01 14:58:28 -0700 | [diff] [blame] | 3902 | static unsigned int ni_gpct_to_stc_register(struct comedi_device *dev, |
| 3903 | enum ni_gpct_register reg) |
| 3904 | { |
| 3905 | const struct mio_regmap *regmap; |
| 3906 | |
| 3907 | if (reg < ARRAY_SIZE(ni_gpct_to_stc_regmap)) { |
| 3908 | regmap = &ni_gpct_to_stc_regmap[reg]; |
| 3909 | } else { |
Geliang Tang | 71f50e2 | 2015-05-25 14:20:44 +0000 | [diff] [blame] | 3910 | dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n", |
H Hartley Sweeten | cfdb3429 | 2015-05-01 14:58:28 -0700 | [diff] [blame] | 3911 | __func__, reg); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3912 | return 0; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3913 | } |
H Hartley Sweeten | cfdb3429 | 2015-05-01 14:58:28 -0700 | [diff] [blame] | 3914 | |
| 3915 | return regmap->mio_reg; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3916 | } |
| 3917 | |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 3918 | static void ni_gpct_write_register(struct ni_gpct *counter, unsigned int bits, |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 3919 | enum ni_gpct_register reg) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3920 | { |
Bill Pemberton | 71b5f4f | 2009-03-16 22:05:08 -0400 | [diff] [blame] | 3921 | struct comedi_device *dev = counter->counter_dev->dev; |
H Hartley Sweeten | cfdb3429 | 2015-05-01 14:58:28 -0700 | [diff] [blame] | 3922 | unsigned int stc_register = ni_gpct_to_stc_register(dev, reg); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3923 | |
H Hartley Sweeten | cfdb3429 | 2015-05-01 14:58:28 -0700 | [diff] [blame] | 3924 | if (stc_register == 0) |
| 3925 | return; |
| 3926 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3927 | switch (reg) { |
H Hartley Sweeten | cfdb3429 | 2015-05-01 14:58:28 -0700 | [diff] [blame] | 3928 | /* m-series only registers */ |
H Hartley Sweeten | 1237529 | 2013-12-19 16:31:33 -0700 | [diff] [blame] | 3929 | case NITIO_G0_CNT_MODE: |
H Hartley Sweeten | 1237529 | 2013-12-19 16:31:33 -0700 | [diff] [blame] | 3930 | case NITIO_G1_CNT_MODE: |
H Hartley Sweeten | 1237529 | 2013-12-19 16:31:33 -0700 | [diff] [blame] | 3931 | case NITIO_G0_GATE2: |
H Hartley Sweeten | 1237529 | 2013-12-19 16:31:33 -0700 | [diff] [blame] | 3932 | case NITIO_G1_GATE2: |
H Hartley Sweeten | 1237529 | 2013-12-19 16:31:33 -0700 | [diff] [blame] | 3933 | case NITIO_G0_DMA_CFG: |
H Hartley Sweeten | 1237529 | 2013-12-19 16:31:33 -0700 | [diff] [blame] | 3934 | case NITIO_G1_DMA_CFG: |
H Hartley Sweeten | 1237529 | 2013-12-19 16:31:33 -0700 | [diff] [blame] | 3935 | case NITIO_G0_ABZ: |
H Hartley Sweeten | 1237529 | 2013-12-19 16:31:33 -0700 | [diff] [blame] | 3936 | case NITIO_G1_ABZ: |
H Hartley Sweeten | cfdb3429 | 2015-05-01 14:58:28 -0700 | [diff] [blame] | 3937 | ni_writew(dev, bits, stc_register); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3938 | break; |
| 3939 | |
| 3940 | /* 32 bit registers */ |
H Hartley Sweeten | 1237529 | 2013-12-19 16:31:33 -0700 | [diff] [blame] | 3941 | case NITIO_G0_LOADA: |
| 3942 | case NITIO_G1_LOADA: |
| 3943 | case NITIO_G0_LOADB: |
| 3944 | case NITIO_G1_LOADB: |
H Hartley Sweeten | 00b14b1 | 2014-06-19 10:20:34 -0700 | [diff] [blame] | 3945 | ni_stc_writel(dev, bits, stc_register); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3946 | break; |
| 3947 | |
| 3948 | /* 16 bit registers */ |
H Hartley Sweeten | 1237529 | 2013-12-19 16:31:33 -0700 | [diff] [blame] | 3949 | case NITIO_G0_INT_ENA: |
H Hartley Sweeten | cfdb3429 | 2015-05-01 14:58:28 -0700 | [diff] [blame] | 3950 | ni_set_bitfield(dev, stc_register, |
H Hartley Sweeten | 2e2f7b7 | 2016-04-14 09:58:02 -0700 | [diff] [blame] | 3951 | NISTC_INTA_ENA_G0_GATE | NISTC_INTA_ENA_G0_TC, |
| 3952 | bits); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3953 | break; |
H Hartley Sweeten | 1237529 | 2013-12-19 16:31:33 -0700 | [diff] [blame] | 3954 | case NITIO_G1_INT_ENA: |
H Hartley Sweeten | cfdb3429 | 2015-05-01 14:58:28 -0700 | [diff] [blame] | 3955 | ni_set_bitfield(dev, stc_register, |
H Hartley Sweeten | 2e2f7b7 | 2016-04-14 09:58:02 -0700 | [diff] [blame] | 3956 | NISTC_INTB_ENA_G1_GATE | NISTC_INTB_ENA_G1_TC, |
| 3957 | bits); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3958 | break; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3959 | default: |
H Hartley Sweeten | 00b14b1 | 2014-06-19 10:20:34 -0700 | [diff] [blame] | 3960 | ni_stc_writew(dev, bits, stc_register); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3961 | } |
| 3962 | } |
| 3963 | |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 3964 | static unsigned int ni_gpct_read_register(struct ni_gpct *counter, |
| 3965 | enum ni_gpct_register reg) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3966 | { |
Bill Pemberton | 71b5f4f | 2009-03-16 22:05:08 -0400 | [diff] [blame] | 3967 | struct comedi_device *dev = counter->counter_dev->dev; |
H Hartley Sweeten | cfdb3429 | 2015-05-01 14:58:28 -0700 | [diff] [blame] | 3968 | unsigned int stc_register = ni_gpct_to_stc_register(dev, reg); |
| 3969 | |
| 3970 | if (stc_register == 0) |
| 3971 | return 0; |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 3972 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3973 | switch (reg) { |
| 3974 | /* m-series only registers */ |
H Hartley Sweeten | 1237529 | 2013-12-19 16:31:33 -0700 | [diff] [blame] | 3975 | case NITIO_G0_DMA_STATUS: |
H Hartley Sweeten | 1237529 | 2013-12-19 16:31:33 -0700 | [diff] [blame] | 3976 | case NITIO_G1_DMA_STATUS: |
H Hartley Sweeten | cfdb3429 | 2015-05-01 14:58:28 -0700 | [diff] [blame] | 3977 | return ni_readw(dev, stc_register); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3978 | |
| 3979 | /* 32 bit registers */ |
H Hartley Sweeten | 1237529 | 2013-12-19 16:31:33 -0700 | [diff] [blame] | 3980 | case NITIO_G0_HW_SAVE: |
| 3981 | case NITIO_G1_HW_SAVE: |
| 3982 | case NITIO_G0_SW_SAVE: |
| 3983 | case NITIO_G1_SW_SAVE: |
H Hartley Sweeten | 00b14b1 | 2014-06-19 10:20:34 -0700 | [diff] [blame] | 3984 | return ni_stc_readl(dev, stc_register); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3985 | |
| 3986 | /* 16 bit registers */ |
| 3987 | default: |
H Hartley Sweeten | 00b14b1 | 2014-06-19 10:20:34 -0700 | [diff] [blame] | 3988 | return ni_stc_readw(dev, stc_register); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3989 | } |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3990 | } |
| 3991 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 3992 | static int ni_freq_out_insn_read(struct comedi_device *dev, |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 3993 | struct comedi_subdevice *s, |
H Hartley Sweeten | d9c4261 | 2014-05-28 16:26:54 -0700 | [diff] [blame] | 3994 | struct comedi_insn *insn, |
| 3995 | unsigned int *data) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 3996 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 3997 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | a47fc02 | 2015-05-01 14:59:10 -0700 | [diff] [blame] | 3998 | unsigned int val = NISTC_CLK_FOUT_TO_DIVIDER(devpriv->clock_and_fout); |
H Hartley Sweeten | d9c4261 | 2014-05-28 16:26:54 -0700 | [diff] [blame] | 3999 | int i; |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 4000 | |
H Hartley Sweeten | d9c4261 | 2014-05-28 16:26:54 -0700 | [diff] [blame] | 4001 | for (i = 0; i < insn->n; i++) |
| 4002 | data[i] = val; |
| 4003 | |
| 4004 | return insn->n; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 4005 | } |
| 4006 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 4007 | static int ni_freq_out_insn_write(struct comedi_device *dev, |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 4008 | struct comedi_subdevice *s, |
H Hartley Sweeten | 00a92c0 | 2014-05-28 16:26:53 -0700 | [diff] [blame] | 4009 | struct comedi_insn *insn, |
| 4010 | unsigned int *data) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 4011 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 4012 | struct ni_private *devpriv = dev->private; |
| 4013 | |
H Hartley Sweeten | 00a92c0 | 2014-05-28 16:26:53 -0700 | [diff] [blame] | 4014 | if (insn->n) { |
H Hartley Sweeten | a47fc02 | 2015-05-01 14:59:10 -0700 | [diff] [blame] | 4015 | unsigned int val = data[insn->n - 1]; |
| 4016 | |
| 4017 | devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_ENA; |
| 4018 | ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG); |
| 4019 | devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_DIVIDER_MASK; |
H Hartley Sweeten | 00a92c0 | 2014-05-28 16:26:53 -0700 | [diff] [blame] | 4020 | |
| 4021 | /* use the last data value to set the fout divider */ |
H Hartley Sweeten | a47fc02 | 2015-05-01 14:59:10 -0700 | [diff] [blame] | 4022 | devpriv->clock_and_fout |= NISTC_CLK_FOUT_DIVIDER(val); |
H Hartley Sweeten | 00a92c0 | 2014-05-28 16:26:53 -0700 | [diff] [blame] | 4023 | |
H Hartley Sweeten | a47fc02 | 2015-05-01 14:59:10 -0700 | [diff] [blame] | 4024 | devpriv->clock_and_fout |= NISTC_CLK_FOUT_ENA; |
| 4025 | ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG); |
H Hartley Sweeten | 00a92c0 | 2014-05-28 16:26:53 -0700 | [diff] [blame] | 4026 | } |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 4027 | return insn->n; |
| 4028 | } |
| 4029 | |
H Hartley Sweeten | e63dabd | 2014-05-28 16:26:52 -0700 | [diff] [blame] | 4030 | static int ni_freq_out_insn_config(struct comedi_device *dev, |
| 4031 | struct comedi_subdevice *s, |
| 4032 | struct comedi_insn *insn, |
| 4033 | unsigned int *data) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 4034 | { |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 4035 | struct ni_private *devpriv = dev->private; |
| 4036 | |
H Hartley Sweeten | e63dabd | 2014-05-28 16:26:52 -0700 | [diff] [blame] | 4037 | switch (data[0]) { |
| 4038 | case INSN_CONFIG_SET_CLOCK_SRC: |
| 4039 | switch (data[1]) { |
| 4040 | case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC: |
H Hartley Sweeten | a47fc02 | 2015-05-01 14:59:10 -0700 | [diff] [blame] | 4041 | devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_TIMEBASE_SEL; |
H Hartley Sweeten | e63dabd | 2014-05-28 16:26:52 -0700 | [diff] [blame] | 4042 | break; |
| 4043 | case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC: |
H Hartley Sweeten | a47fc02 | 2015-05-01 14:59:10 -0700 | [diff] [blame] | 4044 | devpriv->clock_and_fout |= NISTC_CLK_FOUT_TIMEBASE_SEL; |
H Hartley Sweeten | e63dabd | 2014-05-28 16:26:52 -0700 | [diff] [blame] | 4045 | break; |
| 4046 | default: |
| 4047 | return -EINVAL; |
| 4048 | } |
H Hartley Sweeten | a47fc02 | 2015-05-01 14:59:10 -0700 | [diff] [blame] | 4049 | ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 4050 | break; |
H Hartley Sweeten | e63dabd | 2014-05-28 16:26:52 -0700 | [diff] [blame] | 4051 | case INSN_CONFIG_GET_CLOCK_SRC: |
H Hartley Sweeten | a47fc02 | 2015-05-01 14:59:10 -0700 | [diff] [blame] | 4052 | if (devpriv->clock_and_fout & NISTC_CLK_FOUT_TIMEBASE_SEL) { |
H Hartley Sweeten | e63dabd | 2014-05-28 16:26:52 -0700 | [diff] [blame] | 4053 | data[1] = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC; |
| 4054 | data[2] = TIMEBASE_2_NS; |
| 4055 | } else { |
| 4056 | data[1] = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC; |
| 4057 | data[2] = TIMEBASE_1_NS * 2; |
| 4058 | } |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 4059 | break; |
| 4060 | default: |
| 4061 | return -EINVAL; |
| 4062 | } |
H Hartley Sweeten | e63dabd | 2014-05-28 16:26:52 -0700 | [diff] [blame] | 4063 | return insn->n; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 4064 | } |
| 4065 | |
H Hartley Sweeten | 67393c4 | 2014-08-12 11:41:20 -0700 | [diff] [blame] | 4066 | static int ni_8255_callback(struct comedi_device *dev, |
| 4067 | int dir, int port, int data, unsigned long iobase) |
H Hartley Sweeten | f598586 | 2014-05-28 16:26:24 -0700 | [diff] [blame] | 4068 | { |
H Hartley Sweeten | f598586 | 2014-05-28 16:26:24 -0700 | [diff] [blame] | 4069 | if (dir) { |
H Hartley Sweeten | 67393c4 | 2014-08-12 11:41:20 -0700 | [diff] [blame] | 4070 | ni_writeb(dev, data, iobase + 2 * port); |
H Hartley Sweeten | f598586 | 2014-05-28 16:26:24 -0700 | [diff] [blame] | 4071 | return 0; |
H Hartley Sweeten | f598586 | 2014-05-28 16:26:24 -0700 | [diff] [blame] | 4072 | } |
H Hartley Sweeten | 0953ee4 | 2014-07-16 10:43:34 -0700 | [diff] [blame] | 4073 | |
H Hartley Sweeten | 67393c4 | 2014-08-12 11:41:20 -0700 | [diff] [blame] | 4074 | return ni_readb(dev, iobase + 2 * port); |
H Hartley Sweeten | f598586 | 2014-05-28 16:26:24 -0700 | [diff] [blame] | 4075 | } |
| 4076 | |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4077 | static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data) |
| 4078 | { |
| 4079 | struct ni_private *devpriv = dev->private; |
| 4080 | |
| 4081 | data[1] = devpriv->pwm_up_count * devpriv->clock_ns; |
| 4082 | data[2] = devpriv->pwm_down_count * devpriv->clock_ns; |
| 4083 | return 3; |
| 4084 | } |
| 4085 | |
| 4086 | static int ni_m_series_pwm_config(struct comedi_device *dev, |
| 4087 | struct comedi_subdevice *s, |
| 4088 | struct comedi_insn *insn, |
| 4089 | unsigned int *data) |
| 4090 | { |
| 4091 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 4092 | unsigned int up_count, down_count; |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4093 | |
| 4094 | switch (data[0]) { |
| 4095 | case INSN_CONFIG_PWM_OUTPUT: |
| 4096 | switch (data[1]) { |
Ian Abbott | 3280c2d | 2014-09-03 13:45:57 +0100 | [diff] [blame] | 4097 | case CMDF_ROUND_NEAREST: |
Bhaktipriya Shridhar | 1e5a05d | 2016-02-21 16:13:01 +0530 | [diff] [blame] | 4098 | up_count = DIV_ROUND_CLOSEST(data[2], |
| 4099 | devpriv->clock_ns); |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4100 | break; |
Ian Abbott | 3280c2d | 2014-09-03 13:45:57 +0100 | [diff] [blame] | 4101 | case CMDF_ROUND_DOWN: |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4102 | up_count = data[2] / devpriv->clock_ns; |
| 4103 | break; |
Ian Abbott | 3280c2d | 2014-09-03 13:45:57 +0100 | [diff] [blame] | 4104 | case CMDF_ROUND_UP: |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4105 | up_count = |
Bhaktipriya Shridhar | 7f9d2b1 | 2016-03-10 00:05:16 +0530 | [diff] [blame] | 4106 | DIV_ROUND_UP(data[2], devpriv->clock_ns); |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4107 | break; |
| 4108 | default: |
| 4109 | return -EINVAL; |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4110 | } |
| 4111 | switch (data[3]) { |
Ian Abbott | 3280c2d | 2014-09-03 13:45:57 +0100 | [diff] [blame] | 4112 | case CMDF_ROUND_NEAREST: |
Bhaktipriya Shridhar | 1e5a05d | 2016-02-21 16:13:01 +0530 | [diff] [blame] | 4113 | down_count = DIV_ROUND_CLOSEST(data[4], |
| 4114 | devpriv->clock_ns); |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4115 | break; |
Ian Abbott | 3280c2d | 2014-09-03 13:45:57 +0100 | [diff] [blame] | 4116 | case CMDF_ROUND_DOWN: |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4117 | down_count = data[4] / devpriv->clock_ns; |
| 4118 | break; |
Ian Abbott | 3280c2d | 2014-09-03 13:45:57 +0100 | [diff] [blame] | 4119 | case CMDF_ROUND_UP: |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4120 | down_count = |
Bhaktipriya Shridhar | 7f9d2b1 | 2016-03-10 00:05:16 +0530 | [diff] [blame] | 4121 | DIV_ROUND_UP(data[4], devpriv->clock_ns); |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4122 | break; |
| 4123 | default: |
| 4124 | return -EINVAL; |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4125 | } |
| 4126 | if (up_count * devpriv->clock_ns != data[2] || |
| 4127 | down_count * devpriv->clock_ns != data[4]) { |
| 4128 | data[2] = up_count * devpriv->clock_ns; |
| 4129 | data[4] = down_count * devpriv->clock_ns; |
| 4130 | return -EAGAIN; |
| 4131 | } |
H Hartley Sweeten | cc679f9 | 2015-05-01 14:58:42 -0700 | [diff] [blame] | 4132 | ni_writel(dev, NI_M_CAL_PWM_HIGH_TIME(up_count) | |
| 4133 | NI_M_CAL_PWM_LOW_TIME(down_count), |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 4134 | NI_M_CAL_PWM_REG); |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4135 | devpriv->pwm_up_count = up_count; |
| 4136 | devpriv->pwm_down_count = down_count; |
| 4137 | return 5; |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4138 | case INSN_CONFIG_GET_PWM_OUTPUT: |
| 4139 | return ni_get_pwm_config(dev, data); |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4140 | default: |
| 4141 | return -EINVAL; |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4142 | } |
| 4143 | return 0; |
| 4144 | } |
| 4145 | |
| 4146 | static int ni_6143_pwm_config(struct comedi_device *dev, |
| 4147 | struct comedi_subdevice *s, |
| 4148 | struct comedi_insn *insn, |
| 4149 | unsigned int *data) |
| 4150 | { |
| 4151 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 4152 | unsigned int up_count, down_count; |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4153 | |
| 4154 | switch (data[0]) { |
| 4155 | case INSN_CONFIG_PWM_OUTPUT: |
| 4156 | switch (data[1]) { |
Ian Abbott | 3280c2d | 2014-09-03 13:45:57 +0100 | [diff] [blame] | 4157 | case CMDF_ROUND_NEAREST: |
Bhaktipriya Shridhar | 1e5a05d | 2016-02-21 16:13:01 +0530 | [diff] [blame] | 4158 | up_count = DIV_ROUND_CLOSEST(data[2], |
| 4159 | devpriv->clock_ns); |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4160 | break; |
Ian Abbott | 3280c2d | 2014-09-03 13:45:57 +0100 | [diff] [blame] | 4161 | case CMDF_ROUND_DOWN: |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4162 | up_count = data[2] / devpriv->clock_ns; |
| 4163 | break; |
Ian Abbott | 3280c2d | 2014-09-03 13:45:57 +0100 | [diff] [blame] | 4164 | case CMDF_ROUND_UP: |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4165 | up_count = |
Bhaktipriya Shridhar | 7f9d2b1 | 2016-03-10 00:05:16 +0530 | [diff] [blame] | 4166 | DIV_ROUND_UP(data[2], devpriv->clock_ns); |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4167 | break; |
| 4168 | default: |
| 4169 | return -EINVAL; |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4170 | } |
| 4171 | switch (data[3]) { |
Ian Abbott | 3280c2d | 2014-09-03 13:45:57 +0100 | [diff] [blame] | 4172 | case CMDF_ROUND_NEAREST: |
Bhaktipriya Shridhar | 1e5a05d | 2016-02-21 16:13:01 +0530 | [diff] [blame] | 4173 | down_count = DIV_ROUND_CLOSEST(data[4], |
| 4174 | devpriv->clock_ns); |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4175 | break; |
Ian Abbott | 3280c2d | 2014-09-03 13:45:57 +0100 | [diff] [blame] | 4176 | case CMDF_ROUND_DOWN: |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4177 | down_count = data[4] / devpriv->clock_ns; |
| 4178 | break; |
Ian Abbott | 3280c2d | 2014-09-03 13:45:57 +0100 | [diff] [blame] | 4179 | case CMDF_ROUND_UP: |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4180 | down_count = |
Bhaktipriya Shridhar | 7f9d2b1 | 2016-03-10 00:05:16 +0530 | [diff] [blame] | 4181 | DIV_ROUND_UP(data[4], devpriv->clock_ns); |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4182 | break; |
| 4183 | default: |
| 4184 | return -EINVAL; |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4185 | } |
| 4186 | if (up_count * devpriv->clock_ns != data[2] || |
| 4187 | down_count * devpriv->clock_ns != data[4]) { |
| 4188 | data[2] = up_count * devpriv->clock_ns; |
| 4189 | data[4] = down_count * devpriv->clock_ns; |
| 4190 | return -EAGAIN; |
| 4191 | } |
H Hartley Sweeten | ee3e21a | 2015-05-01 15:00:08 -0700 | [diff] [blame] | 4192 | ni_writel(dev, up_count, NI6143_CALIB_HI_TIME_REG); |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4193 | devpriv->pwm_up_count = up_count; |
H Hartley Sweeten | ee3e21a | 2015-05-01 15:00:08 -0700 | [diff] [blame] | 4194 | ni_writel(dev, down_count, NI6143_CALIB_LO_TIME_REG); |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4195 | devpriv->pwm_down_count = down_count; |
| 4196 | return 5; |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4197 | case INSN_CONFIG_GET_PWM_OUTPUT: |
| 4198 | return ni_get_pwm_config(dev, data); |
| 4199 | default: |
| 4200 | return -EINVAL; |
H Hartley Sweeten | 1e49c5d | 2014-05-28 16:26:26 -0700 | [diff] [blame] | 4201 | } |
| 4202 | return 0; |
| 4203 | } |
| 4204 | |
H Hartley Sweeten | 62c2bce | 2014-05-28 16:26:28 -0700 | [diff] [blame] | 4205 | static int pack_mb88341(int addr, int val, int *bitstring) |
| 4206 | { |
| 4207 | /* |
H Hartley Sweeten | bd474a0 | 2016-04-14 09:57:55 -0700 | [diff] [blame] | 4208 | * Fujitsu MB 88341 |
| 4209 | * Note that address bits are reversed. Thanks to |
| 4210 | * Ingo Keen for noticing this. |
| 4211 | * |
| 4212 | * Note also that the 88341 expects address values from |
| 4213 | * 1-12, whereas we use channel numbers 0-11. The NI |
| 4214 | * docs use 1-12, also, so be careful here. |
H Hartley Sweeten | 62c2bce | 2014-05-28 16:26:28 -0700 | [diff] [blame] | 4215 | */ |
| 4216 | addr++; |
| 4217 | *bitstring = ((addr & 0x1) << 11) | |
| 4218 | ((addr & 0x2) << 9) | |
| 4219 | ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff); |
| 4220 | return 12; |
| 4221 | } |
| 4222 | |
| 4223 | static int pack_dac8800(int addr, int val, int *bitstring) |
| 4224 | { |
| 4225 | *bitstring = ((addr & 0x7) << 8) | (val & 0xff); |
| 4226 | return 11; |
| 4227 | } |
| 4228 | |
| 4229 | static int pack_dac8043(int addr, int val, int *bitstring) |
| 4230 | { |
| 4231 | *bitstring = val & 0xfff; |
| 4232 | return 12; |
| 4233 | } |
| 4234 | |
| 4235 | static int pack_ad8522(int addr, int val, int *bitstring) |
| 4236 | { |
| 4237 | *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000); |
| 4238 | return 16; |
| 4239 | } |
| 4240 | |
| 4241 | static int pack_ad8804(int addr, int val, int *bitstring) |
| 4242 | { |
| 4243 | *bitstring = ((addr & 0xf) << 8) | (val & 0xff); |
| 4244 | return 12; |
| 4245 | } |
| 4246 | |
| 4247 | static int pack_ad8842(int addr, int val, int *bitstring) |
| 4248 | { |
| 4249 | *bitstring = ((addr + 1) << 8) | (val & 0xff); |
| 4250 | return 12; |
| 4251 | } |
| 4252 | |
| 4253 | struct caldac_struct { |
| 4254 | int n_chans; |
| 4255 | int n_bits; |
| 4256 | int (*packbits)(int, int, int *); |
| 4257 | }; |
| 4258 | |
| 4259 | static struct caldac_struct caldacs[] = { |
| 4260 | [mb88341] = {12, 8, pack_mb88341}, |
| 4261 | [dac8800] = {8, 8, pack_dac8800}, |
| 4262 | [dac8043] = {1, 12, pack_dac8043}, |
| 4263 | [ad8522] = {2, 12, pack_ad8522}, |
| 4264 | [ad8804] = {12, 8, pack_ad8804}, |
| 4265 | [ad8842] = {8, 8, pack_ad8842}, |
| 4266 | [ad8804_debug] = {16, 8, pack_ad8804}, |
| 4267 | }; |
| 4268 | |
| 4269 | static void ni_write_caldac(struct comedi_device *dev, int addr, int val) |
| 4270 | { |
Ian Abbott | 7cf94ad | 2014-09-09 11:26:44 +0100 | [diff] [blame] | 4271 | const struct ni_board_struct *board = dev->board_ptr; |
H Hartley Sweeten | 62c2bce | 2014-05-28 16:26:28 -0700 | [diff] [blame] | 4272 | struct ni_private *devpriv = dev->private; |
| 4273 | unsigned int loadbit = 0, bits = 0, bit, bitstring = 0; |
H Hartley Sweeten | 2ed183f | 2015-05-01 14:59:53 -0700 | [diff] [blame] | 4274 | unsigned int cmd; |
H Hartley Sweeten | 62c2bce | 2014-05-28 16:26:28 -0700 | [diff] [blame] | 4275 | int i; |
| 4276 | int type; |
| 4277 | |
H Hartley Sweeten | 62c2bce | 2014-05-28 16:26:28 -0700 | [diff] [blame] | 4278 | if (devpriv->caldacs[addr] == val) |
| 4279 | return; |
| 4280 | devpriv->caldacs[addr] = val; |
| 4281 | |
| 4282 | for (i = 0; i < 3; i++) { |
| 4283 | type = board->caldac[i]; |
| 4284 | if (type == caldac_none) |
| 4285 | break; |
| 4286 | if (addr < caldacs[type].n_chans) { |
| 4287 | bits = caldacs[type].packbits(addr, val, &bitstring); |
H Hartley Sweeten | 2ed183f | 2015-05-01 14:59:53 -0700 | [diff] [blame] | 4288 | loadbit = NI_E_SERIAL_CMD_DAC_LD(i); |
H Hartley Sweeten | 62c2bce | 2014-05-28 16:26:28 -0700 | [diff] [blame] | 4289 | break; |
| 4290 | } |
| 4291 | addr -= caldacs[type].n_chans; |
| 4292 | } |
| 4293 | |
H Hartley Sweeten | accb298 | 2015-04-20 11:49:05 -0700 | [diff] [blame] | 4294 | /* bits will be 0 if there is no caldac for the given addr */ |
| 4295 | if (bits == 0) |
| 4296 | return; |
| 4297 | |
H Hartley Sweeten | 62c2bce | 2014-05-28 16:26:28 -0700 | [diff] [blame] | 4298 | for (bit = 1 << (bits - 1); bit; bit >>= 1) { |
H Hartley Sweeten | 2ed183f | 2015-05-01 14:59:53 -0700 | [diff] [blame] | 4299 | cmd = (bit & bitstring) ? NI_E_SERIAL_CMD_SDATA : 0; |
| 4300 | ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG); |
H Hartley Sweeten | 62c2bce | 2014-05-28 16:26:28 -0700 | [diff] [blame] | 4301 | udelay(1); |
H Hartley Sweeten | 2ed183f | 2015-05-01 14:59:53 -0700 | [diff] [blame] | 4302 | ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG); |
H Hartley Sweeten | 62c2bce | 2014-05-28 16:26:28 -0700 | [diff] [blame] | 4303 | udelay(1); |
| 4304 | } |
H Hartley Sweeten | 2ed183f | 2015-05-01 14:59:53 -0700 | [diff] [blame] | 4305 | ni_writeb(dev, loadbit, NI_E_SERIAL_CMD_REG); |
H Hartley Sweeten | 62c2bce | 2014-05-28 16:26:28 -0700 | [diff] [blame] | 4306 | udelay(1); |
H Hartley Sweeten | 2ed183f | 2015-05-01 14:59:53 -0700 | [diff] [blame] | 4307 | ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG); |
H Hartley Sweeten | 62c2bce | 2014-05-28 16:26:28 -0700 | [diff] [blame] | 4308 | } |
| 4309 | |
| 4310 | static int ni_calib_insn_write(struct comedi_device *dev, |
| 4311 | struct comedi_subdevice *s, |
| 4312 | struct comedi_insn *insn, |
| 4313 | unsigned int *data) |
| 4314 | { |
| 4315 | ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]); |
| 4316 | |
| 4317 | return 1; |
| 4318 | } |
| 4319 | |
| 4320 | static int ni_calib_insn_read(struct comedi_device *dev, |
| 4321 | struct comedi_subdevice *s, |
| 4322 | struct comedi_insn *insn, |
| 4323 | unsigned int *data) |
| 4324 | { |
| 4325 | struct ni_private *devpriv = dev->private; |
| 4326 | |
| 4327 | data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)]; |
| 4328 | |
| 4329 | return 1; |
| 4330 | } |
| 4331 | |
| 4332 | static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s) |
| 4333 | { |
Ian Abbott | 7cf94ad | 2014-09-09 11:26:44 +0100 | [diff] [blame] | 4334 | const struct ni_board_struct *board = dev->board_ptr; |
H Hartley Sweeten | 62c2bce | 2014-05-28 16:26:28 -0700 | [diff] [blame] | 4335 | struct ni_private *devpriv = dev->private; |
| 4336 | int i, j; |
| 4337 | int n_dacs; |
| 4338 | int n_chans = 0; |
| 4339 | int n_bits; |
| 4340 | int diffbits = 0; |
| 4341 | int type; |
| 4342 | int chan; |
| 4343 | |
| 4344 | type = board->caldac[0]; |
| 4345 | if (type == caldac_none) |
| 4346 | return; |
| 4347 | n_bits = caldacs[type].n_bits; |
| 4348 | for (i = 0; i < 3; i++) { |
| 4349 | type = board->caldac[i]; |
| 4350 | if (type == caldac_none) |
| 4351 | break; |
| 4352 | if (caldacs[type].n_bits != n_bits) |
| 4353 | diffbits = 1; |
| 4354 | n_chans += caldacs[type].n_chans; |
| 4355 | } |
| 4356 | n_dacs = i; |
| 4357 | s->n_chan = n_chans; |
| 4358 | |
| 4359 | if (diffbits) { |
H Hartley Sweeten | beb1cc1 | 2016-04-14 09:57:57 -0700 | [diff] [blame] | 4360 | unsigned int *maxdata_list = devpriv->caldac_maxdata_list; |
H Hartley Sweeten | 62c2bce | 2014-05-28 16:26:28 -0700 | [diff] [blame] | 4361 | |
| 4362 | if (n_chans > MAX_N_CALDACS) |
H Hartley Sweeten | 89c4695e | 2014-07-18 13:29:52 -0700 | [diff] [blame] | 4363 | dev_err(dev->class_dev, |
| 4364 | "BUG! MAX_N_CALDACS too small\n"); |
H Hartley Sweeten | beb1cc1 | 2016-04-14 09:57:57 -0700 | [diff] [blame] | 4365 | s->maxdata_list = maxdata_list; |
H Hartley Sweeten | 62c2bce | 2014-05-28 16:26:28 -0700 | [diff] [blame] | 4366 | chan = 0; |
| 4367 | for (i = 0; i < n_dacs; i++) { |
| 4368 | type = board->caldac[i]; |
| 4369 | for (j = 0; j < caldacs[type].n_chans; j++) { |
| 4370 | maxdata_list[chan] = |
| 4371 | (1 << caldacs[type].n_bits) - 1; |
| 4372 | chan++; |
| 4373 | } |
| 4374 | } |
| 4375 | |
| 4376 | for (chan = 0; chan < s->n_chan; chan++) |
| 4377 | ni_write_caldac(dev, i, s->maxdata_list[i] / 2); |
| 4378 | } else { |
| 4379 | type = board->caldac[0]; |
| 4380 | s->maxdata = (1 << caldacs[type].n_bits) - 1; |
| 4381 | |
| 4382 | for (chan = 0; chan < s->n_chan; chan++) |
| 4383 | ni_write_caldac(dev, i, s->maxdata / 2); |
| 4384 | } |
| 4385 | } |
| 4386 | |
H Hartley Sweeten | 36adeee | 2014-05-28 16:26:25 -0700 | [diff] [blame] | 4387 | static int ni_read_eeprom(struct comedi_device *dev, int addr) |
| 4388 | { |
H Hartley Sweeten | 2ed183f | 2015-05-01 14:59:53 -0700 | [diff] [blame] | 4389 | unsigned int cmd = NI_E_SERIAL_CMD_EEPROM_CS; |
H Hartley Sweeten | 36adeee | 2014-05-28 16:26:25 -0700 | [diff] [blame] | 4390 | int bit; |
| 4391 | int bitstring; |
| 4392 | |
| 4393 | bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff); |
H Hartley Sweeten | 2ed183f | 2015-05-01 14:59:53 -0700 | [diff] [blame] | 4394 | ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG); |
H Hartley Sweeten | 36adeee | 2014-05-28 16:26:25 -0700 | [diff] [blame] | 4395 | for (bit = 0x8000; bit; bit >>= 1) { |
H Hartley Sweeten | 2ed183f | 2015-05-01 14:59:53 -0700 | [diff] [blame] | 4396 | if (bit & bitstring) |
| 4397 | cmd |= NI_E_SERIAL_CMD_SDATA; |
| 4398 | else |
| 4399 | cmd &= ~NI_E_SERIAL_CMD_SDATA; |
| 4400 | |
| 4401 | ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG); |
| 4402 | ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG); |
H Hartley Sweeten | 36adeee | 2014-05-28 16:26:25 -0700 | [diff] [blame] | 4403 | } |
H Hartley Sweeten | 2ed183f | 2015-05-01 14:59:53 -0700 | [diff] [blame] | 4404 | cmd = NI_E_SERIAL_CMD_EEPROM_CS; |
H Hartley Sweeten | 36adeee | 2014-05-28 16:26:25 -0700 | [diff] [blame] | 4405 | bitstring = 0; |
| 4406 | for (bit = 0x80; bit; bit >>= 1) { |
H Hartley Sweeten | 2ed183f | 2015-05-01 14:59:53 -0700 | [diff] [blame] | 4407 | ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG); |
| 4408 | ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG); |
H Hartley Sweeten | 906170b | 2015-05-01 14:59:52 -0700 | [diff] [blame] | 4409 | if (ni_readb(dev, NI_E_STATUS_REG) & NI_E_STATUS_PROMOUT) |
| 4410 | bitstring |= bit; |
H Hartley Sweeten | 36adeee | 2014-05-28 16:26:25 -0700 | [diff] [blame] | 4411 | } |
H Hartley Sweeten | 2ed183f | 2015-05-01 14:59:53 -0700 | [diff] [blame] | 4412 | ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG); |
H Hartley Sweeten | 36adeee | 2014-05-28 16:26:25 -0700 | [diff] [blame] | 4413 | |
| 4414 | return bitstring; |
| 4415 | } |
| 4416 | |
| 4417 | static int ni_eeprom_insn_read(struct comedi_device *dev, |
| 4418 | struct comedi_subdevice *s, |
| 4419 | struct comedi_insn *insn, |
| 4420 | unsigned int *data) |
| 4421 | { |
| 4422 | data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec)); |
| 4423 | |
| 4424 | return 1; |
| 4425 | } |
| 4426 | |
| 4427 | static int ni_m_series_eeprom_insn_read(struct comedi_device *dev, |
| 4428 | struct comedi_subdevice *s, |
| 4429 | struct comedi_insn *insn, |
| 4430 | unsigned int *data) |
| 4431 | { |
| 4432 | struct ni_private *devpriv = dev->private; |
| 4433 | |
| 4434 | data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)]; |
| 4435 | |
| 4436 | return 1; |
| 4437 | } |
| 4438 | |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 4439 | static unsigned int ni_old_get_pfi_routing(struct comedi_device *dev, |
| 4440 | unsigned int chan) |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4441 | { |
| 4442 | /* pre-m-series boards have fixed signals on pfi pins */ |
| 4443 | switch (chan) { |
| 4444 | case 0: |
| 4445 | return NI_PFI_OUTPUT_AI_START1; |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4446 | case 1: |
| 4447 | return NI_PFI_OUTPUT_AI_START2; |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4448 | case 2: |
| 4449 | return NI_PFI_OUTPUT_AI_CONVERT; |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4450 | case 3: |
| 4451 | return NI_PFI_OUTPUT_G_SRC1; |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4452 | case 4: |
| 4453 | return NI_PFI_OUTPUT_G_GATE1; |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4454 | case 5: |
| 4455 | return NI_PFI_OUTPUT_AO_UPDATE_N; |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4456 | case 6: |
| 4457 | return NI_PFI_OUTPUT_AO_START1; |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4458 | case 7: |
| 4459 | return NI_PFI_OUTPUT_AI_START_PULSE; |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4460 | case 8: |
| 4461 | return NI_PFI_OUTPUT_G_SRC0; |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4462 | case 9: |
| 4463 | return NI_PFI_OUTPUT_G_GATE0; |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4464 | default: |
Haneen Mohammed | cd25503 | 2015-03-05 13:01:49 +0300 | [diff] [blame] | 4465 | dev_err(dev->class_dev, "bug, unhandled case in switch.\n"); |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4466 | break; |
| 4467 | } |
| 4468 | return 0; |
| 4469 | } |
| 4470 | |
| 4471 | static int ni_old_set_pfi_routing(struct comedi_device *dev, |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 4472 | unsigned int chan, unsigned int source) |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4473 | { |
| 4474 | /* pre-m-series boards have fixed signals on pfi pins */ |
| 4475 | if (source != ni_old_get_pfi_routing(dev, chan)) |
| 4476 | return -EINVAL; |
| 4477 | return 2; |
| 4478 | } |
| 4479 | |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 4480 | static unsigned int ni_m_series_get_pfi_routing(struct comedi_device *dev, |
| 4481 | unsigned int chan) |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4482 | { |
| 4483 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 4484 | const unsigned int array_offset = chan / 3; |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4485 | |
H Hartley Sweeten | 43e9d88 | 2015-05-01 14:58:43 -0700 | [diff] [blame] | 4486 | return NI_M_PFI_OUT_SEL_TO_SRC(chan, |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4487 | devpriv->pfi_output_select_reg[array_offset]); |
| 4488 | } |
| 4489 | |
| 4490 | static int ni_m_series_set_pfi_routing(struct comedi_device *dev, |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 4491 | unsigned int chan, unsigned int source) |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4492 | { |
| 4493 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 4494 | unsigned int index = chan / 3; |
H Hartley Sweeten | e0852f6 | 2015-05-01 14:58:30 -0700 | [diff] [blame] | 4495 | unsigned short val = devpriv->pfi_output_select_reg[index]; |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4496 | |
| 4497 | if ((source & 0x1f) != source) |
| 4498 | return -EINVAL; |
H Hartley Sweeten | e0852f6 | 2015-05-01 14:58:30 -0700 | [diff] [blame] | 4499 | |
H Hartley Sweeten | 43e9d88 | 2015-05-01 14:58:43 -0700 | [diff] [blame] | 4500 | val &= ~NI_M_PFI_OUT_SEL_MASK(chan); |
| 4501 | val |= NI_M_PFI_OUT_SEL(chan, source); |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 4502 | ni_writew(dev, val, NI_M_PFI_OUT_SEL_REG(index)); |
H Hartley Sweeten | e0852f6 | 2015-05-01 14:58:30 -0700 | [diff] [blame] | 4503 | devpriv->pfi_output_select_reg[index] = val; |
| 4504 | |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4505 | return 2; |
| 4506 | } |
| 4507 | |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 4508 | static unsigned int ni_get_pfi_routing(struct comedi_device *dev, |
| 4509 | unsigned int chan) |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4510 | { |
H Hartley Sweeten | 1773321 | 2014-06-19 10:20:32 -0700 | [diff] [blame] | 4511 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4512 | |
H Hartley Sweeten | 0953ee4 | 2014-07-16 10:43:34 -0700 | [diff] [blame] | 4513 | return (devpriv->is_m_series) |
| 4514 | ? ni_m_series_get_pfi_routing(dev, chan) |
| 4515 | : ni_old_get_pfi_routing(dev, chan); |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4516 | } |
| 4517 | |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 4518 | static int ni_set_pfi_routing(struct comedi_device *dev, |
| 4519 | unsigned int chan, unsigned int source) |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4520 | { |
H Hartley Sweeten | 1773321 | 2014-06-19 10:20:32 -0700 | [diff] [blame] | 4521 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4522 | |
H Hartley Sweeten | 0953ee4 | 2014-07-16 10:43:34 -0700 | [diff] [blame] | 4523 | return (devpriv->is_m_series) |
| 4524 | ? ni_m_series_set_pfi_routing(dev, chan, source) |
| 4525 | : ni_old_set_pfi_routing(dev, chan, source); |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4526 | } |
| 4527 | |
| 4528 | static int ni_config_filter(struct comedi_device *dev, |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 4529 | unsigned int pfi_channel, |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4530 | enum ni_pfi_filter_select filter) |
| 4531 | { |
H Hartley Sweeten | 9c340ac | 2014-05-29 10:56:32 -0700 | [diff] [blame] | 4532 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 4533 | unsigned int bits; |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4534 | |
H Hartley Sweeten | 1773321 | 2014-06-19 10:20:32 -0700 | [diff] [blame] | 4535 | if (!devpriv->is_m_series) |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4536 | return -ENOTSUPP; |
H Hartley Sweeten | 1773321 | 2014-06-19 10:20:32 -0700 | [diff] [blame] | 4537 | |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 4538 | bits = ni_readl(dev, NI_M_PFI_FILTER_REG); |
H Hartley Sweeten | 0dee7ec | 2015-05-01 14:58:44 -0700 | [diff] [blame] | 4539 | bits &= ~NI_M_PFI_FILTER_SEL_MASK(pfi_channel); |
| 4540 | bits |= NI_M_PFI_FILTER_SEL(pfi_channel, filter); |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 4541 | ni_writel(dev, bits, NI_M_PFI_FILTER_REG); |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4542 | return 0; |
| 4543 | } |
| 4544 | |
| 4545 | static int ni_pfi_insn_config(struct comedi_device *dev, |
| 4546 | struct comedi_subdevice *s, |
| 4547 | struct comedi_insn *insn, |
| 4548 | unsigned int *data) |
| 4549 | { |
| 4550 | struct ni_private *devpriv = dev->private; |
| 4551 | unsigned int chan; |
| 4552 | |
| 4553 | if (insn->n < 1) |
| 4554 | return -EINVAL; |
| 4555 | |
| 4556 | chan = CR_CHAN(insn->chanspec); |
| 4557 | |
| 4558 | switch (data[0]) { |
| 4559 | case COMEDI_OUTPUT: |
H Hartley Sweeten | 5ecadf8 | 2015-05-01 14:59:12 -0700 | [diff] [blame] | 4560 | ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 1); |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4561 | break; |
| 4562 | case COMEDI_INPUT: |
H Hartley Sweeten | 5ecadf8 | 2015-05-01 14:59:12 -0700 | [diff] [blame] | 4563 | ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 0); |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4564 | break; |
| 4565 | case INSN_CONFIG_DIO_QUERY: |
| 4566 | data[1] = |
| 4567 | (devpriv->io_bidirection_pin_reg & (1 << chan)) ? |
| 4568 | COMEDI_OUTPUT : COMEDI_INPUT; |
| 4569 | return 0; |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4570 | case INSN_CONFIG_SET_ROUTING: |
| 4571 | return ni_set_pfi_routing(dev, chan, data[1]); |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4572 | case INSN_CONFIG_GET_ROUTING: |
| 4573 | data[1] = ni_get_pfi_routing(dev, chan); |
| 4574 | break; |
| 4575 | case INSN_CONFIG_FILTER: |
| 4576 | return ni_config_filter(dev, chan, data[1]); |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4577 | default: |
| 4578 | return -EINVAL; |
| 4579 | } |
| 4580 | return 0; |
| 4581 | } |
| 4582 | |
| 4583 | static int ni_pfi_insn_bits(struct comedi_device *dev, |
| 4584 | struct comedi_subdevice *s, |
| 4585 | struct comedi_insn *insn, |
| 4586 | unsigned int *data) |
| 4587 | { |
H Hartley Sweeten | 9c340ac | 2014-05-29 10:56:32 -0700 | [diff] [blame] | 4588 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4589 | |
H Hartley Sweeten | 1773321 | 2014-06-19 10:20:32 -0700 | [diff] [blame] | 4590 | if (!devpriv->is_m_series) |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4591 | return -ENOTSUPP; |
| 4592 | |
| 4593 | if (comedi_dio_update_state(s, data)) |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 4594 | ni_writew(dev, s->state, NI_M_PFI_DO_REG); |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4595 | |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 4596 | data[1] = ni_readw(dev, NI_M_PFI_DI_REG); |
H Hartley Sweeten | 4187a79 | 2014-05-28 16:26:30 -0700 | [diff] [blame] | 4597 | |
| 4598 | return insn->n; |
| 4599 | } |
| 4600 | |
H Hartley Sweeten | 24e7c35 | 2014-05-28 16:26:31 -0700 | [diff] [blame] | 4601 | static int cs5529_wait_for_idle(struct comedi_device *dev) |
| 4602 | { |
| 4603 | unsigned short status; |
| 4604 | const int timeout = HZ; |
| 4605 | int i; |
| 4606 | |
| 4607 | for (i = 0; i < timeout; i++) { |
H Hartley Sweeten | ef39154 | 2015-05-01 15:00:11 -0700 | [diff] [blame] | 4608 | status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG); |
| 4609 | if ((status & NI67XX_CAL_STATUS_BUSY) == 0) |
H Hartley Sweeten | 24e7c35 | 2014-05-28 16:26:31 -0700 | [diff] [blame] | 4610 | break; |
| 4611 | set_current_state(TASK_INTERRUPTIBLE); |
| 4612 | if (schedule_timeout(1)) |
| 4613 | return -EIO; |
| 4614 | } |
H Hartley Sweeten | 24e7c35 | 2014-05-28 16:26:31 -0700 | [diff] [blame] | 4615 | if (i == timeout) { |
Haneen Mohammed | cd25503 | 2015-03-05 13:01:49 +0300 | [diff] [blame] | 4616 | dev_err(dev->class_dev, "timeout\n"); |
H Hartley Sweeten | 24e7c35 | 2014-05-28 16:26:31 -0700 | [diff] [blame] | 4617 | return -ETIME; |
| 4618 | } |
| 4619 | return 0; |
| 4620 | } |
| 4621 | |
| 4622 | static void cs5529_command(struct comedi_device *dev, unsigned short value) |
| 4623 | { |
| 4624 | static const int timeout = 100; |
| 4625 | int i; |
| 4626 | |
H Hartley Sweeten | ef39154 | 2015-05-01 15:00:11 -0700 | [diff] [blame] | 4627 | ni_ao_win_outw(dev, value, NI67XX_CAL_CMD_REG); |
H Hartley Sweeten | 24e7c35 | 2014-05-28 16:26:31 -0700 | [diff] [blame] | 4628 | /* give time for command to start being serially clocked into cs5529. |
H Hartley Sweeten | ef39154 | 2015-05-01 15:00:11 -0700 | [diff] [blame] | 4629 | * this insures that the NI67XX_CAL_STATUS_BUSY bit will get properly |
H Hartley Sweeten | 24e7c35 | 2014-05-28 16:26:31 -0700 | [diff] [blame] | 4630 | * set before we exit this function. |
| 4631 | */ |
| 4632 | for (i = 0; i < timeout; i++) { |
H Hartley Sweeten | ef39154 | 2015-05-01 15:00:11 -0700 | [diff] [blame] | 4633 | if (ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG) & |
| 4634 | NI67XX_CAL_STATUS_BUSY) |
H Hartley Sweeten | 24e7c35 | 2014-05-28 16:26:31 -0700 | [diff] [blame] | 4635 | break; |
| 4636 | udelay(1); |
| 4637 | } |
H Hartley Sweeten | 24e7c35 | 2014-05-28 16:26:31 -0700 | [diff] [blame] | 4638 | if (i == timeout) |
H Hartley Sweeten | 5ac1d82 | 2014-07-17 11:57:33 -0700 | [diff] [blame] | 4639 | dev_err(dev->class_dev, |
| 4640 | "possible problem - never saw adc go busy?\n"); |
H Hartley Sweeten | 24e7c35 | 2014-05-28 16:26:31 -0700 | [diff] [blame] | 4641 | } |
| 4642 | |
| 4643 | static int cs5529_do_conversion(struct comedi_device *dev, |
| 4644 | unsigned short *data) |
| 4645 | { |
| 4646 | int retval; |
| 4647 | unsigned short status; |
| 4648 | |
H Hartley Sweeten | 94f0cbb | 2015-05-01 15:00:10 -0700 | [diff] [blame] | 4649 | cs5529_command(dev, CS5529_CMD_CB | CS5529_CMD_SINGLE_CONV); |
H Hartley Sweeten | 24e7c35 | 2014-05-28 16:26:31 -0700 | [diff] [blame] | 4650 | retval = cs5529_wait_for_idle(dev); |
| 4651 | if (retval) { |
H Hartley Sweeten | 5ac1d82 | 2014-07-17 11:57:33 -0700 | [diff] [blame] | 4652 | dev_err(dev->class_dev, |
| 4653 | "timeout or signal in cs5529_do_conversion()\n"); |
H Hartley Sweeten | 24e7c35 | 2014-05-28 16:26:31 -0700 | [diff] [blame] | 4654 | return -ETIME; |
| 4655 | } |
H Hartley Sweeten | ef39154 | 2015-05-01 15:00:11 -0700 | [diff] [blame] | 4656 | status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG); |
| 4657 | if (status & NI67XX_CAL_STATUS_OSC_DETECT) { |
H Hartley Sweeten | 89c4695e | 2014-07-18 13:29:52 -0700 | [diff] [blame] | 4658 | dev_err(dev->class_dev, |
| 4659 | "cs5529 conversion error, status CSS_OSC_DETECT\n"); |
H Hartley Sweeten | 24e7c35 | 2014-05-28 16:26:31 -0700 | [diff] [blame] | 4660 | return -EIO; |
| 4661 | } |
H Hartley Sweeten | ef39154 | 2015-05-01 15:00:11 -0700 | [diff] [blame] | 4662 | if (status & NI67XX_CAL_STATUS_OVERRANGE) { |
H Hartley Sweeten | 89c4695e | 2014-07-18 13:29:52 -0700 | [diff] [blame] | 4663 | dev_err(dev->class_dev, |
| 4664 | "cs5529 conversion error, overrange (ignoring)\n"); |
H Hartley Sweeten | 24e7c35 | 2014-05-28 16:26:31 -0700 | [diff] [blame] | 4665 | } |
| 4666 | if (data) { |
H Hartley Sweeten | ef39154 | 2015-05-01 15:00:11 -0700 | [diff] [blame] | 4667 | *data = ni_ao_win_inw(dev, NI67XX_CAL_DATA_REG); |
H Hartley Sweeten | 24e7c35 | 2014-05-28 16:26:31 -0700 | [diff] [blame] | 4668 | /* cs5529 returns 16 bit signed data in bipolar mode */ |
| 4669 | *data ^= (1 << 15); |
| 4670 | } |
| 4671 | return 0; |
| 4672 | } |
| 4673 | |
| 4674 | static int cs5529_ai_insn_read(struct comedi_device *dev, |
| 4675 | struct comedi_subdevice *s, |
| 4676 | struct comedi_insn *insn, |
| 4677 | unsigned int *data) |
| 4678 | { |
| 4679 | int n, retval; |
| 4680 | unsigned short sample; |
| 4681 | unsigned int channel_select; |
| 4682 | const unsigned int INTERNAL_REF = 0x1000; |
| 4683 | |
H Hartley Sweeten | bd474a0 | 2016-04-14 09:57:55 -0700 | [diff] [blame] | 4684 | /* |
| 4685 | * Set calibration adc source. Docs lie, reference select bits 8 to 11 |
H Hartley Sweeten | 24e7c35 | 2014-05-28 16:26:31 -0700 | [diff] [blame] | 4686 | * do nothing. bit 12 seems to chooses internal reference voltage, bit |
H Hartley Sweeten | bd474a0 | 2016-04-14 09:57:55 -0700 | [diff] [blame] | 4687 | * 13 causes the adc input to go overrange (maybe reads external |
| 4688 | * reference?) |
| 4689 | */ |
H Hartley Sweeten | 24e7c35 | 2014-05-28 16:26:31 -0700 | [diff] [blame] | 4690 | if (insn->chanspec & CR_ALT_SOURCE) |
| 4691 | channel_select = INTERNAL_REF; |
| 4692 | else |
| 4693 | channel_select = CR_CHAN(insn->chanspec); |
H Hartley Sweeten | ef39154 | 2015-05-01 15:00:11 -0700 | [diff] [blame] | 4694 | ni_ao_win_outw(dev, channel_select, NI67XX_AO_CAL_CHAN_SEL_REG); |
H Hartley Sweeten | 24e7c35 | 2014-05-28 16:26:31 -0700 | [diff] [blame] | 4695 | |
| 4696 | for (n = 0; n < insn->n; n++) { |
| 4697 | retval = cs5529_do_conversion(dev, &sample); |
| 4698 | if (retval < 0) |
| 4699 | return retval; |
| 4700 | data[n] = sample; |
| 4701 | } |
| 4702 | return insn->n; |
| 4703 | } |
| 4704 | |
| 4705 | static void cs5529_config_write(struct comedi_device *dev, unsigned int value, |
| 4706 | unsigned int reg_select_bits) |
| 4707 | { |
H Hartley Sweeten | ef39154 | 2015-05-01 15:00:11 -0700 | [diff] [blame] | 4708 | ni_ao_win_outw(dev, (value >> 16) & 0xff, NI67XX_CAL_CFG_HI_REG); |
| 4709 | ni_ao_win_outw(dev, value & 0xffff, NI67XX_CAL_CFG_LO_REG); |
H Hartley Sweeten | 94f0cbb | 2015-05-01 15:00:10 -0700 | [diff] [blame] | 4710 | reg_select_bits &= CS5529_CMD_REG_MASK; |
| 4711 | cs5529_command(dev, CS5529_CMD_CB | reg_select_bits); |
H Hartley Sweeten | 24e7c35 | 2014-05-28 16:26:31 -0700 | [diff] [blame] | 4712 | if (cs5529_wait_for_idle(dev)) |
H Hartley Sweeten | 5ac1d82 | 2014-07-17 11:57:33 -0700 | [diff] [blame] | 4713 | dev_err(dev->class_dev, |
| 4714 | "timeout or signal in %s\n", __func__); |
H Hartley Sweeten | 24e7c35 | 2014-05-28 16:26:31 -0700 | [diff] [blame] | 4715 | } |
| 4716 | |
| 4717 | static int init_cs5529(struct comedi_device *dev) |
| 4718 | { |
H Hartley Sweeten | b738aa3 | 2015-05-01 15:00:09 -0700 | [diff] [blame] | 4719 | unsigned int config_bits = CS5529_CFG_PORT_FLAG | |
| 4720 | CS5529_CFG_WORD_RATE_2180; |
H Hartley Sweeten | 24e7c35 | 2014-05-28 16:26:31 -0700 | [diff] [blame] | 4721 | |
| 4722 | #if 1 |
| 4723 | /* do self-calibration */ |
H Hartley Sweeten | b738aa3 | 2015-05-01 15:00:09 -0700 | [diff] [blame] | 4724 | cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_BOTH_SELF, |
H Hartley Sweeten | 94f0cbb | 2015-05-01 15:00:10 -0700 | [diff] [blame] | 4725 | CS5529_CFG_REG); |
H Hartley Sweeten | 24e7c35 | 2014-05-28 16:26:31 -0700 | [diff] [blame] | 4726 | /* need to force a conversion for calibration to run */ |
| 4727 | cs5529_do_conversion(dev, NULL); |
| 4728 | #else |
| 4729 | /* force gain calibration to 1 */ |
H Hartley Sweeten | 94f0cbb | 2015-05-01 15:00:10 -0700 | [diff] [blame] | 4730 | cs5529_config_write(dev, 0x400000, CS5529_GAIN_REG); |
H Hartley Sweeten | b738aa3 | 2015-05-01 15:00:09 -0700 | [diff] [blame] | 4731 | cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_OFFSET_SELF, |
H Hartley Sweeten | 94f0cbb | 2015-05-01 15:00:10 -0700 | [diff] [blame] | 4732 | CS5529_CFG_REG); |
H Hartley Sweeten | 24e7c35 | 2014-05-28 16:26:31 -0700 | [diff] [blame] | 4733 | if (cs5529_wait_for_idle(dev)) |
H Hartley Sweeten | 5ac1d82 | 2014-07-17 11:57:33 -0700 | [diff] [blame] | 4734 | dev_err(dev->class_dev, |
| 4735 | "timeout or signal in %s\n", __func__); |
H Hartley Sweeten | 24e7c35 | 2014-05-28 16:26:31 -0700 | [diff] [blame] | 4736 | #endif |
| 4737 | return 0; |
| 4738 | } |
| 4739 | |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4740 | /* |
| 4741 | * Find best multiplier/divider to try and get the PLL running at 80 MHz |
| 4742 | * given an arbitrary frequency input clock. |
| 4743 | */ |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 4744 | static int ni_mseries_get_pll_parameters(unsigned int reference_period_ns, |
| 4745 | unsigned int *freq_divider, |
| 4746 | unsigned int *freq_multiplier, |
| 4747 | unsigned int *actual_period_ns) |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4748 | { |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 4749 | unsigned int div; |
| 4750 | unsigned int best_div = 1; |
| 4751 | unsigned int mult; |
| 4752 | unsigned int best_mult = 1; |
| 4753 | static const unsigned int pico_per_nano = 1000; |
| 4754 | const unsigned int reference_picosec = reference_period_ns * |
| 4755 | pico_per_nano; |
H Hartley Sweeten | bd474a0 | 2016-04-14 09:57:55 -0700 | [diff] [blame] | 4756 | /* |
| 4757 | * m-series wants the phased-locked loop to output 80MHz, which is |
| 4758 | * divided by 4 to 20 MHz for most timing clocks |
| 4759 | */ |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 4760 | static const unsigned int target_picosec = 12500; |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4761 | int best_period_picosec = 0; |
H Hartley Sweeten | f740197 | 2014-07-16 11:02:08 -0700 | [diff] [blame] | 4762 | |
H Hartley Sweeten | b965e6a | 2015-05-01 14:58:37 -0700 | [diff] [blame] | 4763 | for (div = 1; div <= NI_M_PLL_MAX_DIVISOR; ++div) { |
| 4764 | for (mult = 1; mult <= NI_M_PLL_MAX_MULTIPLIER; ++mult) { |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 4765 | unsigned int new_period_ps = |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4766 | (reference_picosec * div) / mult; |
| 4767 | if (abs(new_period_ps - target_picosec) < |
| 4768 | abs(best_period_picosec - target_picosec)) { |
| 4769 | best_period_picosec = new_period_ps; |
| 4770 | best_div = div; |
| 4771 | best_mult = mult; |
| 4772 | } |
| 4773 | } |
| 4774 | } |
H Hartley Sweeten | 07e6b2e | 2014-07-18 13:29:53 -0700 | [diff] [blame] | 4775 | if (best_period_picosec == 0) |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4776 | return -EIO; |
H Hartley Sweeten | 07e6b2e | 2014-07-18 13:29:53 -0700 | [diff] [blame] | 4777 | |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4778 | *freq_divider = best_div; |
| 4779 | *freq_multiplier = best_mult; |
H Hartley Sweeten | 68556ff | 2016-04-14 09:58:04 -0700 | [diff] [blame] | 4780 | /* return the actual period (* fudge factor for 80 to 20 MHz) */ |
| 4781 | *actual_period_ns = DIV_ROUND_CLOSEST(best_period_picosec * 4, |
Bhaktipriya Shridhar | 1e5a05d | 2016-02-21 16:13:01 +0530 | [diff] [blame] | 4782 | pico_per_nano); |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4783 | return 0; |
| 4784 | } |
| 4785 | |
| 4786 | static int ni_mseries_set_pll_master_clock(struct comedi_device *dev, |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 4787 | unsigned int source, |
| 4788 | unsigned int period_ns) |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4789 | { |
| 4790 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 4791 | static const unsigned int min_period_ns = 50; |
| 4792 | static const unsigned int max_period_ns = 1000; |
| 4793 | static const unsigned int timeout = 1000; |
| 4794 | unsigned int pll_control_bits; |
| 4795 | unsigned int freq_divider; |
| 4796 | unsigned int freq_multiplier; |
| 4797 | unsigned int rtsi; |
| 4798 | unsigned int i; |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4799 | int retval; |
| 4800 | |
| 4801 | if (source == NI_MIO_PLL_PXI10_CLOCK) |
| 4802 | period_ns = 100; |
H Hartley Sweeten | b6a0e5b | 2016-04-14 09:57:56 -0700 | [diff] [blame] | 4803 | /* |
| 4804 | * These limits are somewhat arbitrary, but NI advertises 1 to 20MHz |
| 4805 | * range so we'll use that. |
| 4806 | */ |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4807 | if (period_ns < min_period_ns || period_ns > max_period_ns) { |
H Hartley Sweeten | 89c4695e | 2014-07-18 13:29:52 -0700 | [diff] [blame] | 4808 | dev_err(dev->class_dev, |
| 4809 | "%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\n", |
| 4810 | __func__, min_period_ns, max_period_ns); |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4811 | return -EINVAL; |
| 4812 | } |
H Hartley Sweeten | a4f18b1 | 2015-05-01 14:59:14 -0700 | [diff] [blame] | 4813 | devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK; |
H Hartley Sweeten | 00b14b1 | 2014-06-19 10:20:34 -0700 | [diff] [blame] | 4814 | ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg, |
H Hartley Sweeten | a4f18b1 | 2015-05-01 14:59:14 -0700 | [diff] [blame] | 4815 | NISTC_RTSI_TRIG_DIR_REG); |
H Hartley Sweeten | b965e6a | 2015-05-01 14:58:37 -0700 | [diff] [blame] | 4816 | pll_control_bits = NI_M_PLL_CTRL_ENA | NI_M_PLL_CTRL_VCO_MODE_75_150MHZ; |
H Hartley Sweeten | 40aafd7 | 2015-05-01 14:58:36 -0700 | [diff] [blame] | 4817 | devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_TIMEBASE1_PLL | |
| 4818 | NI_M_CLK_FOUT2_TIMEBASE3_PLL; |
| 4819 | devpriv->clock_and_fout2 &= ~NI_M_CLK_FOUT2_PLL_SRC_MASK; |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4820 | switch (source) { |
| 4821 | case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK: |
H Hartley Sweeten | 40aafd7 | 2015-05-01 14:58:36 -0700 | [diff] [blame] | 4822 | devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_STAR; |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4823 | break; |
| 4824 | case NI_MIO_PLL_PXI10_CLOCK: |
| 4825 | /* pxi clock is 10MHz */ |
H Hartley Sweeten | 40aafd7 | 2015-05-01 14:58:36 -0700 | [diff] [blame] | 4826 | devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_PXI10; |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4827 | break; |
| 4828 | default: |
H Hartley Sweeten | 40aafd7 | 2015-05-01 14:58:36 -0700 | [diff] [blame] | 4829 | for (rtsi = 0; rtsi <= NI_M_MAX_RTSI_CHAN; ++rtsi) { |
| 4830 | if (source == NI_MIO_PLL_RTSI_CLOCK(rtsi)) { |
| 4831 | devpriv->clock_and_fout2 |= |
| 4832 | NI_M_CLK_FOUT2_PLL_SRC_RTSI(rtsi); |
| 4833 | break; |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4834 | } |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4835 | } |
H Hartley Sweeten | 40aafd7 | 2015-05-01 14:58:36 -0700 | [diff] [blame] | 4836 | if (rtsi > NI_M_MAX_RTSI_CHAN) |
| 4837 | return -EINVAL; |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4838 | break; |
| 4839 | } |
H Hartley Sweeten | 07e6b2e | 2014-07-18 13:29:53 -0700 | [diff] [blame] | 4840 | retval = ni_mseries_get_pll_parameters(period_ns, |
| 4841 | &freq_divider, |
| 4842 | &freq_multiplier, |
| 4843 | &devpriv->clock_ns); |
| 4844 | if (retval < 0) { |
| 4845 | dev_err(dev->class_dev, |
Haneen Mohammed | cd25503 | 2015-03-05 13:01:49 +0300 | [diff] [blame] | 4846 | "bug, failed to find pll parameters\n"); |
H Hartley Sweeten | 07e6b2e | 2014-07-18 13:29:53 -0700 | [diff] [blame] | 4847 | return retval; |
| 4848 | } |
| 4849 | |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 4850 | ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG); |
H Hartley Sweeten | b965e6a | 2015-05-01 14:58:37 -0700 | [diff] [blame] | 4851 | pll_control_bits |= NI_M_PLL_CTRL_DIVISOR(freq_divider) | |
| 4852 | NI_M_PLL_CTRL_MULTIPLIER(freq_multiplier); |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4853 | |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 4854 | ni_writew(dev, pll_control_bits, NI_M_PLL_CTRL_REG); |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4855 | devpriv->clock_source = source; |
H Hartley Sweeten | b6a0e5b | 2016-04-14 09:57:56 -0700 | [diff] [blame] | 4856 | /* it takes a few hundred microseconds for PLL to lock */ |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4857 | for (i = 0; i < timeout; ++i) { |
H Hartley Sweeten | b1c7064 | 2015-05-01 14:58:38 -0700 | [diff] [blame] | 4858 | if (ni_readw(dev, NI_M_PLL_STATUS_REG) & NI_M_PLL_STATUS_LOCKED) |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4859 | break; |
| 4860 | udelay(1); |
| 4861 | } |
| 4862 | if (i == timeout) { |
H Hartley Sweeten | 89c4695e | 2014-07-18 13:29:52 -0700 | [diff] [blame] | 4863 | dev_err(dev->class_dev, |
| 4864 | "%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns\n", |
| 4865 | __func__, source, period_ns); |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4866 | return -ETIMEDOUT; |
| 4867 | } |
| 4868 | return 3; |
| 4869 | } |
| 4870 | |
| 4871 | static int ni_set_master_clock(struct comedi_device *dev, |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 4872 | unsigned int source, unsigned int period_ns) |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4873 | { |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4874 | struct ni_private *devpriv = dev->private; |
| 4875 | |
| 4876 | if (source == NI_MIO_INTERNAL_CLOCK) { |
H Hartley Sweeten | a4f18b1 | 2015-05-01 14:59:14 -0700 | [diff] [blame] | 4877 | devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK; |
H Hartley Sweeten | 00b14b1 | 2014-06-19 10:20:34 -0700 | [diff] [blame] | 4878 | ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg, |
H Hartley Sweeten | a4f18b1 | 2015-05-01 14:59:14 -0700 | [diff] [blame] | 4879 | NISTC_RTSI_TRIG_DIR_REG); |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4880 | devpriv->clock_ns = TIMEBASE_1_NS; |
H Hartley Sweeten | 1773321 | 2014-06-19 10:20:32 -0700 | [diff] [blame] | 4881 | if (devpriv->is_m_series) { |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4882 | devpriv->clock_and_fout2 &= |
H Hartley Sweeten | 40aafd7 | 2015-05-01 14:58:36 -0700 | [diff] [blame] | 4883 | ~(NI_M_CLK_FOUT2_TIMEBASE1_PLL | |
| 4884 | NI_M_CLK_FOUT2_TIMEBASE3_PLL); |
H Hartley Sweeten | 5a92cac | 2014-06-19 10:20:35 -0700 | [diff] [blame] | 4885 | ni_writew(dev, devpriv->clock_and_fout2, |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 4886 | NI_M_CLK_FOUT2_REG); |
| 4887 | ni_writew(dev, 0, NI_M_PLL_CTRL_REG); |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4888 | } |
| 4889 | devpriv->clock_source = source; |
| 4890 | } else { |
H Hartley Sweeten | 1773321 | 2014-06-19 10:20:32 -0700 | [diff] [blame] | 4891 | if (devpriv->is_m_series) { |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4892 | return ni_mseries_set_pll_master_clock(dev, source, |
| 4893 | period_ns); |
| 4894 | } else { |
| 4895 | if (source == NI_MIO_RTSI_CLOCK) { |
| 4896 | devpriv->rtsi_trig_direction_reg |= |
H Hartley Sweeten | a4f18b1 | 2015-05-01 14:59:14 -0700 | [diff] [blame] | 4897 | NISTC_RTSI_TRIG_USE_CLK; |
H Hartley Sweeten | 00b14b1 | 2014-06-19 10:20:34 -0700 | [diff] [blame] | 4898 | ni_stc_writew(dev, |
| 4899 | devpriv->rtsi_trig_direction_reg, |
H Hartley Sweeten | a4f18b1 | 2015-05-01 14:59:14 -0700 | [diff] [blame] | 4900 | NISTC_RTSI_TRIG_DIR_REG); |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4901 | if (period_ns == 0) { |
H Hartley Sweeten | 89c4695e | 2014-07-18 13:29:52 -0700 | [diff] [blame] | 4902 | dev_err(dev->class_dev, |
Haneen Mohammed | cd25503 | 2015-03-05 13:01:49 +0300 | [diff] [blame] | 4903 | "we don't handle an unspecified clock period correctly yet, returning error\n"); |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4904 | return -EINVAL; |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4905 | } |
H Hartley Sweeten | 0953ee4 | 2014-07-16 10:43:34 -0700 | [diff] [blame] | 4906 | devpriv->clock_ns = period_ns; |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4907 | devpriv->clock_source = source; |
H Hartley Sweeten | 6ac986d0 | 2015-03-05 13:21:18 -0700 | [diff] [blame] | 4908 | } else { |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4909 | return -EINVAL; |
H Hartley Sweeten | 6ac986d0 | 2015-03-05 13:21:18 -0700 | [diff] [blame] | 4910 | } |
H Hartley Sweeten | 624b161 | 2014-05-28 16:26:46 -0700 | [diff] [blame] | 4911 | } |
| 4912 | } |
| 4913 | return 3; |
| 4914 | } |
| 4915 | |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 4916 | static int ni_valid_rtsi_output_source(struct comedi_device *dev, |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 4917 | unsigned int chan, unsigned int source) |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 4918 | { |
H Hartley Sweeten | 1773321 | 2014-06-19 10:20:32 -0700 | [diff] [blame] | 4919 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 4920 | |
H Hartley Sweeten | a4f18b1 | 2015-05-01 14:59:14 -0700 | [diff] [blame] | 4921 | if (chan >= NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) { |
| 4922 | if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) { |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 4923 | if (source == NI_RTSI_OUTPUT_RTSI_OSC) |
| 4924 | return 1; |
H Hartley Sweeten | 0953ee4 | 2014-07-16 10:43:34 -0700 | [diff] [blame] | 4925 | |
H Hartley Sweeten | 89c4695e | 2014-07-18 13:29:52 -0700 | [diff] [blame] | 4926 | dev_err(dev->class_dev, |
| 4927 | "%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n", |
H Hartley Sweeten | a4f18b1 | 2015-05-01 14:59:14 -0700 | [diff] [blame] | 4928 | __func__, chan, NISTC_RTSI_TRIG_OLD_CLK_CHAN); |
H Hartley Sweeten | 0953ee4 | 2014-07-16 10:43:34 -0700 | [diff] [blame] | 4929 | return 0; |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 4930 | } |
| 4931 | return 0; |
| 4932 | } |
| 4933 | switch (source) { |
| 4934 | case NI_RTSI_OUTPUT_ADR_START1: |
| 4935 | case NI_RTSI_OUTPUT_ADR_START2: |
| 4936 | case NI_RTSI_OUTPUT_SCLKG: |
| 4937 | case NI_RTSI_OUTPUT_DACUPDN: |
| 4938 | case NI_RTSI_OUTPUT_DA_START1: |
| 4939 | case NI_RTSI_OUTPUT_G_SRC0: |
| 4940 | case NI_RTSI_OUTPUT_G_GATE0: |
| 4941 | case NI_RTSI_OUTPUT_RGOUT0: |
| 4942 | case NI_RTSI_OUTPUT_RTSI_BRD_0: |
| 4943 | return 1; |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 4944 | case NI_RTSI_OUTPUT_RTSI_OSC: |
H Hartley Sweeten | 9594096 | 2014-07-16 10:43:33 -0700 | [diff] [blame] | 4945 | return (devpriv->is_m_series) ? 1 : 0; |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 4946 | default: |
| 4947 | return 0; |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 4948 | } |
| 4949 | } |
| 4950 | |
| 4951 | static int ni_set_rtsi_routing(struct comedi_device *dev, |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 4952 | unsigned int chan, unsigned int src) |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 4953 | { |
| 4954 | struct ni_private *devpriv = dev->private; |
| 4955 | |
H Hartley Sweeten | 390bc6f | 2015-05-01 14:59:32 -0700 | [diff] [blame] | 4956 | if (ni_valid_rtsi_output_source(dev, chan, src) == 0) |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 4957 | return -EINVAL; |
| 4958 | if (chan < 4) { |
H Hartley Sweeten | 390bc6f | 2015-05-01 14:59:32 -0700 | [diff] [blame] | 4959 | devpriv->rtsi_trig_a_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan); |
| 4960 | devpriv->rtsi_trig_a_output_reg |= NISTC_RTSI_TRIG(chan, src); |
H Hartley Sweeten | 00b14b1 | 2014-06-19 10:20:34 -0700 | [diff] [blame] | 4961 | ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg, |
H Hartley Sweeten | 390bc6f | 2015-05-01 14:59:32 -0700 | [diff] [blame] | 4962 | NISTC_RTSI_TRIGA_OUT_REG); |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 4963 | } else if (chan < 8) { |
H Hartley Sweeten | 390bc6f | 2015-05-01 14:59:32 -0700 | [diff] [blame] | 4964 | devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan); |
| 4965 | devpriv->rtsi_trig_b_output_reg |= NISTC_RTSI_TRIG(chan, src); |
H Hartley Sweeten | 00b14b1 | 2014-06-19 10:20:34 -0700 | [diff] [blame] | 4966 | ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg, |
H Hartley Sweeten | 390bc6f | 2015-05-01 14:59:32 -0700 | [diff] [blame] | 4967 | NISTC_RTSI_TRIGB_OUT_REG); |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 4968 | } |
| 4969 | return 2; |
| 4970 | } |
| 4971 | |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 4972 | static unsigned int ni_get_rtsi_routing(struct comedi_device *dev, |
| 4973 | unsigned int chan) |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 4974 | { |
| 4975 | struct ni_private *devpriv = dev->private; |
| 4976 | |
| 4977 | if (chan < 4) { |
H Hartley Sweeten | 390bc6f | 2015-05-01 14:59:32 -0700 | [diff] [blame] | 4978 | return NISTC_RTSI_TRIG_TO_SRC(chan, |
| 4979 | devpriv->rtsi_trig_a_output_reg); |
H Hartley Sweeten | a4f18b1 | 2015-05-01 14:59:14 -0700 | [diff] [blame] | 4980 | } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) { |
H Hartley Sweeten | 390bc6f | 2015-05-01 14:59:32 -0700 | [diff] [blame] | 4981 | return NISTC_RTSI_TRIG_TO_SRC(chan, |
| 4982 | devpriv->rtsi_trig_b_output_reg); |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 4983 | } else { |
H Hartley Sweeten | a4f18b1 | 2015-05-01 14:59:14 -0700 | [diff] [blame] | 4984 | if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 4985 | return NI_RTSI_OUTPUT_RTSI_OSC; |
Haneen Mohammed | cd25503 | 2015-03-05 13:01:49 +0300 | [diff] [blame] | 4986 | dev_err(dev->class_dev, "bug! should never get here?\n"); |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 4987 | return 0; |
| 4988 | } |
| 4989 | } |
| 4990 | |
| 4991 | static int ni_rtsi_insn_config(struct comedi_device *dev, |
| 4992 | struct comedi_subdevice *s, |
| 4993 | struct comedi_insn *insn, |
| 4994 | unsigned int *data) |
| 4995 | { |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 4996 | struct ni_private *devpriv = dev->private; |
| 4997 | unsigned int chan = CR_CHAN(insn->chanspec); |
H Hartley Sweeten | a4f18b1 | 2015-05-01 14:59:14 -0700 | [diff] [blame] | 4998 | unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series); |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 4999 | |
| 5000 | switch (data[0]) { |
| 5001 | case INSN_CONFIG_DIO_OUTPUT: |
H Hartley Sweeten | a4f18b1 | 2015-05-01 14:59:14 -0700 | [diff] [blame] | 5002 | if (chan < max_chan) { |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 5003 | devpriv->rtsi_trig_direction_reg |= |
H Hartley Sweeten | a4f18b1 | 2015-05-01 14:59:14 -0700 | [diff] [blame] | 5004 | NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series); |
| 5005 | } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) { |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 5006 | devpriv->rtsi_trig_direction_reg |= |
H Hartley Sweeten | a4f18b1 | 2015-05-01 14:59:14 -0700 | [diff] [blame] | 5007 | NISTC_RTSI_TRIG_DRV_CLK; |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 5008 | } |
H Hartley Sweeten | 00b14b1 | 2014-06-19 10:20:34 -0700 | [diff] [blame] | 5009 | ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg, |
H Hartley Sweeten | a4f18b1 | 2015-05-01 14:59:14 -0700 | [diff] [blame] | 5010 | NISTC_RTSI_TRIG_DIR_REG); |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 5011 | break; |
| 5012 | case INSN_CONFIG_DIO_INPUT: |
H Hartley Sweeten | a4f18b1 | 2015-05-01 14:59:14 -0700 | [diff] [blame] | 5013 | if (chan < max_chan) { |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 5014 | devpriv->rtsi_trig_direction_reg &= |
H Hartley Sweeten | a4f18b1 | 2015-05-01 14:59:14 -0700 | [diff] [blame] | 5015 | ~NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series); |
| 5016 | } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) { |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 5017 | devpriv->rtsi_trig_direction_reg &= |
H Hartley Sweeten | a4f18b1 | 2015-05-01 14:59:14 -0700 | [diff] [blame] | 5018 | ~NISTC_RTSI_TRIG_DRV_CLK; |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 5019 | } |
H Hartley Sweeten | 00b14b1 | 2014-06-19 10:20:34 -0700 | [diff] [blame] | 5020 | ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg, |
H Hartley Sweeten | a4f18b1 | 2015-05-01 14:59:14 -0700 | [diff] [blame] | 5021 | NISTC_RTSI_TRIG_DIR_REG); |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 5022 | break; |
| 5023 | case INSN_CONFIG_DIO_QUERY: |
H Hartley Sweeten | a4f18b1 | 2015-05-01 14:59:14 -0700 | [diff] [blame] | 5024 | if (chan < max_chan) { |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 5025 | data[1] = |
| 5026 | (devpriv->rtsi_trig_direction_reg & |
H Hartley Sweeten | a4f18b1 | 2015-05-01 14:59:14 -0700 | [diff] [blame] | 5027 | NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series)) |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 5028 | ? INSN_CONFIG_DIO_OUTPUT |
| 5029 | : INSN_CONFIG_DIO_INPUT; |
H Hartley Sweeten | a4f18b1 | 2015-05-01 14:59:14 -0700 | [diff] [blame] | 5030 | } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) { |
| 5031 | data[1] = (devpriv->rtsi_trig_direction_reg & |
| 5032 | NISTC_RTSI_TRIG_DRV_CLK) |
| 5033 | ? INSN_CONFIG_DIO_OUTPUT |
| 5034 | : INSN_CONFIG_DIO_INPUT; |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 5035 | } |
| 5036 | return 2; |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 5037 | case INSN_CONFIG_SET_CLOCK_SRC: |
| 5038 | return ni_set_master_clock(dev, data[1], data[2]); |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 5039 | case INSN_CONFIG_GET_CLOCK_SRC: |
| 5040 | data[1] = devpriv->clock_source; |
| 5041 | data[2] = devpriv->clock_ns; |
| 5042 | return 3; |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 5043 | case INSN_CONFIG_SET_ROUTING: |
| 5044 | return ni_set_rtsi_routing(dev, chan, data[1]); |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 5045 | case INSN_CONFIG_GET_ROUTING: |
| 5046 | data[1] = ni_get_rtsi_routing(dev, chan); |
| 5047 | return 2; |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 5048 | default: |
| 5049 | return -EINVAL; |
H Hartley Sweeten | ae43763 | 2014-05-28 16:26:45 -0700 | [diff] [blame] | 5050 | } |
| 5051 | return 1; |
| 5052 | } |
| 5053 | |
H Hartley Sweeten | 12db141 | 2014-05-28 16:26:32 -0700 | [diff] [blame] | 5054 | static int ni_rtsi_insn_bits(struct comedi_device *dev, |
| 5055 | struct comedi_subdevice *s, |
| 5056 | struct comedi_insn *insn, |
| 5057 | unsigned int *data) |
| 5058 | { |
| 5059 | data[1] = 0; |
| 5060 | |
| 5061 | return insn->n; |
| 5062 | } |
| 5063 | |
H Hartley Sweeten | 892885e | 2014-05-28 16:26:44 -0700 | [diff] [blame] | 5064 | static void ni_rtsi_init(struct comedi_device *dev) |
| 5065 | { |
H Hartley Sweeten | 892885e | 2014-05-28 16:26:44 -0700 | [diff] [blame] | 5066 | struct ni_private *devpriv = dev->private; |
| 5067 | |
| 5068 | /* Initialises the RTSI bus signal switch to a default state */ |
| 5069 | |
H Hartley Sweeten | 40aafd7 | 2015-05-01 14:58:36 -0700 | [diff] [blame] | 5070 | /* |
| 5071 | * Use 10MHz instead of 20MHz for RTSI clock frequency. Appears |
| 5072 | * to have no effect, at least on pxi-6281, which always uses |
| 5073 | * 20MHz rtsi clock frequency |
| 5074 | */ |
| 5075 | devpriv->clock_and_fout2 = NI_M_CLK_FOUT2_RTSI_10MHZ; |
H Hartley Sweeten | 892885e | 2014-05-28 16:26:44 -0700 | [diff] [blame] | 5076 | /* Set clock mode to internal */ |
H Hartley Sweeten | 892885e | 2014-05-28 16:26:44 -0700 | [diff] [blame] | 5077 | if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0) |
H Hartley Sweeten | 89c4695e | 2014-07-18 13:29:52 -0700 | [diff] [blame] | 5078 | dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n"); |
H Hartley Sweeten | 892885e | 2014-05-28 16:26:44 -0700 | [diff] [blame] | 5079 | /* default internal lines routing to RTSI bus lines */ |
| 5080 | devpriv->rtsi_trig_a_output_reg = |
H Hartley Sweeten | 390bc6f | 2015-05-01 14:59:32 -0700 | [diff] [blame] | 5081 | NISTC_RTSI_TRIG(0, NI_RTSI_OUTPUT_ADR_START1) | |
| 5082 | NISTC_RTSI_TRIG(1, NI_RTSI_OUTPUT_ADR_START2) | |
| 5083 | NISTC_RTSI_TRIG(2, NI_RTSI_OUTPUT_SCLKG) | |
| 5084 | NISTC_RTSI_TRIG(3, NI_RTSI_OUTPUT_DACUPDN); |
H Hartley Sweeten | 00b14b1 | 2014-06-19 10:20:34 -0700 | [diff] [blame] | 5085 | ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg, |
H Hartley Sweeten | 390bc6f | 2015-05-01 14:59:32 -0700 | [diff] [blame] | 5086 | NISTC_RTSI_TRIGA_OUT_REG); |
H Hartley Sweeten | 892885e | 2014-05-28 16:26:44 -0700 | [diff] [blame] | 5087 | devpriv->rtsi_trig_b_output_reg = |
H Hartley Sweeten | 390bc6f | 2015-05-01 14:59:32 -0700 | [diff] [blame] | 5088 | NISTC_RTSI_TRIG(4, NI_RTSI_OUTPUT_DA_START1) | |
| 5089 | NISTC_RTSI_TRIG(5, NI_RTSI_OUTPUT_G_SRC0) | |
| 5090 | NISTC_RTSI_TRIG(6, NI_RTSI_OUTPUT_G_GATE0); |
H Hartley Sweeten | 1773321 | 2014-06-19 10:20:32 -0700 | [diff] [blame] | 5091 | if (devpriv->is_m_series) |
H Hartley Sweeten | 892885e | 2014-05-28 16:26:44 -0700 | [diff] [blame] | 5092 | devpriv->rtsi_trig_b_output_reg |= |
H Hartley Sweeten | 390bc6f | 2015-05-01 14:59:32 -0700 | [diff] [blame] | 5093 | NISTC_RTSI_TRIG(7, NI_RTSI_OUTPUT_RTSI_OSC); |
H Hartley Sweeten | 00b14b1 | 2014-06-19 10:20:34 -0700 | [diff] [blame] | 5094 | ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg, |
H Hartley Sweeten | 390bc6f | 2015-05-01 14:59:32 -0700 | [diff] [blame] | 5095 | NISTC_RTSI_TRIGB_OUT_REG); |
H Hartley Sweeten | 892885e | 2014-05-28 16:26:44 -0700 | [diff] [blame] | 5096 | |
H Hartley Sweeten | 24a11ba | 2015-05-01 14:59:33 -0700 | [diff] [blame] | 5097 | /* |
| 5098 | * Sets the source and direction of the 4 on board lines |
| 5099 | * ni_stc_writew(dev, 0, NISTC_RTSI_BOARD_REG); |
| 5100 | */ |
H Hartley Sweeten | 892885e | 2014-05-28 16:26:44 -0700 | [diff] [blame] | 5101 | } |
| 5102 | |
H Hartley Sweeten | c8508a1 | 2014-05-28 16:26:29 -0700 | [diff] [blame] | 5103 | #ifdef PCIDMA |
| 5104 | static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s) |
| 5105 | { |
| 5106 | struct ni_gpct *counter = s->private; |
| 5107 | int retval; |
| 5108 | |
| 5109 | retval = ni_request_gpct_mite_channel(dev, counter->counter_index, |
| 5110 | COMEDI_INPUT); |
| 5111 | if (retval) { |
H Hartley Sweeten | 5ac1d82 | 2014-07-17 11:57:33 -0700 | [diff] [blame] | 5112 | dev_err(dev->class_dev, |
| 5113 | "no dma channel available for use by counter\n"); |
H Hartley Sweeten | c8508a1 | 2014-05-28 16:26:29 -0700 | [diff] [blame] | 5114 | return retval; |
| 5115 | } |
H Hartley Sweeten | f8cfd0e | 2014-07-28 10:27:04 -0700 | [diff] [blame] | 5116 | ni_tio_acknowledge(counter); |
H Hartley Sweeten | c8508a1 | 2014-05-28 16:26:29 -0700 | [diff] [blame] | 5117 | ni_e_series_enable_second_irq(dev, counter->counter_index, 1); |
| 5118 | |
| 5119 | return ni_tio_cmd(dev, s); |
| 5120 | } |
| 5121 | |
| 5122 | static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s) |
| 5123 | { |
| 5124 | struct ni_gpct *counter = s->private; |
| 5125 | int retval; |
| 5126 | |
| 5127 | retval = ni_tio_cancel(counter); |
| 5128 | ni_e_series_enable_second_irq(dev, counter->counter_index, 0); |
| 5129 | ni_release_gpct_mite_channel(dev, counter->counter_index); |
| 5130 | return retval; |
| 5131 | } |
| 5132 | #endif |
| 5133 | |
H Hartley Sweeten | c75527f | 2014-05-28 16:26:42 -0700 | [diff] [blame] | 5134 | static irqreturn_t ni_E_interrupt(int irq, void *d) |
| 5135 | { |
| 5136 | struct comedi_device *dev = d; |
H Hartley Sweeten | ba5c0da | 2016-04-21 12:04:41 -0700 | [diff] [blame] | 5137 | struct comedi_subdevice *s_ai = dev->read_subdev; |
H Hartley Sweeten | 7ef1745 | 2016-04-21 12:04:39 -0700 | [diff] [blame] | 5138 | struct comedi_subdevice *s_ao = dev->write_subdev; |
H Hartley Sweeten | c75527f | 2014-05-28 16:26:42 -0700 | [diff] [blame] | 5139 | unsigned short a_status; |
| 5140 | unsigned short b_status; |
H Hartley Sweeten | c75527f | 2014-05-28 16:26:42 -0700 | [diff] [blame] | 5141 | unsigned long flags; |
| 5142 | #ifdef PCIDMA |
H Hartley Sweeten | 00b14b1 | 2014-06-19 10:20:34 -0700 | [diff] [blame] | 5143 | struct ni_private *devpriv = dev->private; |
H Hartley Sweeten | c75527f | 2014-05-28 16:26:42 -0700 | [diff] [blame] | 5144 | #endif |
| 5145 | |
| 5146 | if (!dev->attached) |
| 5147 | return IRQ_NONE; |
H Hartley Sweeten | b6a0e5b | 2016-04-14 09:57:56 -0700 | [diff] [blame] | 5148 | smp_mb(); /* make sure dev->attached is checked */ |
H Hartley Sweeten | c75527f | 2014-05-28 16:26:42 -0700 | [diff] [blame] | 5149 | |
| 5150 | /* lock to avoid race with comedi_poll */ |
| 5151 | spin_lock_irqsave(&dev->spinlock, flags); |
H Hartley Sweeten | 7b14fff | 2015-05-01 14:59:37 -0700 | [diff] [blame] | 5152 | a_status = ni_stc_readw(dev, NISTC_AI_STATUS1_REG); |
H Hartley Sweeten | d123ee3 | 2015-05-01 14:59:38 -0700 | [diff] [blame] | 5153 | b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG); |
H Hartley Sweeten | c75527f | 2014-05-28 16:26:42 -0700 | [diff] [blame] | 5154 | #ifdef PCIDMA |
Spencer E. Olson | 6aab7fe | 2016-01-27 14:28:28 -0700 | [diff] [blame] | 5155 | if (devpriv->mite) { |
H Hartley Sweeten | c75527f | 2014-05-28 16:26:42 -0700 | [diff] [blame] | 5156 | unsigned long flags_too; |
| 5157 | |
| 5158 | spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too); |
H Hartley Sweeten | f7d005c | 2016-04-21 12:04:44 -0700 | [diff] [blame] | 5159 | if (s_ai && devpriv->ai_mite_chan) |
| 5160 | mite_ack_linkc(devpriv->ai_mite_chan, s_ai, false); |
| 5161 | if (s_ao && devpriv->ao_mite_chan) |
| 5162 | mite_ack_linkc(devpriv->ao_mite_chan, s_ao, false); |
H Hartley Sweeten | c75527f | 2014-05-28 16:26:42 -0700 | [diff] [blame] | 5163 | spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too); |
| 5164 | } |
| 5165 | #endif |
| 5166 | ack_a_interrupt(dev, a_status); |
| 5167 | ack_b_interrupt(dev, b_status); |
H Hartley Sweeten | 3da088c | 2016-04-21 12:04:43 -0700 | [diff] [blame] | 5168 | if (s_ai) { |
| 5169 | if (a_status & NISTC_AI_STATUS1_INTA) |
| 5170 | handle_a_interrupt(dev, s_ai, a_status); |
| 5171 | /* handle any interrupt or dma events */ |
| 5172 | comedi_handle_events(dev, s_ai); |
| 5173 | } |
H Hartley Sweeten | 4b2d738 | 2016-04-21 12:04:40 -0700 | [diff] [blame] | 5174 | if (s_ao) { |
| 5175 | if (b_status & NISTC_AO_STATUS1_INTB) |
| 5176 | handle_b_interrupt(dev, s_ao, b_status); |
| 5177 | /* handle any interrupt or dma events */ |
| 5178 | comedi_handle_events(dev, s_ao); |
| 5179 | } |
H Hartley Sweeten | c75527f | 2014-05-28 16:26:42 -0700 | [diff] [blame] | 5180 | handle_gpct_interrupt(dev, 0); |
| 5181 | handle_gpct_interrupt(dev, 1); |
H Hartley Sweeten | cf122bb | 2016-04-14 09:57:52 -0700 | [diff] [blame] | 5182 | #ifdef PCIDMA |
| 5183 | if (devpriv->is_m_series) |
| 5184 | handle_cdio_interrupt(dev); |
| 5185 | #endif |
H Hartley Sweeten | c75527f | 2014-05-28 16:26:42 -0700 | [diff] [blame] | 5186 | |
| 5187 | spin_unlock_irqrestore(&dev->spinlock, flags); |
| 5188 | return IRQ_HANDLED; |
| 5189 | } |
| 5190 | |
H Hartley Sweeten | 2832b18 | 2014-05-28 16:26:49 -0700 | [diff] [blame] | 5191 | static int ni_alloc_private(struct comedi_device *dev) |
| 5192 | { |
| 5193 | struct ni_private *devpriv; |
| 5194 | |
| 5195 | devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); |
| 5196 | if (!devpriv) |
| 5197 | return -ENOMEM; |
| 5198 | |
| 5199 | spin_lock_init(&devpriv->window_lock); |
| 5200 | spin_lock_init(&devpriv->soft_reg_copy_lock); |
| 5201 | spin_lock_init(&devpriv->mite_channel_lock); |
| 5202 | |
| 5203 | return 0; |
| 5204 | } |
| 5205 | |
H Hartley Sweeten | 1fa955b | 2014-06-20 11:10:23 -0700 | [diff] [blame] | 5206 | static int ni_E_init(struct comedi_device *dev, |
H Hartley Sweeten | fe20a34 | 2016-04-14 09:57:53 -0700 | [diff] [blame] | 5207 | unsigned int interrupt_pin, unsigned int irq_polarity) |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5208 | { |
Ian Abbott | 7cf94ad | 2014-09-09 11:26:44 +0100 | [diff] [blame] | 5209 | const struct ni_board_struct *board = dev->board_ptr; |
H Hartley Sweeten | 0e05c55 | 2012-10-15 10:19:06 -0700 | [diff] [blame] | 5210 | struct ni_private *devpriv = dev->private; |
Bill Pemberton | 34c4392 | 2009-03-16 22:05:14 -0400 | [diff] [blame] | 5211 | struct comedi_subdevice *s; |
H Hartley Sweeten | 8b6c569 | 2012-06-12 11:59:33 -0700 | [diff] [blame] | 5212 | int ret; |
H Hartley Sweeten | 43f2c8b7 | 2014-07-14 12:24:03 -0700 | [diff] [blame] | 5213 | int i; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5214 | |
H Hartley Sweeten | 6293e35 | 2013-03-05 10:20:41 -0700 | [diff] [blame] | 5215 | if (board->n_aochan > MAX_N_AO_CHAN) { |
H Hartley Sweeten | 89c4695e | 2014-07-18 13:29:52 -0700 | [diff] [blame] | 5216 | dev_err(dev->class_dev, "bug! n_aochan > MAX_N_AO_CHAN\n"); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5217 | return -EINVAL; |
| 5218 | } |
| 5219 | |
H Hartley Sweeten | caedecf | 2014-07-14 12:23:59 -0700 | [diff] [blame] | 5220 | /* initialize clock dividers */ |
H Hartley Sweeten | a47fc02 | 2015-05-01 14:59:10 -0700 | [diff] [blame] | 5221 | devpriv->clock_and_fout = NISTC_CLK_FOUT_SLOW_DIV2 | |
| 5222 | NISTC_CLK_FOUT_SLOW_TIMEBASE | |
| 5223 | NISTC_CLK_FOUT_TO_BOARD_DIV2 | |
| 5224 | NISTC_CLK_FOUT_TO_BOARD; |
H Hartley Sweeten | caedecf | 2014-07-14 12:23:59 -0700 | [diff] [blame] | 5225 | if (!devpriv->is_6xxx) { |
| 5226 | /* BEAM is this needed for PCI-6143 ?? */ |
H Hartley Sweeten | a47fc02 | 2015-05-01 14:59:10 -0700 | [diff] [blame] | 5227 | devpriv->clock_and_fout |= (NISTC_CLK_FOUT_AI_OUT_DIV2 | |
| 5228 | NISTC_CLK_FOUT_AO_OUT_DIV2); |
H Hartley Sweeten | caedecf | 2014-07-14 12:23:59 -0700 | [diff] [blame] | 5229 | } |
H Hartley Sweeten | a47fc02 | 2015-05-01 14:59:10 -0700 | [diff] [blame] | 5230 | ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG); |
H Hartley Sweeten | caedecf | 2014-07-14 12:23:59 -0700 | [diff] [blame] | 5231 | |
H Hartley Sweeten | 8b6c569 | 2012-06-12 11:59:33 -0700 | [diff] [blame] | 5232 | ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES); |
| 5233 | if (ret) |
| 5234 | return ret; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5235 | |
H Hartley Sweeten | a06500b | 2014-07-14 12:23:55 -0700 | [diff] [blame] | 5236 | /* Analog Input subdevice */ |
H Hartley Sweeten | f9cd92e | 2012-09-05 18:50:19 -0700 | [diff] [blame] | 5237 | s = &dev->subdevices[NI_AI_SUBDEV]; |
H Hartley Sweeten | 6293e35 | 2013-03-05 10:20:41 -0700 | [diff] [blame] | 5238 | if (board->n_adchan) { |
H Hartley Sweeten | a06500b | 2014-07-14 12:23:55 -0700 | [diff] [blame] | 5239 | s->type = COMEDI_SUBD_AI; |
| 5240 | s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_DITHER; |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 5241 | if (!devpriv->is_611x) |
H Hartley Sweeten | a06500b | 2014-07-14 12:23:55 -0700 | [diff] [blame] | 5242 | s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER; |
H Hartley Sweeten | db2255f | 2014-07-14 12:23:52 -0700 | [diff] [blame] | 5243 | if (board->ai_maxdata > 0xffff) |
H Hartley Sweeten | a06500b | 2014-07-14 12:23:55 -0700 | [diff] [blame] | 5244 | s->subdev_flags |= SDF_LSAMPL; |
H Hartley Sweeten | 1773321 | 2014-06-19 10:20:32 -0700 | [diff] [blame] | 5245 | if (devpriv->is_m_series) |
H Hartley Sweeten | a06500b | 2014-07-14 12:23:55 -0700 | [diff] [blame] | 5246 | s->subdev_flags |= SDF_SOFT_CALIBRATED; |
| 5247 | s->n_chan = board->n_adchan; |
| 5248 | s->maxdata = board->ai_maxdata; |
| 5249 | s->range_table = ni_range_lkup[board->gainlkup]; |
| 5250 | s->insn_read = ni_ai_insn_read; |
| 5251 | s->insn_config = ni_ai_insn_config; |
| 5252 | if (dev->irq) { |
| 5253 | dev->read_subdev = s; |
| 5254 | s->subdev_flags |= SDF_CMD_READ; |
| 5255 | s->len_chanlist = 512; |
| 5256 | s->do_cmdtest = ni_ai_cmdtest; |
| 5257 | s->do_cmd = ni_ai_cmd; |
| 5258 | s->cancel = ni_ai_reset; |
| 5259 | s->poll = ni_ai_poll; |
| 5260 | s->munge = ni_ai_munge; |
| 5261 | |
| 5262 | if (devpriv->mite) |
| 5263 | s->async_dma_dir = DMA_FROM_DEVICE; |
| 5264 | } |
H Hartley Sweeten | eeca0ca | 2014-07-14 12:24:00 -0700 | [diff] [blame] | 5265 | |
| 5266 | /* reset the analog input configuration */ |
| 5267 | ni_ai_reset(dev, s); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5268 | } else { |
H Hartley Sweeten | a06500b | 2014-07-14 12:23:55 -0700 | [diff] [blame] | 5269 | s->type = COMEDI_SUBD_UNUSED; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5270 | } |
| 5271 | |
H Hartley Sweeten | 80a94e4 | 2014-07-14 12:23:56 -0700 | [diff] [blame] | 5272 | /* Analog Output subdevice */ |
H Hartley Sweeten | f9cd92e | 2012-09-05 18:50:19 -0700 | [diff] [blame] | 5273 | s = &dev->subdevices[NI_AO_SUBDEV]; |
H Hartley Sweeten | 6293e35 | 2013-03-05 10:20:41 -0700 | [diff] [blame] | 5274 | if (board->n_aochan) { |
H Hartley Sweeten | 80a94e4 | 2014-07-14 12:23:56 -0700 | [diff] [blame] | 5275 | s->type = COMEDI_SUBD_AO; |
| 5276 | s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND; |
H Hartley Sweeten | 1773321 | 2014-06-19 10:20:32 -0700 | [diff] [blame] | 5277 | if (devpriv->is_m_series) |
H Hartley Sweeten | 80a94e4 | 2014-07-14 12:23:56 -0700 | [diff] [blame] | 5278 | s->subdev_flags |= SDF_SOFT_CALIBRATED; |
| 5279 | s->n_chan = board->n_aochan; |
| 5280 | s->maxdata = board->ao_maxdata; |
| 5281 | s->range_table = board->ao_range_table; |
H Hartley Sweeten | 80a94e4 | 2014-07-14 12:23:56 -0700 | [diff] [blame] | 5282 | s->insn_config = ni_ao_insn_config; |
H Hartley Sweeten | b6d977e | 2014-08-25 16:04:15 -0700 | [diff] [blame] | 5283 | s->insn_write = ni_ao_insn_write; |
H Hartley Sweeten | b6d977e | 2014-08-25 16:04:15 -0700 | [diff] [blame] | 5284 | |
| 5285 | ret = comedi_alloc_subdev_readback(s); |
| 5286 | if (ret) |
| 5287 | return ret; |
H Hartley Sweeten | 80a94e4 | 2014-07-14 12:23:56 -0700 | [diff] [blame] | 5288 | |
| 5289 | /* |
| 5290 | * Along with the IRQ we need either a FIFO or DMA for |
| 5291 | * async command support. |
| 5292 | */ |
| 5293 | if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) { |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5294 | dev->write_subdev = s; |
H Hartley Sweeten | 80a94e4 | 2014-07-14 12:23:56 -0700 | [diff] [blame] | 5295 | s->subdev_flags |= SDF_CMD_WRITE; |
| 5296 | s->len_chanlist = s->n_chan; |
| 5297 | s->do_cmdtest = ni_ao_cmdtest; |
| 5298 | s->do_cmd = ni_ao_cmd; |
| 5299 | s->cancel = ni_ao_reset; |
H Hartley Sweeten | 1773321 | 2014-06-19 10:20:32 -0700 | [diff] [blame] | 5300 | if (!devpriv->is_m_series) |
H Hartley Sweeten | 80a94e4 | 2014-07-14 12:23:56 -0700 | [diff] [blame] | 5301 | s->munge = ni_ao_munge; |
| 5302 | |
| 5303 | if (devpriv->mite) |
| 5304 | s->async_dma_dir = DMA_TO_DEVICE; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5305 | } |
H Hartley Sweeten | 80a94e4 | 2014-07-14 12:23:56 -0700 | [diff] [blame] | 5306 | |
| 5307 | if (devpriv->is_67xx) |
| 5308 | init_ao_67xx(dev, s); |
H Hartley Sweeten | eeca0ca | 2014-07-14 12:24:00 -0700 | [diff] [blame] | 5309 | |
| 5310 | /* reset the analog output configuration */ |
| 5311 | ni_ao_reset(dev, s); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5312 | } else { |
H Hartley Sweeten | 80a94e4 | 2014-07-14 12:23:56 -0700 | [diff] [blame] | 5313 | s->type = COMEDI_SUBD_UNUSED; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5314 | } |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5315 | |
H Hartley Sweeten | 2d4ecc3 | 2014-07-14 12:23:58 -0700 | [diff] [blame] | 5316 | /* Digital I/O subdevice */ |
H Hartley Sweeten | f9cd92e | 2012-09-05 18:50:19 -0700 | [diff] [blame] | 5317 | s = &dev->subdevices[NI_DIO_SUBDEV]; |
H Hartley Sweeten | 2d4ecc3 | 2014-07-14 12:23:58 -0700 | [diff] [blame] | 5318 | s->type = COMEDI_SUBD_DIO; |
| 5319 | s->subdev_flags = SDF_WRITABLE | SDF_READABLE; |
| 5320 | s->n_chan = board->has_32dio_chan ? 32 : 8; |
| 5321 | s->maxdata = 1; |
| 5322 | s->range_table = &range_digital; |
H Hartley Sweeten | 1773321 | 2014-06-19 10:20:32 -0700 | [diff] [blame] | 5323 | if (devpriv->is_m_series) { |
H Hartley Sweeten | cf122bb | 2016-04-14 09:57:52 -0700 | [diff] [blame] | 5324 | #ifdef PCIDMA |
H Hartley Sweeten | 2d4ecc3 | 2014-07-14 12:23:58 -0700 | [diff] [blame] | 5325 | s->subdev_flags |= SDF_LSAMPL; |
| 5326 | s->insn_bits = ni_m_series_dio_insn_bits; |
| 5327 | s->insn_config = ni_m_series_dio_insn_config; |
| 5328 | if (dev->irq) { |
| 5329 | s->subdev_flags |= SDF_CMD_WRITE /* | SDF_CMD_READ */; |
| 5330 | s->len_chanlist = s->n_chan; |
| 5331 | s->do_cmdtest = ni_cdio_cmdtest; |
| 5332 | s->do_cmd = ni_cdio_cmd; |
| 5333 | s->cancel = ni_cdio_cancel; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5334 | |
H Hartley Sweeten | 2d4ecc3 | 2014-07-14 12:23:58 -0700 | [diff] [blame] | 5335 | /* M-series boards use DMA */ |
| 5336 | s->async_dma_dir = DMA_BIDIRECTIONAL; |
| 5337 | } |
| 5338 | |
| 5339 | /* reset DIO and set all channels to inputs */ |
H Hartley Sweeten | 3c3eb8e | 2015-05-01 14:58:47 -0700 | [diff] [blame] | 5340 | ni_writel(dev, NI_M_CDO_CMD_RESET | |
| 5341 | NI_M_CDI_CMD_RESET, |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 5342 | NI_M_CDIO_CMD_REG); |
| 5343 | ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG); |
H Hartley Sweeten | cf122bb | 2016-04-14 09:57:52 -0700 | [diff] [blame] | 5344 | #endif /* PCIDMA */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5345 | } else { |
H Hartley Sweeten | 2d4ecc3 | 2014-07-14 12:23:58 -0700 | [diff] [blame] | 5346 | s->insn_bits = ni_dio_insn_bits; |
| 5347 | s->insn_config = ni_dio_insn_config; |
| 5348 | |
| 5349 | /* set all channels to inputs */ |
H Hartley Sweeten | 59a97c3 | 2015-05-01 14:59:02 -0700 | [diff] [blame] | 5350 | devpriv->dio_control = NISTC_DIO_CTRL_DIR(s->io_bits); |
| 5351 | ni_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5352 | } |
| 5353 | |
| 5354 | /* 8255 device */ |
H Hartley Sweeten | f9cd92e | 2012-09-05 18:50:19 -0700 | [diff] [blame] | 5355 | s = &dev->subdevices[NI_8255_DIO_SUBDEV]; |
H Hartley Sweeten | e6439a4 | 2014-02-03 10:43:25 -0700 | [diff] [blame] | 5356 | if (board->has_8255) { |
H Hartley Sweeten | 61260f5 | 2015-05-01 14:59:55 -0700 | [diff] [blame] | 5357 | ret = subdev_8255_init(dev, s, ni_8255_callback, |
| 5358 | NI_E_8255_BASE); |
H Hartley Sweeten | e6439a4 | 2014-02-03 10:43:25 -0700 | [diff] [blame] | 5359 | if (ret) |
| 5360 | return ret; |
| 5361 | } else { |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5362 | s->type = COMEDI_SUBD_UNUSED; |
H Hartley Sweeten | e6439a4 | 2014-02-03 10:43:25 -0700 | [diff] [blame] | 5363 | } |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5364 | |
| 5365 | /* formerly general purpose counter/timer device, but no longer used */ |
H Hartley Sweeten | f9cd92e | 2012-09-05 18:50:19 -0700 | [diff] [blame] | 5366 | s = &dev->subdevices[NI_UNUSED_SUBDEV]; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5367 | s->type = COMEDI_SUBD_UNUSED; |
| 5368 | |
H Hartley Sweeten | cb42950 | 2014-07-14 12:24:01 -0700 | [diff] [blame] | 5369 | /* Calibration subdevice */ |
H Hartley Sweeten | f9cd92e | 2012-09-05 18:50:19 -0700 | [diff] [blame] | 5370 | s = &dev->subdevices[NI_CALIBRATION_SUBDEV]; |
H Hartley Sweeten | cb42950 | 2014-07-14 12:24:01 -0700 | [diff] [blame] | 5371 | s->type = COMEDI_SUBD_CALIB; |
| 5372 | s->subdev_flags = SDF_INTERNAL; |
| 5373 | s->n_chan = 1; |
| 5374 | s->maxdata = 0; |
H Hartley Sweeten | 1773321 | 2014-06-19 10:20:32 -0700 | [diff] [blame] | 5375 | if (devpriv->is_m_series) { |
H Hartley Sweeten | cb42950 | 2014-07-14 12:24:01 -0700 | [diff] [blame] | 5376 | /* internal PWM output used for AI nonlinearity calibration */ |
| 5377 | s->insn_config = ni_m_series_pwm_config; |
| 5378 | |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 5379 | ni_writel(dev, 0x0, NI_M_CAL_PWM_REG); |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 5380 | } else if (devpriv->is_6143) { |
H Hartley Sweeten | cb42950 | 2014-07-14 12:24:01 -0700 | [diff] [blame] | 5381 | /* internal PWM output used for AI nonlinearity calibration */ |
| 5382 | s->insn_config = ni_6143_pwm_config; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5383 | } else { |
H Hartley Sweeten | cb42950 | 2014-07-14 12:24:01 -0700 | [diff] [blame] | 5384 | s->subdev_flags |= SDF_WRITABLE; |
| 5385 | s->insn_read = ni_calib_insn_read; |
| 5386 | s->insn_write = ni_calib_insn_write; |
| 5387 | |
| 5388 | /* setup the caldacs and find the real n_chan and maxdata */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5389 | caldac_setup(dev, s); |
| 5390 | } |
| 5391 | |
H Hartley Sweeten | 433c79f | 2014-07-14 12:24:02 -0700 | [diff] [blame] | 5392 | /* EEPROM subdevice */ |
H Hartley Sweeten | f9cd92e | 2012-09-05 18:50:19 -0700 | [diff] [blame] | 5393 | s = &dev->subdevices[NI_EEPROM_SUBDEV]; |
H Hartley Sweeten | 433c79f | 2014-07-14 12:24:02 -0700 | [diff] [blame] | 5394 | s->type = COMEDI_SUBD_MEMORY; |
| 5395 | s->subdev_flags = SDF_READABLE | SDF_INTERNAL; |
| 5396 | s->maxdata = 0xff; |
H Hartley Sweeten | 1773321 | 2014-06-19 10:20:32 -0700 | [diff] [blame] | 5397 | if (devpriv->is_m_series) { |
H Hartley Sweeten | 433c79f | 2014-07-14 12:24:02 -0700 | [diff] [blame] | 5398 | s->n_chan = M_SERIES_EEPROM_SIZE; |
| 5399 | s->insn_read = ni_m_series_eeprom_insn_read; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5400 | } else { |
H Hartley Sweeten | 433c79f | 2014-07-14 12:24:02 -0700 | [diff] [blame] | 5401 | s->n_chan = 512; |
| 5402 | s->insn_read = ni_eeprom_insn_read; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5403 | } |
| 5404 | |
H Hartley Sweeten | 43f2c8b7 | 2014-07-14 12:24:03 -0700 | [diff] [blame] | 5405 | /* Digital I/O (PFI) subdevice */ |
H Hartley Sweeten | f9cd92e | 2012-09-05 18:50:19 -0700 | [diff] [blame] | 5406 | s = &dev->subdevices[NI_PFI_DIO_SUBDEV]; |
H Hartley Sweeten | 43f2c8b7 | 2014-07-14 12:24:03 -0700 | [diff] [blame] | 5407 | s->type = COMEDI_SUBD_DIO; |
| 5408 | s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; |
| 5409 | s->maxdata = 1; |
H Hartley Sweeten | 1773321 | 2014-06-19 10:20:32 -0700 | [diff] [blame] | 5410 | if (devpriv->is_m_series) { |
H Hartley Sweeten | 43f2c8b7 | 2014-07-14 12:24:03 -0700 | [diff] [blame] | 5411 | s->n_chan = 16; |
| 5412 | s->insn_bits = ni_pfi_insn_bits; |
| 5413 | |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 5414 | ni_writew(dev, s->state, NI_M_PFI_DO_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5415 | for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) { |
H Hartley Sweeten | 5a92cac | 2014-06-19 10:20:35 -0700 | [diff] [blame] | 5416 | ni_writew(dev, devpriv->pfi_output_select_reg[i], |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 5417 | NI_M_PFI_OUT_SEL_REG(i)); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5418 | } |
| 5419 | } else { |
H Hartley Sweeten | 43f2c8b7 | 2014-07-14 12:24:03 -0700 | [diff] [blame] | 5420 | s->n_chan = 10; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5421 | } |
H Hartley Sweeten | 43f2c8b7 | 2014-07-14 12:24:03 -0700 | [diff] [blame] | 5422 | s->insn_config = ni_pfi_insn_config; |
| 5423 | |
H Hartley Sweeten | 5ecadf8 | 2015-05-01 14:59:12 -0700 | [diff] [blame] | 5424 | ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, ~0, 0); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5425 | |
| 5426 | /* cs5529 calibration adc */ |
H Hartley Sweeten | f9cd92e | 2012-09-05 18:50:19 -0700 | [diff] [blame] | 5427 | s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV]; |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 5428 | if (devpriv->is_67xx) { |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5429 | s->type = COMEDI_SUBD_AI; |
| 5430 | s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL; |
Bill Pemberton | 2696fb5 | 2009-03-27 11:29:34 -0400 | [diff] [blame] | 5431 | /* one channel for each analog output channel */ |
H Hartley Sweeten | 6293e35 | 2013-03-05 10:20:41 -0700 | [diff] [blame] | 5432 | s->n_chan = board->n_aochan; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5433 | s->maxdata = (1 << 16) - 1; |
| 5434 | s->range_table = &range_unknown; /* XXX */ |
| 5435 | s->insn_read = cs5529_ai_insn_read; |
| 5436 | s->insn_config = NULL; |
| 5437 | init_cs5529(dev); |
| 5438 | } else { |
| 5439 | s->type = COMEDI_SUBD_UNUSED; |
| 5440 | } |
| 5441 | |
| 5442 | /* Serial */ |
H Hartley Sweeten | f9cd92e | 2012-09-05 18:50:19 -0700 | [diff] [blame] | 5443 | s = &dev->subdevices[NI_SERIAL_SUBDEV]; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5444 | s->type = COMEDI_SUBD_SERIAL; |
| 5445 | s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; |
| 5446 | s->n_chan = 1; |
| 5447 | s->maxdata = 0xff; |
| 5448 | s->insn_config = ni_serial_insn_config; |
| 5449 | devpriv->serial_interval_ns = 0; |
| 5450 | devpriv->serial_hw_mode = 0; |
| 5451 | |
| 5452 | /* RTSI */ |
H Hartley Sweeten | f9cd92e | 2012-09-05 18:50:19 -0700 | [diff] [blame] | 5453 | s = &dev->subdevices[NI_RTSI_SUBDEV]; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5454 | s->type = COMEDI_SUBD_DIO; |
| 5455 | s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; |
| 5456 | s->n_chan = 8; |
| 5457 | s->maxdata = 1; |
| 5458 | s->insn_bits = ni_rtsi_insn_bits; |
| 5459 | s->insn_config = ni_rtsi_insn_config; |
| 5460 | ni_rtsi_init(dev); |
| 5461 | |
H Hartley Sweeten | c607b33 | 2014-07-14 12:24:04 -0700 | [diff] [blame] | 5462 | /* allocate and initialize the gpct counter device */ |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5463 | devpriv->counter_dev = ni_gpct_device_construct(dev, |
H Hartley Sweeten | c607b33 | 2014-07-14 12:24:04 -0700 | [diff] [blame] | 5464 | ni_gpct_write_register, |
| 5465 | ni_gpct_read_register, |
| 5466 | (devpriv->is_m_series) |
| 5467 | ? ni_gpct_variant_m_series |
| 5468 | : ni_gpct_variant_e_series, |
| 5469 | NUM_GPCT); |
Kumar Amit Mehta | c095fad | 2014-02-26 01:04:45 +0200 | [diff] [blame] | 5470 | if (!devpriv->counter_dev) |
| 5471 | return -ENOMEM; |
| 5472 | |
H Hartley Sweeten | c607b33 | 2014-07-14 12:24:04 -0700 | [diff] [blame] | 5473 | /* Counter (gpct) subdevices */ |
H Hartley Sweeten | 43f2c8b7 | 2014-07-14 12:24:03 -0700 | [diff] [blame] | 5474 | for (i = 0; i < NUM_GPCT; ++i) { |
H Hartley Sweeten | c607b33 | 2014-07-14 12:24:04 -0700 | [diff] [blame] | 5475 | struct ni_gpct *gpct = &devpriv->counter_dev->counters[i]; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5476 | |
H Hartley Sweeten | c607b33 | 2014-07-14 12:24:04 -0700 | [diff] [blame] | 5477 | /* setup and initialize the counter */ |
| 5478 | gpct->chip_index = 0; |
| 5479 | gpct->counter_index = i; |
| 5480 | ni_tio_init_counter(gpct); |
| 5481 | |
| 5482 | s = &dev->subdevices[NI_GPCT_SUBDEV(i)]; |
| 5483 | s->type = COMEDI_SUBD_COUNTER; |
| 5484 | s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL; |
| 5485 | s->n_chan = 3; |
| 5486 | s->maxdata = (devpriv->is_m_series) ? 0xffffffff |
| 5487 | : 0x00ffffff; |
| 5488 | s->insn_read = ni_tio_insn_read; |
Ian Abbott | 5ca0534 | 2016-07-20 17:07:34 +0100 | [diff] [blame] | 5489 | s->insn_write = ni_tio_insn_write; |
H Hartley Sweeten | c607b33 | 2014-07-14 12:24:04 -0700 | [diff] [blame] | 5490 | s->insn_config = ni_tio_insn_config; |
| 5491 | #ifdef PCIDMA |
| 5492 | if (dev->irq && devpriv->mite) { |
| 5493 | s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */; |
| 5494 | s->len_chanlist = 1; |
| 5495 | s->do_cmdtest = ni_tio_cmdtest; |
| 5496 | s->do_cmd = ni_gpct_cmd; |
| 5497 | s->cancel = ni_gpct_cancel; |
| 5498 | |
| 5499 | s->async_dma_dir = DMA_BIDIRECTIONAL; |
| 5500 | } |
| 5501 | #endif |
| 5502 | s->private = gpct; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5503 | } |
| 5504 | |
H Hartley Sweeten | 4168ac9 | 2014-07-14 12:24:05 -0700 | [diff] [blame] | 5505 | /* Frequency output subdevice */ |
H Hartley Sweeten | f9cd92e | 2012-09-05 18:50:19 -0700 | [diff] [blame] | 5506 | s = &dev->subdevices[NI_FREQ_OUT_SUBDEV]; |
H Hartley Sweeten | 4168ac9 | 2014-07-14 12:24:05 -0700 | [diff] [blame] | 5507 | s->type = COMEDI_SUBD_COUNTER; |
| 5508 | s->subdev_flags = SDF_READABLE | SDF_WRITABLE; |
| 5509 | s->n_chan = 1; |
| 5510 | s->maxdata = 0xf; |
| 5511 | s->insn_read = ni_freq_out_insn_read; |
| 5512 | s->insn_write = ni_freq_out_insn_write; |
| 5513 | s->insn_config = ni_freq_out_insn_config; |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5514 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5515 | if (dev->irq) { |
H Hartley Sweeten | 00b14b1 | 2014-06-19 10:20:34 -0700 | [diff] [blame] | 5516 | ni_stc_writew(dev, |
H Hartley Sweeten | d8f62c4 | 2015-05-01 14:59:15 -0700 | [diff] [blame] | 5517 | (irq_polarity ? NISTC_INT_CTRL_INT_POL : 0) | |
| 5518 | (NISTC_INT_CTRL_3PIN_INT & 0) | |
| 5519 | NISTC_INT_CTRL_INTA_ENA | |
| 5520 | NISTC_INT_CTRL_INTB_ENA | |
| 5521 | NISTC_INT_CTRL_INTA_SEL(interrupt_pin) | |
| 5522 | NISTC_INT_CTRL_INTB_SEL(interrupt_pin), |
| 5523 | NISTC_INT_CTRL_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5524 | } |
| 5525 | |
| 5526 | /* DMA setup */ |
H Hartley Sweeten | a4b7ef9 | 2015-05-01 15:00:03 -0700 | [diff] [blame] | 5527 | ni_writeb(dev, devpriv->ai_ao_select_reg, NI_E_DMA_AI_AO_SEL_REG); |
H Hartley Sweeten | 7d6f3aa | 2015-05-01 15:00:04 -0700 | [diff] [blame] | 5528 | ni_writeb(dev, devpriv->g0_g1_select_reg, NI_E_DMA_G0_G1_SEL_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5529 | |
H Hartley Sweeten | a52b53e | 2014-07-14 12:23:44 -0700 | [diff] [blame] | 5530 | if (devpriv->is_6xxx) { |
H Hartley Sweeten | 0418da5 | 2015-05-01 15:00:07 -0700 | [diff] [blame] | 5531 | ni_writeb(dev, 0, NI611X_MAGIC_REG); |
H Hartley Sweeten | 1773321 | 2014-06-19 10:20:32 -0700 | [diff] [blame] | 5532 | } else if (devpriv->is_m_series) { |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5533 | int channel; |
H Hartley Sweeten | f740197 | 2014-07-16 11:02:08 -0700 | [diff] [blame] | 5534 | |
H Hartley Sweeten | 6293e35 | 2013-03-05 10:20:41 -0700 | [diff] [blame] | 5535 | for (channel = 0; channel < board->n_aochan; ++channel) { |
H Hartley Sweeten | 5a92cac | 2014-06-19 10:20:35 -0700 | [diff] [blame] | 5536 | ni_writeb(dev, 0xf, |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 5537 | NI_M_AO_WAVEFORM_ORDER_REG(channel)); |
H Hartley Sweeten | 5a92cac | 2014-06-19 10:20:35 -0700 | [diff] [blame] | 5538 | ni_writeb(dev, 0x0, |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 5539 | NI_M_AO_REF_ATTENUATION_REG(channel)); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5540 | } |
H Hartley Sweeten | 975b6d2 | 2015-05-01 14:58:34 -0700 | [diff] [blame] | 5541 | ni_writeb(dev, 0x0, NI_M_AO_CALIB_REG); |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5542 | } |
| 5543 | |
David Schleef | 03aef4b | 2009-02-17 17:04:22 -0800 | [diff] [blame] | 5544 | return 0; |
| 5545 | } |
H Hartley Sweeten | 2832b18 | 2014-05-28 16:26:49 -0700 | [diff] [blame] | 5546 | |
| 5547 | static void mio_common_detach(struct comedi_device *dev) |
| 5548 | { |
| 5549 | struct ni_private *devpriv = dev->private; |
| 5550 | |
H Hartley Sweeten | 99307a6 | 2016-03-22 11:10:42 -0700 | [diff] [blame] | 5551 | if (devpriv) |
| 5552 | ni_gpct_device_destroy(devpriv->counter_dev); |
H Hartley Sweeten | 2832b18 | 2014-05-28 16:26:49 -0700 | [diff] [blame] | 5553 | } |