viresh kumar | bc4e814 | 2010-04-01 12:30:58 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-spear3xx/spear320.c |
| 3 | * |
| 4 | * SPEAr320 machine source file |
| 5 | * |
Viresh Kumar | c5fa4fd | 2012-03-23 00:17:43 +0530 | [diff] [blame] | 6 | * Copyright (C) 2009-2012 ST Microelectronics |
| 7 | * Viresh Kumar <viresh.kumar@st.com> |
viresh kumar | bc4e814 | 2010-04-01 12:30:58 +0100 | [diff] [blame] | 8 | * |
| 9 | * This file is licensed under the terms of the GNU General Public |
| 10 | * License version 2. This program is licensed "as is" without any |
| 11 | * warranty of any kind, whether express or implied. |
| 12 | */ |
| 13 | |
Viresh Kumar | 5fb00f9 | 2012-03-26 10:39:43 +0530 | [diff] [blame] | 14 | #define pr_fmt(fmt) "SPEAr320: " fmt |
| 15 | |
Viresh Kumar | c5fa4fd | 2012-03-23 00:17:43 +0530 | [diff] [blame] | 16 | #include <linux/amba/pl022.h> |
| 17 | #include <linux/amba/pl08x.h> |
| 18 | #include <linux/amba/serial.h> |
| 19 | #include <linux/of_platform.h> |
| 20 | #include <asm/hardware/vic.h> |
| 21 | #include <asm/mach/arch.h> |
viresh kumar | 410782b | 2011-03-07 05:57:01 +0100 | [diff] [blame] | 22 | #include <plat/shirq.h> |
viresh kumar | bc4e814 | 2010-04-01 12:30:58 +0100 | [diff] [blame] | 23 | #include <mach/generic.h> |
Arnd Bergmann | 5019f0b | 2012-04-11 17:30:11 +0000 | [diff] [blame^] | 24 | #include <mach/spear.h> |
| 25 | |
| 26 | #define SPEAR320_UART1_BASE UL(0xA3000000) |
| 27 | #define SPEAR320_UART2_BASE UL(0xA4000000) |
| 28 | #define SPEAR320_SSP0_BASE UL(0xA5000000) |
| 29 | #define SPEAR320_SSP1_BASE UL(0xA6000000) |
| 30 | #define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) |
| 31 | |
| 32 | /* Interrupt registers offsets and masks */ |
| 33 | #define SPEAR320_INT_STS_MASK_REG 0x04 |
| 34 | #define SPEAR320_INT_CLR_MASK_REG 0x04 |
| 35 | #define SPEAR320_INT_ENB_MASK_REG 0x08 |
| 36 | #define SPEAR320_GPIO_IRQ_MASK (1 << 0) |
| 37 | #define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1) |
| 38 | #define SPEAR320_I2S_REC_IRQ_MASK (1 << 2) |
| 39 | #define SPEAR320_EMI_IRQ_MASK (1 << 7) |
| 40 | #define SPEAR320_CLCD_IRQ_MASK (1 << 8) |
| 41 | #define SPEAR320_SPP_IRQ_MASK (1 << 9) |
| 42 | #define SPEAR320_SDHCI_IRQ_MASK (1 << 10) |
| 43 | #define SPEAR320_CAN_U_IRQ_MASK (1 << 11) |
| 44 | #define SPEAR320_CAN_L_IRQ_MASK (1 << 12) |
| 45 | #define SPEAR320_UART1_IRQ_MASK (1 << 13) |
| 46 | #define SPEAR320_UART2_IRQ_MASK (1 << 14) |
| 47 | #define SPEAR320_SSP1_IRQ_MASK (1 << 15) |
| 48 | #define SPEAR320_SSP2_IRQ_MASK (1 << 16) |
| 49 | #define SPEAR320_SMII0_IRQ_MASK (1 << 17) |
| 50 | #define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18) |
| 51 | #define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19) |
| 52 | #define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20) |
| 53 | #define SPEAR320_I2C1_IRQ_MASK (1 << 21) |
| 54 | |
| 55 | #define SPEAR320_SHIRQ_RAS1_MASK 0x000380 |
| 56 | #define SPEAR320_SHIRQ_RAS3_MASK 0x000007 |
| 57 | #define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800 |
| 58 | |
| 59 | /* SPEAr320 Virtual irq definitions */ |
| 60 | /* IRQs sharing IRQ_GEN_RAS_1 */ |
| 61 | #define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0) |
| 62 | #define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1) |
| 63 | #define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2) |
| 64 | |
| 65 | /* IRQs sharing IRQ_GEN_RAS_2 */ |
| 66 | #define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2 |
| 67 | |
| 68 | /* IRQs sharing IRQ_GEN_RAS_3 */ |
| 69 | #define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3) |
| 70 | #define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4) |
| 71 | #define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5) |
| 72 | |
| 73 | /* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ |
| 74 | #define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6) |
| 75 | #define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7) |
| 76 | #define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8) |
| 77 | #define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9) |
| 78 | #define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10) |
| 79 | #define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11) |
| 80 | #define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12) |
| 81 | #define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13) |
| 82 | #define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14) |
| 83 | #define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15) |
| 84 | #define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16) |
viresh kumar | bc4e814 | 2010-04-01 12:30:58 +0100 | [diff] [blame] | 85 | |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 86 | /* pad multiplexing support */ |
| 87 | /* muxing registers */ |
| 88 | #define PAD_MUX_CONFIG_REG 0x0C |
| 89 | #define MODE_CONFIG_REG 0x10 |
| 90 | |
| 91 | /* modes */ |
| 92 | #define AUTO_NET_SMII_MODE (1 << 0) |
| 93 | #define AUTO_NET_MII_MODE (1 << 1) |
| 94 | #define AUTO_EXP_MODE (1 << 2) |
| 95 | #define SMALL_PRINTERS_MODE (1 << 3) |
| 96 | #define ALL_MODES 0xF |
| 97 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 98 | struct pmx_mode spear320_auto_net_smii_mode = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 99 | .id = AUTO_NET_SMII_MODE, |
| 100 | .name = "Automation Networking SMII Mode", |
| 101 | .mask = 0x00, |
| 102 | }; |
| 103 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 104 | struct pmx_mode spear320_auto_net_mii_mode = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 105 | .id = AUTO_NET_MII_MODE, |
| 106 | .name = "Automation Networking MII Mode", |
| 107 | .mask = 0x01, |
| 108 | }; |
| 109 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 110 | struct pmx_mode spear320_auto_exp_mode = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 111 | .id = AUTO_EXP_MODE, |
| 112 | .name = "Automation Expanded Mode", |
| 113 | .mask = 0x02, |
| 114 | }; |
| 115 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 116 | struct pmx_mode spear320_small_printers_mode = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 117 | .id = SMALL_PRINTERS_MODE, |
| 118 | .name = "Small Printers Mode", |
| 119 | .mask = 0x03, |
| 120 | }; |
| 121 | |
| 122 | /* devices */ |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 123 | static struct pmx_dev_mode pmx_clcd_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 124 | { |
| 125 | .ids = AUTO_NET_SMII_MODE, |
| 126 | .mask = 0x0, |
| 127 | }, |
| 128 | }; |
| 129 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 130 | struct pmx_dev spear320_pmx_clcd = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 131 | .name = "clcd", |
| 132 | .modes = pmx_clcd_modes, |
| 133 | .mode_count = ARRAY_SIZE(pmx_clcd_modes), |
| 134 | .enb_on_reset = 1, |
| 135 | }; |
| 136 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 137 | static struct pmx_dev_mode pmx_emi_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 138 | { |
| 139 | .ids = AUTO_EXP_MODE, |
| 140 | .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, |
| 141 | }, |
| 142 | }; |
| 143 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 144 | struct pmx_dev spear320_pmx_emi = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 145 | .name = "emi", |
| 146 | .modes = pmx_emi_modes, |
| 147 | .mode_count = ARRAY_SIZE(pmx_emi_modes), |
| 148 | .enb_on_reset = 1, |
| 149 | }; |
| 150 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 151 | static struct pmx_dev_mode pmx_fsmc_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 152 | { |
| 153 | .ids = ALL_MODES, |
| 154 | .mask = 0x0, |
| 155 | }, |
| 156 | }; |
| 157 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 158 | struct pmx_dev spear320_pmx_fsmc = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 159 | .name = "fsmc", |
| 160 | .modes = pmx_fsmc_modes, |
| 161 | .mode_count = ARRAY_SIZE(pmx_fsmc_modes), |
| 162 | .enb_on_reset = 1, |
| 163 | }; |
| 164 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 165 | static struct pmx_dev_mode pmx_spp_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 166 | { |
| 167 | .ids = SMALL_PRINTERS_MODE, |
| 168 | .mask = 0x0, |
| 169 | }, |
| 170 | }; |
| 171 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 172 | struct pmx_dev spear320_pmx_spp = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 173 | .name = "spp", |
| 174 | .modes = pmx_spp_modes, |
| 175 | .mode_count = ARRAY_SIZE(pmx_spp_modes), |
| 176 | .enb_on_reset = 1, |
| 177 | }; |
| 178 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 179 | static struct pmx_dev_mode pmx_sdhci_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 180 | { |
| 181 | .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | |
| 182 | SMALL_PRINTERS_MODE, |
| 183 | .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, |
| 184 | }, |
| 185 | }; |
| 186 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 187 | struct pmx_dev spear320_pmx_sdhci = { |
viresh kumar | 069580b | 2011-03-07 05:57:03 +0100 | [diff] [blame] | 188 | .name = "sdhci", |
| 189 | .modes = pmx_sdhci_modes, |
| 190 | .mode_count = ARRAY_SIZE(pmx_sdhci_modes), |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 191 | .enb_on_reset = 1, |
| 192 | }; |
| 193 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 194 | static struct pmx_dev_mode pmx_i2s_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 195 | { |
| 196 | .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, |
| 197 | .mask = PMX_UART0_MODEM_MASK, |
| 198 | }, |
| 199 | }; |
| 200 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 201 | struct pmx_dev spear320_pmx_i2s = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 202 | .name = "i2s", |
| 203 | .modes = pmx_i2s_modes, |
| 204 | .mode_count = ARRAY_SIZE(pmx_i2s_modes), |
| 205 | .enb_on_reset = 1, |
| 206 | }; |
| 207 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 208 | static struct pmx_dev_mode pmx_uart1_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 209 | { |
| 210 | .ids = ALL_MODES, |
| 211 | .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK, |
| 212 | }, |
| 213 | }; |
| 214 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 215 | struct pmx_dev spear320_pmx_uart1 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 216 | .name = "uart1", |
| 217 | .modes = pmx_uart1_modes, |
| 218 | .mode_count = ARRAY_SIZE(pmx_uart1_modes), |
| 219 | .enb_on_reset = 1, |
| 220 | }; |
| 221 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 222 | static struct pmx_dev_mode pmx_uart1_modem_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 223 | { |
| 224 | .ids = AUTO_EXP_MODE, |
| 225 | .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | |
| 226 | PMX_SSP_CS_MASK, |
| 227 | }, { |
| 228 | .ids = SMALL_PRINTERS_MODE, |
| 229 | .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK | |
| 230 | PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK, |
| 231 | }, |
| 232 | }; |
| 233 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 234 | struct pmx_dev spear320_pmx_uart1_modem = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 235 | .name = "uart1_modem", |
| 236 | .modes = pmx_uart1_modem_modes, |
| 237 | .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes), |
| 238 | .enb_on_reset = 1, |
| 239 | }; |
| 240 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 241 | static struct pmx_dev_mode pmx_uart2_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 242 | { |
| 243 | .ids = ALL_MODES, |
| 244 | .mask = PMX_FIRDA_MASK, |
| 245 | }, |
| 246 | }; |
| 247 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 248 | struct pmx_dev spear320_pmx_uart2 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 249 | .name = "uart2", |
| 250 | .modes = pmx_uart2_modes, |
| 251 | .mode_count = ARRAY_SIZE(pmx_uart2_modes), |
| 252 | .enb_on_reset = 1, |
| 253 | }; |
| 254 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 255 | static struct pmx_dev_mode pmx_touchscreen_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 256 | { |
| 257 | .ids = AUTO_NET_SMII_MODE, |
| 258 | .mask = PMX_SSP_CS_MASK, |
| 259 | }, |
| 260 | }; |
| 261 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 262 | struct pmx_dev spear320_pmx_touchscreen = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 263 | .name = "touchscreen", |
| 264 | .modes = pmx_touchscreen_modes, |
| 265 | .mode_count = ARRAY_SIZE(pmx_touchscreen_modes), |
| 266 | .enb_on_reset = 1, |
| 267 | }; |
| 268 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 269 | static struct pmx_dev_mode pmx_can_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 270 | { |
| 271 | .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE, |
| 272 | .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | |
| 273 | PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK, |
| 274 | }, |
| 275 | }; |
| 276 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 277 | struct pmx_dev spear320_pmx_can = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 278 | .name = "can", |
| 279 | .modes = pmx_can_modes, |
| 280 | .mode_count = ARRAY_SIZE(pmx_can_modes), |
| 281 | .enb_on_reset = 1, |
| 282 | }; |
| 283 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 284 | static struct pmx_dev_mode pmx_sdhci_led_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 285 | { |
| 286 | .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, |
| 287 | .mask = PMX_SSP_CS_MASK, |
| 288 | }, |
| 289 | }; |
| 290 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 291 | struct pmx_dev spear320_pmx_sdhci_led = { |
viresh kumar | 069580b | 2011-03-07 05:57:03 +0100 | [diff] [blame] | 292 | .name = "sdhci_led", |
| 293 | .modes = pmx_sdhci_led_modes, |
| 294 | .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes), |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 295 | .enb_on_reset = 1, |
| 296 | }; |
| 297 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 298 | static struct pmx_dev_mode pmx_pwm0_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 299 | { |
| 300 | .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, |
| 301 | .mask = PMX_UART0_MODEM_MASK, |
| 302 | }, { |
| 303 | .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE, |
| 304 | .mask = PMX_MII_MASK, |
| 305 | }, |
| 306 | }; |
| 307 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 308 | struct pmx_dev spear320_pmx_pwm0 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 309 | .name = "pwm0", |
| 310 | .modes = pmx_pwm0_modes, |
| 311 | .mode_count = ARRAY_SIZE(pmx_pwm0_modes), |
| 312 | .enb_on_reset = 1, |
| 313 | }; |
| 314 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 315 | static struct pmx_dev_mode pmx_pwm1_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 316 | { |
| 317 | .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, |
| 318 | .mask = PMX_UART0_MODEM_MASK, |
| 319 | }, { |
| 320 | .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE, |
| 321 | .mask = PMX_MII_MASK, |
| 322 | }, |
| 323 | }; |
| 324 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 325 | struct pmx_dev spear320_pmx_pwm1 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 326 | .name = "pwm1", |
| 327 | .modes = pmx_pwm1_modes, |
| 328 | .mode_count = ARRAY_SIZE(pmx_pwm1_modes), |
| 329 | .enb_on_reset = 1, |
| 330 | }; |
| 331 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 332 | static struct pmx_dev_mode pmx_pwm2_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 333 | { |
| 334 | .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, |
| 335 | .mask = PMX_SSP_CS_MASK, |
| 336 | }, { |
| 337 | .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE, |
| 338 | .mask = PMX_MII_MASK, |
| 339 | }, |
| 340 | }; |
| 341 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 342 | struct pmx_dev spear320_pmx_pwm2 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 343 | .name = "pwm2", |
| 344 | .modes = pmx_pwm2_modes, |
| 345 | .mode_count = ARRAY_SIZE(pmx_pwm2_modes), |
| 346 | .enb_on_reset = 1, |
| 347 | }; |
| 348 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 349 | static struct pmx_dev_mode pmx_pwm3_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 350 | { |
| 351 | .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE, |
| 352 | .mask = PMX_MII_MASK, |
| 353 | }, |
| 354 | }; |
| 355 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 356 | struct pmx_dev spear320_pmx_pwm3 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 357 | .name = "pwm3", |
| 358 | .modes = pmx_pwm3_modes, |
| 359 | .mode_count = ARRAY_SIZE(pmx_pwm3_modes), |
| 360 | .enb_on_reset = 1, |
| 361 | }; |
| 362 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 363 | static struct pmx_dev_mode pmx_ssp1_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 364 | { |
| 365 | .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE, |
| 366 | .mask = PMX_MII_MASK, |
| 367 | }, |
| 368 | }; |
| 369 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 370 | struct pmx_dev spear320_pmx_ssp1 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 371 | .name = "ssp1", |
| 372 | .modes = pmx_ssp1_modes, |
| 373 | .mode_count = ARRAY_SIZE(pmx_ssp1_modes), |
| 374 | .enb_on_reset = 1, |
| 375 | }; |
| 376 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 377 | static struct pmx_dev_mode pmx_ssp2_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 378 | { |
| 379 | .ids = AUTO_NET_SMII_MODE, |
| 380 | .mask = PMX_MII_MASK, |
| 381 | }, |
| 382 | }; |
| 383 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 384 | struct pmx_dev spear320_pmx_ssp2 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 385 | .name = "ssp2", |
| 386 | .modes = pmx_ssp2_modes, |
| 387 | .mode_count = ARRAY_SIZE(pmx_ssp2_modes), |
| 388 | .enb_on_reset = 1, |
| 389 | }; |
| 390 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 391 | static struct pmx_dev_mode pmx_mii1_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 392 | { |
| 393 | .ids = AUTO_NET_MII_MODE, |
| 394 | .mask = 0x0, |
| 395 | }, |
| 396 | }; |
| 397 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 398 | struct pmx_dev spear320_pmx_mii1 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 399 | .name = "mii1", |
| 400 | .modes = pmx_mii1_modes, |
| 401 | .mode_count = ARRAY_SIZE(pmx_mii1_modes), |
| 402 | .enb_on_reset = 1, |
| 403 | }; |
| 404 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 405 | static struct pmx_dev_mode pmx_smii0_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 406 | { |
| 407 | .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE, |
| 408 | .mask = PMX_MII_MASK, |
| 409 | }, |
| 410 | }; |
| 411 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 412 | struct pmx_dev spear320_pmx_smii0 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 413 | .name = "smii0", |
| 414 | .modes = pmx_smii0_modes, |
| 415 | .mode_count = ARRAY_SIZE(pmx_smii0_modes), |
| 416 | .enb_on_reset = 1, |
| 417 | }; |
| 418 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 419 | static struct pmx_dev_mode pmx_smii1_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 420 | { |
| 421 | .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE, |
| 422 | .mask = PMX_MII_MASK, |
| 423 | }, |
| 424 | }; |
| 425 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 426 | struct pmx_dev spear320_pmx_smii1 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 427 | .name = "smii1", |
| 428 | .modes = pmx_smii1_modes, |
| 429 | .mode_count = ARRAY_SIZE(pmx_smii1_modes), |
| 430 | .enb_on_reset = 1, |
| 431 | }; |
| 432 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 433 | static struct pmx_dev_mode pmx_i2c1_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 434 | { |
| 435 | .ids = AUTO_EXP_MODE, |
| 436 | .mask = 0x0, |
| 437 | }, |
| 438 | }; |
| 439 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 440 | struct pmx_dev spear320_pmx_i2c1 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 441 | .name = "i2c1", |
| 442 | .modes = pmx_i2c1_modes, |
| 443 | .mode_count = ARRAY_SIZE(pmx_i2c1_modes), |
| 444 | .enb_on_reset = 1, |
| 445 | }; |
| 446 | |
| 447 | /* pmx driver structure */ |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 448 | static struct pmx_driver pmx_driver = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 449 | .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007}, |
| 450 | .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, |
| 451 | }; |
| 452 | |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 453 | /* spear3xx shared irq */ |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 454 | static struct shirq_dev_config shirq_ras1_config[] = { |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 455 | { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 456 | .virq = SPEAR320_VIRQ_EMI, |
| 457 | .status_mask = SPEAR320_EMI_IRQ_MASK, |
| 458 | .clear_mask = SPEAR320_EMI_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 459 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 460 | .virq = SPEAR320_VIRQ_CLCD, |
| 461 | .status_mask = SPEAR320_CLCD_IRQ_MASK, |
| 462 | .clear_mask = SPEAR320_CLCD_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 463 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 464 | .virq = SPEAR320_VIRQ_SPP, |
| 465 | .status_mask = SPEAR320_SPP_IRQ_MASK, |
| 466 | .clear_mask = SPEAR320_SPP_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 467 | }, |
| 468 | }; |
| 469 | |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 470 | static struct spear_shirq shirq_ras1 = { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 471 | .irq = SPEAR3XX_IRQ_GEN_RAS_1, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 472 | .dev_config = shirq_ras1_config, |
| 473 | .dev_count = ARRAY_SIZE(shirq_ras1_config), |
| 474 | .regs = { |
| 475 | .enb_reg = -1, |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 476 | .status_reg = SPEAR320_INT_STS_MASK_REG, |
| 477 | .status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK, |
| 478 | .clear_reg = SPEAR320_INT_CLR_MASK_REG, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 479 | .reset_to_clear = 1, |
| 480 | }, |
| 481 | }; |
| 482 | |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 483 | static struct shirq_dev_config shirq_ras3_config[] = { |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 484 | { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 485 | .virq = SPEAR320_VIRQ_PLGPIO, |
| 486 | .enb_mask = SPEAR320_GPIO_IRQ_MASK, |
| 487 | .status_mask = SPEAR320_GPIO_IRQ_MASK, |
| 488 | .clear_mask = SPEAR320_GPIO_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 489 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 490 | .virq = SPEAR320_VIRQ_I2S_PLAY, |
| 491 | .enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK, |
| 492 | .status_mask = SPEAR320_I2S_PLAY_IRQ_MASK, |
| 493 | .clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 494 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 495 | .virq = SPEAR320_VIRQ_I2S_REC, |
| 496 | .enb_mask = SPEAR320_I2S_REC_IRQ_MASK, |
| 497 | .status_mask = SPEAR320_I2S_REC_IRQ_MASK, |
| 498 | .clear_mask = SPEAR320_I2S_REC_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 499 | }, |
| 500 | }; |
| 501 | |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 502 | static struct spear_shirq shirq_ras3 = { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 503 | .irq = SPEAR3XX_IRQ_GEN_RAS_3, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 504 | .dev_config = shirq_ras3_config, |
| 505 | .dev_count = ARRAY_SIZE(shirq_ras3_config), |
| 506 | .regs = { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 507 | .enb_reg = SPEAR320_INT_ENB_MASK_REG, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 508 | .reset_to_enb = 1, |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 509 | .status_reg = SPEAR320_INT_STS_MASK_REG, |
| 510 | .status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK, |
| 511 | .clear_reg = SPEAR320_INT_CLR_MASK_REG, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 512 | .reset_to_clear = 1, |
| 513 | }, |
| 514 | }; |
| 515 | |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 516 | static struct shirq_dev_config shirq_intrcomm_ras_config[] = { |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 517 | { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 518 | .virq = SPEAR320_VIRQ_CANU, |
| 519 | .status_mask = SPEAR320_CAN_U_IRQ_MASK, |
| 520 | .clear_mask = SPEAR320_CAN_U_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 521 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 522 | .virq = SPEAR320_VIRQ_CANL, |
| 523 | .status_mask = SPEAR320_CAN_L_IRQ_MASK, |
| 524 | .clear_mask = SPEAR320_CAN_L_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 525 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 526 | .virq = SPEAR320_VIRQ_UART1, |
| 527 | .status_mask = SPEAR320_UART1_IRQ_MASK, |
| 528 | .clear_mask = SPEAR320_UART1_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 529 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 530 | .virq = SPEAR320_VIRQ_UART2, |
| 531 | .status_mask = SPEAR320_UART2_IRQ_MASK, |
| 532 | .clear_mask = SPEAR320_UART2_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 533 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 534 | .virq = SPEAR320_VIRQ_SSP1, |
| 535 | .status_mask = SPEAR320_SSP1_IRQ_MASK, |
| 536 | .clear_mask = SPEAR320_SSP1_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 537 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 538 | .virq = SPEAR320_VIRQ_SSP2, |
| 539 | .status_mask = SPEAR320_SSP2_IRQ_MASK, |
| 540 | .clear_mask = SPEAR320_SSP2_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 541 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 542 | .virq = SPEAR320_VIRQ_SMII0, |
| 543 | .status_mask = SPEAR320_SMII0_IRQ_MASK, |
| 544 | .clear_mask = SPEAR320_SMII0_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 545 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 546 | .virq = SPEAR320_VIRQ_MII1_SMII1, |
| 547 | .status_mask = SPEAR320_MII1_SMII1_IRQ_MASK, |
| 548 | .clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 549 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 550 | .virq = SPEAR320_VIRQ_WAKEUP_SMII0, |
| 551 | .status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK, |
| 552 | .clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 553 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 554 | .virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1, |
| 555 | .status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK, |
| 556 | .clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 557 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 558 | .virq = SPEAR320_VIRQ_I2C1, |
| 559 | .status_mask = SPEAR320_I2C1_IRQ_MASK, |
| 560 | .clear_mask = SPEAR320_I2C1_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 561 | }, |
| 562 | }; |
| 563 | |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 564 | static struct spear_shirq shirq_intrcomm_ras = { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 565 | .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 566 | .dev_config = shirq_intrcomm_ras_config, |
| 567 | .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config), |
| 568 | .regs = { |
| 569 | .enb_reg = -1, |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 570 | .status_reg = SPEAR320_INT_STS_MASK_REG, |
| 571 | .status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK, |
| 572 | .clear_reg = SPEAR320_INT_CLR_MASK_REG, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 573 | .reset_to_clear = 1, |
| 574 | }, |
| 575 | }; |
| 576 | |
Viresh Kumar | c5fa4fd | 2012-03-23 00:17:43 +0530 | [diff] [blame] | 577 | /* padmux devices to enable */ |
| 578 | static struct pmx_dev *spear320_evb_pmx_devs[] = { |
| 579 | /* spear3xx specific devices */ |
| 580 | &spear3xx_pmx_i2c, |
| 581 | &spear3xx_pmx_ssp, |
| 582 | &spear3xx_pmx_mii, |
| 583 | &spear3xx_pmx_uart0, |
viresh kumar | c2c0783 | 2011-03-07 05:57:05 +0100 | [diff] [blame] | 584 | |
Viresh Kumar | c5fa4fd | 2012-03-23 00:17:43 +0530 | [diff] [blame] | 585 | /* spear320 specific devices */ |
| 586 | &spear320_pmx_fsmc, |
| 587 | &spear320_pmx_sdhci, |
| 588 | &spear320_pmx_i2s, |
| 589 | &spear320_pmx_uart1, |
| 590 | &spear320_pmx_uart2, |
| 591 | &spear320_pmx_can, |
| 592 | &spear320_pmx_pwm0, |
| 593 | &spear320_pmx_pwm1, |
| 594 | &spear320_pmx_pwm2, |
| 595 | &spear320_pmx_mii1, |
| 596 | }; |
| 597 | |
Viresh Kumar | 0b7ee71 | 2012-03-26 10:29:23 +0530 | [diff] [blame] | 598 | /* DMAC platform data's slave info */ |
| 599 | struct pl08x_channel_data spear320_dma_info[] = { |
| 600 | { |
| 601 | .bus_id = "uart0_rx", |
| 602 | .min_signal = 2, |
| 603 | .max_signal = 2, |
| 604 | .muxval = 0, |
| 605 | .cctl = 0, |
| 606 | .periph_buses = PL08X_AHB1, |
| 607 | }, { |
| 608 | .bus_id = "uart0_tx", |
| 609 | .min_signal = 3, |
| 610 | .max_signal = 3, |
| 611 | .muxval = 0, |
| 612 | .cctl = 0, |
| 613 | .periph_buses = PL08X_AHB1, |
| 614 | }, { |
| 615 | .bus_id = "ssp0_rx", |
| 616 | .min_signal = 8, |
| 617 | .max_signal = 8, |
| 618 | .muxval = 0, |
| 619 | .cctl = 0, |
| 620 | .periph_buses = PL08X_AHB1, |
| 621 | }, { |
| 622 | .bus_id = "ssp0_tx", |
| 623 | .min_signal = 9, |
| 624 | .max_signal = 9, |
| 625 | .muxval = 0, |
| 626 | .cctl = 0, |
| 627 | .periph_buses = PL08X_AHB1, |
| 628 | }, { |
| 629 | .bus_id = "i2c0_rx", |
| 630 | .min_signal = 10, |
| 631 | .max_signal = 10, |
| 632 | .muxval = 0, |
| 633 | .cctl = 0, |
| 634 | .periph_buses = PL08X_AHB1, |
| 635 | }, { |
| 636 | .bus_id = "i2c0_tx", |
| 637 | .min_signal = 11, |
| 638 | .max_signal = 11, |
| 639 | .muxval = 0, |
| 640 | .cctl = 0, |
| 641 | .periph_buses = PL08X_AHB1, |
| 642 | }, { |
| 643 | .bus_id = "irda", |
| 644 | .min_signal = 12, |
| 645 | .max_signal = 12, |
| 646 | .muxval = 0, |
| 647 | .cctl = 0, |
| 648 | .periph_buses = PL08X_AHB1, |
| 649 | }, { |
| 650 | .bus_id = "adc", |
| 651 | .min_signal = 13, |
| 652 | .max_signal = 13, |
| 653 | .muxval = 0, |
| 654 | .cctl = 0, |
| 655 | .periph_buses = PL08X_AHB1, |
| 656 | }, { |
| 657 | .bus_id = "to_jpeg", |
| 658 | .min_signal = 14, |
| 659 | .max_signal = 14, |
| 660 | .muxval = 0, |
| 661 | .cctl = 0, |
| 662 | .periph_buses = PL08X_AHB1, |
| 663 | }, { |
| 664 | .bus_id = "from_jpeg", |
| 665 | .min_signal = 15, |
| 666 | .max_signal = 15, |
| 667 | .muxval = 0, |
| 668 | .cctl = 0, |
| 669 | .periph_buses = PL08X_AHB1, |
| 670 | }, { |
| 671 | .bus_id = "ssp1_rx", |
| 672 | .min_signal = 0, |
| 673 | .max_signal = 0, |
| 674 | .muxval = 1, |
| 675 | .cctl = 0, |
| 676 | .periph_buses = PL08X_AHB2, |
| 677 | }, { |
| 678 | .bus_id = "ssp1_tx", |
| 679 | .min_signal = 1, |
| 680 | .max_signal = 1, |
| 681 | .muxval = 1, |
| 682 | .cctl = 0, |
| 683 | .periph_buses = PL08X_AHB2, |
| 684 | }, { |
| 685 | .bus_id = "ssp2_rx", |
| 686 | .min_signal = 2, |
| 687 | .max_signal = 2, |
| 688 | .muxval = 1, |
| 689 | .cctl = 0, |
| 690 | .periph_buses = PL08X_AHB2, |
| 691 | }, { |
| 692 | .bus_id = "ssp2_tx", |
| 693 | .min_signal = 3, |
| 694 | .max_signal = 3, |
| 695 | .muxval = 1, |
| 696 | .cctl = 0, |
| 697 | .periph_buses = PL08X_AHB2, |
| 698 | }, { |
| 699 | .bus_id = "uart1_rx", |
| 700 | .min_signal = 4, |
| 701 | .max_signal = 4, |
| 702 | .muxval = 1, |
| 703 | .cctl = 0, |
| 704 | .periph_buses = PL08X_AHB2, |
| 705 | }, { |
| 706 | .bus_id = "uart1_tx", |
| 707 | .min_signal = 5, |
| 708 | .max_signal = 5, |
| 709 | .muxval = 1, |
| 710 | .cctl = 0, |
| 711 | .periph_buses = PL08X_AHB2, |
| 712 | }, { |
| 713 | .bus_id = "uart2_rx", |
| 714 | .min_signal = 6, |
| 715 | .max_signal = 6, |
| 716 | .muxval = 1, |
| 717 | .cctl = 0, |
| 718 | .periph_buses = PL08X_AHB2, |
| 719 | }, { |
| 720 | .bus_id = "uart2_tx", |
| 721 | .min_signal = 7, |
| 722 | .max_signal = 7, |
| 723 | .muxval = 1, |
| 724 | .cctl = 0, |
| 725 | .periph_buses = PL08X_AHB2, |
| 726 | }, { |
| 727 | .bus_id = "i2c1_rx", |
| 728 | .min_signal = 8, |
| 729 | .max_signal = 8, |
| 730 | .muxval = 1, |
| 731 | .cctl = 0, |
| 732 | .periph_buses = PL08X_AHB2, |
| 733 | }, { |
| 734 | .bus_id = "i2c1_tx", |
| 735 | .min_signal = 9, |
| 736 | .max_signal = 9, |
| 737 | .muxval = 1, |
| 738 | .cctl = 0, |
| 739 | .periph_buses = PL08X_AHB2, |
| 740 | }, { |
| 741 | .bus_id = "i2c2_rx", |
| 742 | .min_signal = 10, |
| 743 | .max_signal = 10, |
| 744 | .muxval = 1, |
| 745 | .cctl = 0, |
| 746 | .periph_buses = PL08X_AHB2, |
| 747 | }, { |
| 748 | .bus_id = "i2c2_tx", |
| 749 | .min_signal = 11, |
| 750 | .max_signal = 11, |
| 751 | .muxval = 1, |
| 752 | .cctl = 0, |
| 753 | .periph_buses = PL08X_AHB2, |
| 754 | }, { |
| 755 | .bus_id = "i2s_rx", |
| 756 | .min_signal = 12, |
| 757 | .max_signal = 12, |
| 758 | .muxval = 1, |
| 759 | .cctl = 0, |
| 760 | .periph_buses = PL08X_AHB2, |
| 761 | }, { |
| 762 | .bus_id = "i2s_tx", |
| 763 | .min_signal = 13, |
| 764 | .max_signal = 13, |
| 765 | .muxval = 1, |
| 766 | .cctl = 0, |
| 767 | .periph_buses = PL08X_AHB2, |
| 768 | }, { |
| 769 | .bus_id = "rs485_rx", |
| 770 | .min_signal = 14, |
| 771 | .max_signal = 14, |
| 772 | .muxval = 1, |
| 773 | .cctl = 0, |
| 774 | .periph_buses = PL08X_AHB2, |
| 775 | }, { |
| 776 | .bus_id = "rs485_tx", |
| 777 | .min_signal = 15, |
| 778 | .max_signal = 15, |
| 779 | .muxval = 1, |
| 780 | .cctl = 0, |
| 781 | .periph_buses = PL08X_AHB2, |
| 782 | }, |
| 783 | }; |
| 784 | |
Viresh Kumar | c5fa4fd | 2012-03-23 00:17:43 +0530 | [diff] [blame] | 785 | static struct pl022_ssp_controller spear320_ssp_data[] = { |
| 786 | { |
| 787 | .bus_id = 1, |
| 788 | .enable_dma = 1, |
| 789 | .dma_filter = pl08x_filter_id, |
| 790 | .dma_tx_param = "ssp1_tx", |
| 791 | .dma_rx_param = "ssp1_rx", |
| 792 | .num_chipselect = 2, |
| 793 | }, { |
| 794 | .bus_id = 2, |
| 795 | .enable_dma = 1, |
| 796 | .dma_filter = pl08x_filter_id, |
| 797 | .dma_tx_param = "ssp2_tx", |
| 798 | .dma_rx_param = "ssp2_rx", |
| 799 | .num_chipselect = 2, |
| 800 | } |
| 801 | }; |
| 802 | |
| 803 | static struct amba_pl011_data spear320_uart_data[] = { |
| 804 | { |
| 805 | .dma_filter = pl08x_filter_id, |
| 806 | .dma_tx_param = "uart1_tx", |
| 807 | .dma_rx_param = "uart1_rx", |
| 808 | }, { |
| 809 | .dma_filter = pl08x_filter_id, |
| 810 | .dma_tx_param = "uart2_tx", |
| 811 | .dma_rx_param = "uart2_rx", |
| 812 | }, |
| 813 | }; |
| 814 | |
| 815 | /* Add SPEAr310 auxdata to pass platform data */ |
| 816 | static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = { |
| 817 | OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, |
| 818 | &pl022_plat_data), |
Viresh Kumar | 0b7ee71 | 2012-03-26 10:29:23 +0530 | [diff] [blame] | 819 | OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL, |
| 820 | &pl080_plat_data), |
Viresh Kumar | c5fa4fd | 2012-03-23 00:17:43 +0530 | [diff] [blame] | 821 | OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL, |
| 822 | &spear320_ssp_data[0]), |
| 823 | OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL, |
| 824 | &spear320_ssp_data[1]), |
| 825 | OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL, |
| 826 | &spear320_uart_data[0]), |
| 827 | OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL, |
| 828 | &spear320_uart_data[1]), |
| 829 | {} |
| 830 | }; |
| 831 | |
| 832 | static void __init spear320_dt_init(void) |
viresh kumar | bc4e814 | 2010-04-01 12:30:58 +0100 | [diff] [blame] | 833 | { |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 834 | void __iomem *base; |
| 835 | int ret = 0; |
| 836 | |
Viresh Kumar | 0b7ee71 | 2012-03-26 10:29:23 +0530 | [diff] [blame] | 837 | pl080_plat_data.slave_channels = spear320_dma_info; |
| 838 | pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info); |
| 839 | |
Viresh Kumar | c5fa4fd | 2012-03-23 00:17:43 +0530 | [diff] [blame] | 840 | of_platform_populate(NULL, of_default_bus_match_table, |
| 841 | spear320_auxdata_lookup, NULL); |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 842 | |
Uwe Kleine-König | b595076 | 2010-11-01 15:38:34 -0400 | [diff] [blame] | 843 | /* shared irq registration */ |
viresh kumar | 5382116 | 2011-03-07 05:57:06 +0100 | [diff] [blame] | 844 | base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K); |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 845 | if (base) { |
| 846 | /* shirq 1 */ |
| 847 | shirq_ras1.regs.base = base; |
| 848 | ret = spear_shirq_register(&shirq_ras1); |
| 849 | if (ret) |
Viresh Kumar | 5fb00f9 | 2012-03-26 10:39:43 +0530 | [diff] [blame] | 850 | pr_err("Error registering Shared IRQ 1\n"); |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 851 | |
| 852 | /* shirq 3 */ |
| 853 | shirq_ras3.regs.base = base; |
| 854 | ret = spear_shirq_register(&shirq_ras3); |
| 855 | if (ret) |
Viresh Kumar | 5fb00f9 | 2012-03-26 10:39:43 +0530 | [diff] [blame] | 856 | pr_err("Error registering Shared IRQ 3\n"); |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 857 | |
| 858 | /* shirq 4 */ |
| 859 | shirq_intrcomm_ras.regs.base = base; |
| 860 | ret = spear_shirq_register(&shirq_intrcomm_ras); |
| 861 | if (ret) |
Viresh Kumar | 5fb00f9 | 2012-03-26 10:39:43 +0530 | [diff] [blame] | 862 | pr_err("Error registering Shared IRQ 4\n"); |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 863 | } |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 864 | |
Viresh Kumar | c5fa4fd | 2012-03-23 00:17:43 +0530 | [diff] [blame] | 865 | if (of_machine_is_compatible("st,spear320-evb")) { |
| 866 | /* pmx initialization */ |
| 867 | pmx_driver.base = base; |
| 868 | pmx_driver.mode = &spear320_auto_net_mii_mode; |
| 869 | pmx_driver.devs = spear320_evb_pmx_devs; |
| 870 | pmx_driver.devs_count = ARRAY_SIZE(spear320_evb_pmx_devs); |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 871 | |
Viresh Kumar | c5fa4fd | 2012-03-23 00:17:43 +0530 | [diff] [blame] | 872 | ret = pmx_register(&pmx_driver); |
| 873 | if (ret) |
| 874 | pr_err("padmux: registration failed. err no: %d\n", |
| 875 | ret); |
| 876 | } |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 877 | } |
Viresh Kumar | c5fa4fd | 2012-03-23 00:17:43 +0530 | [diff] [blame] | 878 | |
| 879 | static const char * const spear320_dt_board_compat[] = { |
| 880 | "st,spear320", |
| 881 | "st,spear320-evb", |
| 882 | NULL, |
| 883 | }; |
| 884 | |
| 885 | static void __init spear320_map_io(void) |
| 886 | { |
| 887 | spear3xx_map_io(); |
| 888 | spear320_clk_init(); |
| 889 | } |
| 890 | |
| 891 | DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree") |
| 892 | .map_io = spear320_map_io, |
| 893 | .init_irq = spear3xx_dt_init_irq, |
| 894 | .handle_irq = vic_handle_irq, |
| 895 | .timer = &spear3xx_timer, |
| 896 | .init_machine = spear320_dt_init, |
| 897 | .restart = spear_restart, |
| 898 | .dt_compat = spear320_dt_board_compat, |
| 899 | MACHINE_END |