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Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001/*
2 * omap iommu: tlb and pagetable primitives
3 *
Hiroshi DOYUc127c7d2010-02-15 10:03:32 -08004 * Copyright (C) 2008-2010 Nokia Corporation
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02005 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
7 * Paul Mundt and Toshihiro Kobayashi
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/err.h>
15#include <linux/module.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090016#include <linux/slab.h>
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020017#include <linux/interrupt.h>
18#include <linux/ioport.h>
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020019#include <linux/platform_device.h>
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +030020#include <linux/iommu.h>
Tony Lindgrenc8d35c82012-11-02 12:24:03 -070021#include <linux/omap-iommu.h>
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +030022#include <linux/mutex.h>
23#include <linux/spinlock.h>
Tony Lindgrened1c7de2012-11-02 12:24:06 -070024#include <linux/io.h>
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -060025#include <linux/pm_runtime.h>
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020026
27#include <asm/cacheflush.h>
28
Tony Lindgren2ab7c842012-11-02 12:24:14 -070029#include <linux/platform_data/iommu-omap.h>
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020030
Ido Yariv2f7702a2012-11-02 12:24:00 -070031#include "omap-iopgtable.h"
Tony Lindgrened1c7de2012-11-02 12:24:06 -070032#include "omap-iommu.h"
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020033
Hiroshi DOYU37c28362010-04-27 05:37:12 +000034#define for_each_iotlb_cr(obj, n, __i, cr) \
35 for (__i = 0; \
36 (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \
37 __i++)
38
Ohad Ben-Cohen66bc8cf2011-11-10 11:32:27 +020039/* bitmap of the page sizes currently supported */
40#define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M)
41
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +030042/**
43 * struct omap_iommu_domain - omap iommu domain
44 * @pgtable: the page table
45 * @iommu_dev: an omap iommu device attached to this domain. only a single
46 * iommu device can be attached for now.
Omar Ramirez Luna803b5272012-04-18 13:09:41 -050047 * @dev: Device using this domain.
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +030048 * @lock: domain lock, should be taken when attaching/detaching
49 */
50struct omap_iommu_domain {
51 u32 *pgtable;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +030052 struct omap_iommu *iommu_dev;
Omar Ramirez Luna803b5272012-04-18 13:09:41 -050053 struct device *dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +030054 spinlock_t lock;
55};
56
Ido Yariv7bd9e252012-11-02 12:24:09 -070057#define MMU_LOCK_BASE_SHIFT 10
58#define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT)
59#define MMU_LOCK_BASE(x) \
60 ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
61
62#define MMU_LOCK_VICT_SHIFT 4
63#define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT)
64#define MMU_LOCK_VICT(x) \
65 ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
66
67struct iotlb_lock {
68 short base;
69 short vict;
70};
71
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020072/* accommodate the difference between omap1 and omap2/3 */
73static const struct iommu_functions *arch_iommu;
74
75static struct platform_driver omap_iommu_driver;
76static struct kmem_cache *iopte_cachep;
77
78/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +030079 * omap_install_iommu_arch - Install archtecure specific iommu functions
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020080 * @ops: a pointer to architecture specific iommu functions
81 *
82 * There are several kind of iommu algorithm(tlb, pagetable) among
83 * omap series. This interface installs such an iommu algorighm.
84 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +030085int omap_install_iommu_arch(const struct iommu_functions *ops)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020086{
87 if (arch_iommu)
88 return -EBUSY;
89
90 arch_iommu = ops;
91 return 0;
92}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +030093EXPORT_SYMBOL_GPL(omap_install_iommu_arch);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020094
95/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +030096 * omap_uninstall_iommu_arch - Uninstall archtecure specific iommu functions
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020097 * @ops: a pointer to architecture specific iommu functions
98 *
99 * This interface uninstalls the iommu algorighm installed previously.
100 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300101void omap_uninstall_iommu_arch(const struct iommu_functions *ops)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200102{
103 if (arch_iommu != ops)
104 pr_err("%s: not your arch\n", __func__);
105
106 arch_iommu = NULL;
107}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300108EXPORT_SYMBOL_GPL(omap_uninstall_iommu_arch);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200109
110/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300111 * omap_iommu_save_ctx - Save registers for pm off-mode support
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200112 * @dev: client device
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200113 **/
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200114void omap_iommu_save_ctx(struct device *dev)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200115{
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200116 struct omap_iommu *obj = dev_to_omap_iommu(dev);
117
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200118 arch_iommu->save_ctx(obj);
119}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300120EXPORT_SYMBOL_GPL(omap_iommu_save_ctx);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200121
122/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300123 * omap_iommu_restore_ctx - Restore registers for pm off-mode support
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200124 * @dev: client device
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200125 **/
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200126void omap_iommu_restore_ctx(struct device *dev)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200127{
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200128 struct omap_iommu *obj = dev_to_omap_iommu(dev);
129
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200130 arch_iommu->restore_ctx(obj);
131}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300132EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200133
134/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300135 * omap_iommu_arch_version - Return running iommu arch version
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200136 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300137u32 omap_iommu_arch_version(void)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200138{
139 return arch_iommu->version;
140}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300141EXPORT_SYMBOL_GPL(omap_iommu_arch_version);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200142
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300143static int iommu_enable(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200144{
145 int err;
Omar Ramirez Luna72b15b62012-11-19 19:05:50 -0600146 struct platform_device *pdev = to_platform_device(obj->dev);
147 struct iommu_platform_data *pdata = pdev->dev.platform_data;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200148
Cong Ding0af125c2013-01-18 21:42:18 +0100149 if (!pdata)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200150 return -EINVAL;
151
Martin Hostettleref4815a2011-02-24 12:51:31 -0800152 if (!arch_iommu)
153 return -ENODEV;
154
Omar Ramirez Luna72b15b62012-11-19 19:05:50 -0600155 if (pdata->deassert_reset) {
156 err = pdata->deassert_reset(pdev, pdata->reset_name);
157 if (err) {
158 dev_err(obj->dev, "deassert_reset failed: %d\n", err);
159 return err;
160 }
161 }
162
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600163 pm_runtime_get_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200164
165 err = arch_iommu->enable(obj);
166
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200167 return err;
168}
169
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300170static void iommu_disable(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200171{
Omar Ramirez Luna72b15b62012-11-19 19:05:50 -0600172 struct platform_device *pdev = to_platform_device(obj->dev);
173 struct iommu_platform_data *pdata = pdev->dev.platform_data;
174
Cong Ding0af125c2013-01-18 21:42:18 +0100175 if (!pdata)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200176 return;
177
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200178 arch_iommu->disable(obj);
179
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600180 pm_runtime_put_sync(obj->dev);
Omar Ramirez Luna72b15b62012-11-19 19:05:50 -0600181
182 if (pdata->assert_reset)
183 pdata->assert_reset(pdev, pdata->reset_name);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200184}
185
186/*
187 * TLB operations
188 */
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300189void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200190{
191 BUG_ON(!cr || !e);
192
193 arch_iommu->cr_to_e(cr, e);
194}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300195EXPORT_SYMBOL_GPL(omap_iotlb_cr_to_e);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200196
197static inline int iotlb_cr_valid(struct cr_regs *cr)
198{
199 if (!cr)
200 return -EINVAL;
201
202 return arch_iommu->cr_valid(cr);
203}
204
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300205static inline struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj,
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200206 struct iotlb_entry *e)
207{
208 if (!e)
209 return NULL;
210
211 return arch_iommu->alloc_cr(obj, e);
212}
213
Ohad Ben-Cohene1f23812011-08-16 14:58:14 +0300214static u32 iotlb_cr_to_virt(struct cr_regs *cr)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200215{
216 return arch_iommu->cr_to_virt(cr);
217}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200218
219static u32 get_iopte_attr(struct iotlb_entry *e)
220{
221 return arch_iommu->get_pte_attr(e);
222}
223
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300224static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200225{
226 return arch_iommu->fault_isr(obj, da);
227}
228
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300229static void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200230{
231 u32 val;
232
233 val = iommu_read_reg(obj, MMU_LOCK);
234
235 l->base = MMU_LOCK_BASE(val);
236 l->vict = MMU_LOCK_VICT(val);
237
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200238}
239
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300240static void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200241{
242 u32 val;
243
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200244 val = (l->base << MMU_LOCK_BASE_SHIFT);
245 val |= (l->vict << MMU_LOCK_VICT_SHIFT);
246
247 iommu_write_reg(obj, val, MMU_LOCK);
248}
249
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300250static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200251{
252 arch_iommu->tlb_read_cr(obj, cr);
253}
254
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300255static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200256{
257 arch_iommu->tlb_load_cr(obj, cr);
258
259 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
260 iommu_write_reg(obj, 1, MMU_LD_TLB);
261}
262
263/**
264 * iotlb_dump_cr - Dump an iommu tlb entry into buf
265 * @obj: target iommu
266 * @cr: contents of cam and ram register
267 * @buf: output buffer
268 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300269static inline ssize_t iotlb_dump_cr(struct omap_iommu *obj, struct cr_regs *cr,
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200270 char *buf)
271{
272 BUG_ON(!cr || !buf);
273
274 return arch_iommu->dump_cr(obj, cr, buf);
275}
276
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000277/* only used in iotlb iteration for-loop */
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300278static struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n)
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000279{
280 struct cr_regs cr;
281 struct iotlb_lock l;
282
283 iotlb_lock_get(obj, &l);
284 l.vict = n;
285 iotlb_lock_set(obj, &l);
286 iotlb_read_cr(obj, &cr);
287
288 return cr;
289}
290
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200291/**
292 * load_iotlb_entry - Set an iommu tlb entry
293 * @obj: target iommu
294 * @e: an iommu tlb entry info
295 **/
Ohad Ben-Cohen5da14a42011-08-16 15:19:10 +0300296#ifdef PREFETCH_IOTLB
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300297static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200298{
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200299 int err = 0;
300 struct iotlb_lock l;
301 struct cr_regs *cr;
302
303 if (!obj || !obj->nr_tlb_entries || !e)
304 return -EINVAL;
305
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600306 pm_runtime_get_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200307
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000308 iotlb_lock_get(obj, &l);
309 if (l.base == obj->nr_tlb_entries) {
310 dev_warn(obj->dev, "%s: preserve entries full\n", __func__);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200311 err = -EBUSY;
312 goto out;
313 }
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000314 if (!e->prsvd) {
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000315 int i;
316 struct cr_regs tmp;
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000317
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000318 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp)
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000319 if (!iotlb_cr_valid(&tmp))
320 break;
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000321
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000322 if (i == obj->nr_tlb_entries) {
323 dev_dbg(obj->dev, "%s: full: no entry\n", __func__);
324 err = -EBUSY;
325 goto out;
326 }
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000327
328 iotlb_lock_get(obj, &l);
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000329 } else {
330 l.vict = l.base;
331 iotlb_lock_set(obj, &l);
332 }
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200333
334 cr = iotlb_alloc_cr(obj, e);
335 if (IS_ERR(cr)) {
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600336 pm_runtime_put_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200337 return PTR_ERR(cr);
338 }
339
340 iotlb_load_cr(obj, cr);
341 kfree(cr);
342
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000343 if (e->prsvd)
344 l.base++;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200345 /* increment victim for next tlb load */
346 if (++l.vict == obj->nr_tlb_entries)
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000347 l.vict = l.base;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200348 iotlb_lock_set(obj, &l);
349out:
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600350 pm_runtime_put_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200351 return err;
352}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200353
Ohad Ben-Cohen5da14a42011-08-16 15:19:10 +0300354#else /* !PREFETCH_IOTLB */
355
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300356static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
Ohad Ben-Cohen5da14a42011-08-16 15:19:10 +0300357{
358 return 0;
359}
360
361#endif /* !PREFETCH_IOTLB */
362
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300363static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
Ohad Ben-Cohen5da14a42011-08-16 15:19:10 +0300364{
365 return load_iotlb_entry(obj, e);
366}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200367
368/**
369 * flush_iotlb_page - Clear an iommu tlb entry
370 * @obj: target iommu
371 * @da: iommu device virtual address
372 *
373 * Clear an iommu tlb entry which includes 'da' address.
374 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300375static void flush_iotlb_page(struct omap_iommu *obj, u32 da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200376{
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200377 int i;
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000378 struct cr_regs cr;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200379
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600380 pm_runtime_get_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200381
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000382 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) {
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200383 u32 start;
384 size_t bytes;
385
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200386 if (!iotlb_cr_valid(&cr))
387 continue;
388
389 start = iotlb_cr_to_virt(&cr);
390 bytes = iopgsz_to_bytes(cr.cam & 3);
391
392 if ((start <= da) && (da < start + bytes)) {
393 dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
394 __func__, start, da, bytes);
Hari Kanigeri0fa035e2010-08-20 13:50:18 +0000395 iotlb_load_cr(obj, &cr);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200396 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
397 }
398 }
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600399 pm_runtime_put_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200400
401 if (i == obj->nr_tlb_entries)
402 dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da);
403}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200404
405/**
406 * flush_iotlb_all - Clear all iommu tlb entries
407 * @obj: target iommu
408 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300409static void flush_iotlb_all(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200410{
411 struct iotlb_lock l;
412
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600413 pm_runtime_get_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200414
415 l.base = 0;
416 l.vict = 0;
417 iotlb_lock_set(obj, &l);
418
419 iommu_write_reg(obj, 1, MMU_GFLUSH);
420
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600421 pm_runtime_put_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200422}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200423
Arnd Bergmanne4efd942011-10-02 14:34:05 -0400424#if defined(CONFIG_OMAP_IOMMU_DEBUG) || defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE)
Kanigeri, Hariddfa9752010-05-24 02:01:51 +0000425
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300426ssize_t omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t bytes)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200427{
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200428 if (!obj || !buf)
429 return -EINVAL;
430
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600431 pm_runtime_get_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200432
Hiroshi DOYU14e0e672009-08-28 10:54:41 -0700433 bytes = arch_iommu->dump_ctx(obj, buf, bytes);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200434
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600435 pm_runtime_put_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200436
437 return bytes;
438}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300439EXPORT_SYMBOL_GPL(omap_iommu_dump_ctx);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200440
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300441static int
442__dump_tlb_entries(struct omap_iommu *obj, struct cr_regs *crs, int num)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200443{
444 int i;
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000445 struct iotlb_lock saved;
446 struct cr_regs tmp;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200447 struct cr_regs *p = crs;
448
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600449 pm_runtime_get_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200450 iotlb_lock_get(obj, &saved);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200451
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000452 for_each_iotlb_cr(obj, num, i, tmp) {
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200453 if (!iotlb_cr_valid(&tmp))
454 continue;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200455 *p++ = tmp;
456 }
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000457
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200458 iotlb_lock_set(obj, &saved);
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600459 pm_runtime_put_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200460
461 return p - crs;
462}
463
464/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300465 * omap_dump_tlb_entries - dump cr arrays to given buffer
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200466 * @obj: target iommu
467 * @buf: output buffer
468 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300469size_t omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t bytes)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200470{
Hiroshi DOYU14e0e672009-08-28 10:54:41 -0700471 int i, num;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200472 struct cr_regs *cr;
473 char *p = buf;
474
Hiroshi DOYU14e0e672009-08-28 10:54:41 -0700475 num = bytes / sizeof(*cr);
476 num = min(obj->nr_tlb_entries, num);
477
478 cr = kcalloc(num, sizeof(*cr), GFP_KERNEL);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200479 if (!cr)
480 return 0;
481
Hiroshi DOYU14e0e672009-08-28 10:54:41 -0700482 num = __dump_tlb_entries(obj, cr, num);
483 for (i = 0; i < num; i++)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200484 p += iotlb_dump_cr(obj, cr + i, p);
485 kfree(cr);
486
487 return p - buf;
488}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300489EXPORT_SYMBOL_GPL(omap_dump_tlb_entries);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200490
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300491int omap_foreach_iommu_device(void *data, int (*fn)(struct device *, void *))
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200492{
493 return driver_for_each_device(&omap_iommu_driver.driver,
494 NULL, data, fn);
495}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300496EXPORT_SYMBOL_GPL(omap_foreach_iommu_device);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200497
498#endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */
499
500/*
501 * H/W pagetable operations
502 */
503static void flush_iopgd_range(u32 *first, u32 *last)
504{
505 /* FIXME: L2 cache should be taken care of if it exists */
506 do {
507 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd"
508 : : "r" (first));
509 first += L1_CACHE_BYTES / sizeof(*first);
510 } while (first <= last);
511}
512
513static void flush_iopte_range(u32 *first, u32 *last)
514{
515 /* FIXME: L2 cache should be taken care of if it exists */
516 do {
517 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte"
518 : : "r" (first));
519 first += L1_CACHE_BYTES / sizeof(*first);
520 } while (first <= last);
521}
522
523static void iopte_free(u32 *iopte)
524{
525 /* Note: freed iopte's must be clean ready for re-use */
526 kmem_cache_free(iopte_cachep, iopte);
527}
528
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300529static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, u32 da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200530{
531 u32 *iopte;
532
533 /* a table has already existed */
534 if (*iopgd)
535 goto pte_ready;
536
537 /*
538 * do the allocation outside the page table lock
539 */
540 spin_unlock(&obj->page_table_lock);
541 iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL);
542 spin_lock(&obj->page_table_lock);
543
544 if (!*iopgd) {
545 if (!iopte)
546 return ERR_PTR(-ENOMEM);
547
548 *iopgd = virt_to_phys(iopte) | IOPGD_TABLE;
549 flush_iopgd_range(iopgd, iopgd);
550
551 dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte);
552 } else {
553 /* We raced, free the reduniovant table */
554 iopte_free(iopte);
555 }
556
557pte_ready:
558 iopte = iopte_offset(iopgd, da);
559
560 dev_vdbg(obj->dev,
561 "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
562 __func__, da, iopgd, *iopgd, iopte, *iopte);
563
564 return iopte;
565}
566
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300567static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200568{
569 u32 *iopgd = iopgd_offset(obj, da);
570
Hiroshi DOYU4abb7612010-05-06 18:24:04 +0300571 if ((da | pa) & ~IOSECTION_MASK) {
572 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
573 __func__, da, pa, IOSECTION_SIZE);
574 return -EINVAL;
575 }
576
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200577 *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION;
578 flush_iopgd_range(iopgd, iopgd);
579 return 0;
580}
581
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300582static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200583{
584 u32 *iopgd = iopgd_offset(obj, da);
585 int i;
586
Hiroshi DOYU4abb7612010-05-06 18:24:04 +0300587 if ((da | pa) & ~IOSUPER_MASK) {
588 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
589 __func__, da, pa, IOSUPER_SIZE);
590 return -EINVAL;
591 }
592
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200593 for (i = 0; i < 16; i++)
594 *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER;
595 flush_iopgd_range(iopgd, iopgd + 15);
596 return 0;
597}
598
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300599static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200600{
601 u32 *iopgd = iopgd_offset(obj, da);
602 u32 *iopte = iopte_alloc(obj, iopgd, da);
603
604 if (IS_ERR(iopte))
605 return PTR_ERR(iopte);
606
607 *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL;
608 flush_iopte_range(iopte, iopte);
609
610 dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n",
611 __func__, da, pa, iopte, *iopte);
612
613 return 0;
614}
615
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300616static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200617{
618 u32 *iopgd = iopgd_offset(obj, da);
619 u32 *iopte = iopte_alloc(obj, iopgd, da);
620 int i;
621
Hiroshi DOYU4abb7612010-05-06 18:24:04 +0300622 if ((da | pa) & ~IOLARGE_MASK) {
623 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
624 __func__, da, pa, IOLARGE_SIZE);
625 return -EINVAL;
626 }
627
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200628 if (IS_ERR(iopte))
629 return PTR_ERR(iopte);
630
631 for (i = 0; i < 16; i++)
632 *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE;
633 flush_iopte_range(iopte, iopte + 15);
634 return 0;
635}
636
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300637static int
638iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200639{
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300640 int (*fn)(struct omap_iommu *, u32, u32, u32);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200641 u32 prot;
642 int err;
643
644 if (!obj || !e)
645 return -EINVAL;
646
647 switch (e->pgsz) {
648 case MMU_CAM_PGSZ_16M:
649 fn = iopgd_alloc_super;
650 break;
651 case MMU_CAM_PGSZ_1M:
652 fn = iopgd_alloc_section;
653 break;
654 case MMU_CAM_PGSZ_64K:
655 fn = iopte_alloc_large;
656 break;
657 case MMU_CAM_PGSZ_4K:
658 fn = iopte_alloc_page;
659 break;
660 default:
661 fn = NULL;
662 BUG();
663 break;
664 }
665
666 prot = get_iopte_attr(e);
667
668 spin_lock(&obj->page_table_lock);
669 err = fn(obj, e->da, e->pa, prot);
670 spin_unlock(&obj->page_table_lock);
671
672 return err;
673}
674
675/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300676 * omap_iopgtable_store_entry - Make an iommu pte entry
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200677 * @obj: target iommu
678 * @e: an iommu tlb entry info
679 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300680int omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200681{
682 int err;
683
684 flush_iotlb_page(obj, e->da);
685 err = iopgtable_store_entry_core(obj, e);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200686 if (!err)
Ohad Ben-Cohen5da14a42011-08-16 15:19:10 +0300687 prefetch_iotlb_entry(obj, e);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200688 return err;
689}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300690EXPORT_SYMBOL_GPL(omap_iopgtable_store_entry);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200691
692/**
693 * iopgtable_lookup_entry - Lookup an iommu pte entry
694 * @obj: target iommu
695 * @da: iommu device virtual address
696 * @ppgd: iommu pgd entry pointer to be returned
697 * @ppte: iommu pte entry pointer to be returned
698 **/
Ohad Ben-Cohene1f23812011-08-16 14:58:14 +0300699static void
700iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200701{
702 u32 *iopgd, *iopte = NULL;
703
704 iopgd = iopgd_offset(obj, da);
705 if (!*iopgd)
706 goto out;
707
Hiroshi DOYUa1a54452010-05-13 09:45:35 +0300708 if (iopgd_is_table(*iopgd))
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200709 iopte = iopte_offset(iopgd, da);
710out:
711 *ppgd = iopgd;
712 *ppte = iopte;
713}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200714
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300715static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200716{
717 size_t bytes;
718 u32 *iopgd = iopgd_offset(obj, da);
719 int nent = 1;
720
721 if (!*iopgd)
722 return 0;
723
Hiroshi DOYUa1a54452010-05-13 09:45:35 +0300724 if (iopgd_is_table(*iopgd)) {
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200725 int i;
726 u32 *iopte = iopte_offset(iopgd, da);
727
728 bytes = IOPTE_SIZE;
729 if (*iopte & IOPTE_LARGE) {
730 nent *= 16;
731 /* rewind to the 1st entry */
Hiroshi DOYUc127c7d2010-02-15 10:03:32 -0800732 iopte = iopte_offset(iopgd, (da & IOLARGE_MASK));
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200733 }
734 bytes *= nent;
735 memset(iopte, 0, nent * sizeof(*iopte));
736 flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte));
737
738 /*
739 * do table walk to check if this table is necessary or not
740 */
741 iopte = iopte_offset(iopgd, 0);
742 for (i = 0; i < PTRS_PER_IOPTE; i++)
743 if (iopte[i])
744 goto out;
745
746 iopte_free(iopte);
747 nent = 1; /* for the next L1 entry */
748 } else {
749 bytes = IOPGD_SIZE;
Hiroshi DOYUdcc730d2009-10-22 14:46:32 -0700750 if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) {
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200751 nent *= 16;
752 /* rewind to the 1st entry */
Hiroshi DOYU8d33ea52010-02-15 10:03:32 -0800753 iopgd = iopgd_offset(obj, (da & IOSUPER_MASK));
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200754 }
755 bytes *= nent;
756 }
757 memset(iopgd, 0, nent * sizeof(*iopgd));
758 flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd));
759out:
760 return bytes;
761}
762
763/**
764 * iopgtable_clear_entry - Remove an iommu pte entry
765 * @obj: target iommu
766 * @da: iommu device virtual address
767 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300768static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200769{
770 size_t bytes;
771
772 spin_lock(&obj->page_table_lock);
773
774 bytes = iopgtable_clear_entry_core(obj, da);
775 flush_iotlb_page(obj, da);
776
777 spin_unlock(&obj->page_table_lock);
778
779 return bytes;
780}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200781
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300782static void iopgtable_clear_entry_all(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200783{
784 int i;
785
786 spin_lock(&obj->page_table_lock);
787
788 for (i = 0; i < PTRS_PER_IOPGD; i++) {
789 u32 da;
790 u32 *iopgd;
791
792 da = i << IOPGD_SHIFT;
793 iopgd = iopgd_offset(obj, da);
794
795 if (!*iopgd)
796 continue;
797
Hiroshi DOYUa1a54452010-05-13 09:45:35 +0300798 if (iopgd_is_table(*iopgd))
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200799 iopte_free(iopte_offset(iopgd, 0));
800
801 *iopgd = 0;
802 flush_iopgd_range(iopgd, iopgd);
803 }
804
805 flush_iotlb_all(obj);
806
807 spin_unlock(&obj->page_table_lock);
808}
809
810/*
811 * Device IOMMU generic operations
812 */
813static irqreturn_t iommu_fault_handler(int irq, void *data)
814{
David Cohend594f1f2011-02-16 19:35:51 +0000815 u32 da, errs;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200816 u32 *iopgd, *iopte;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300817 struct omap_iommu *obj = data;
Ohad Ben-Cohene7f10f02011-09-13 15:26:29 -0400818 struct iommu_domain *domain = obj->domain;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200819
820 if (!obj->refcount)
821 return IRQ_NONE;
822
David Cohend594f1f2011-02-16 19:35:51 +0000823 errs = iommu_report_fault(obj, &da);
Laurent Pinchartc56b2dd2011-05-10 16:56:46 +0200824 if (errs == 0)
825 return IRQ_HANDLED;
David Cohend594f1f2011-02-16 19:35:51 +0000826
827 /* Fault callback or TLB/PTE Dynamic loading */
Ohad Ben-Cohene7f10f02011-09-13 15:26:29 -0400828 if (!report_iommu_fault(domain, obj->dev, da, 0))
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200829 return IRQ_HANDLED;
830
Hiroshi DOYU37b29812010-05-24 02:01:52 +0000831 iommu_disable(obj);
832
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200833 iopgd = iopgd_offset(obj, da);
834
Hiroshi DOYUa1a54452010-05-13 09:45:35 +0300835 if (!iopgd_is_table(*iopgd)) {
Suman Annab6c2e092013-05-30 18:10:59 -0500836 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:px%08x\n",
837 obj->name, errs, da, iopgd, *iopgd);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200838 return IRQ_NONE;
839 }
840
841 iopte = iopte_offset(iopgd, da);
842
Suman Annab6c2e092013-05-30 18:10:59 -0500843 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x pte:0x%p *pte:0x%08x\n",
844 obj->name, errs, da, iopgd, *iopgd, iopte, *iopte);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200845
846 return IRQ_NONE;
847}
848
849static int device_match_by_alias(struct device *dev, void *data)
850{
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300851 struct omap_iommu *obj = to_iommu(dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200852 const char *name = data;
853
854 pr_debug("%s: %s %s\n", __func__, obj->name, name);
855
856 return strcmp(obj->name, name) == 0;
857}
858
859/**
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300860 * omap_iommu_attach() - attach iommu device to an iommu domain
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200861 * @name: name of target omap iommu device
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300862 * @iopgd: page table
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200863 **/
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200864static struct omap_iommu *omap_iommu_attach(const char *name, u32 *iopgd)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200865{
866 int err = -ENOMEM;
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200867 struct device *dev;
868 struct omap_iommu *obj;
869
870 dev = driver_find_device(&omap_iommu_driver.driver, NULL,
871 (void *)name,
872 device_match_by_alias);
873 if (!dev)
874 return NULL;
875
876 obj = to_iommu(dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200877
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300878 spin_lock(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200879
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300880 /* an iommu device can only be attached once */
881 if (++obj->refcount > 1) {
882 dev_err(dev, "%s: already attached!\n", obj->name);
883 err = -EBUSY;
884 goto err_enable;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200885 }
886
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300887 obj->iopgd = iopgd;
888 err = iommu_enable(obj);
889 if (err)
890 goto err_enable;
891 flush_iotlb_all(obj);
892
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200893 if (!try_module_get(obj->owner))
894 goto err_module;
895
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300896 spin_unlock(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200897
898 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
899 return obj;
900
901err_module:
902 if (obj->refcount == 1)
903 iommu_disable(obj);
904err_enable:
905 obj->refcount--;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300906 spin_unlock(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200907 return ERR_PTR(err);
908}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200909
910/**
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300911 * omap_iommu_detach - release iommu device
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200912 * @obj: target iommu
913 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300914static void omap_iommu_detach(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200915{
Roel Kluinacf9d462010-01-08 10:29:05 -0800916 if (!obj || IS_ERR(obj))
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200917 return;
918
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300919 spin_lock(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200920
921 if (--obj->refcount == 0)
922 iommu_disable(obj);
923
924 module_put(obj->owner);
925
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300926 obj->iopgd = NULL;
927
928 spin_unlock(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200929
930 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
931}
David Cohend594f1f2011-02-16 19:35:51 +0000932
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200933/*
934 * OMAP Device MMU(IOMMU) detection
935 */
Greg Kroah-Hartmand34d6512012-12-21 15:05:21 -0800936static int omap_iommu_probe(struct platform_device *pdev)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200937{
938 int err = -ENODEV;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200939 int irq;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300940 struct omap_iommu *obj;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200941 struct resource *res;
942 struct iommu_platform_data *pdata = pdev->dev.platform_data;
943
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200944 obj = kzalloc(sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL);
945 if (!obj)
946 return -ENOMEM;
947
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200948 obj->nr_tlb_entries = pdata->nr_tlb_entries;
949 obj->name = pdata->name;
950 obj->dev = &pdev->dev;
951 obj->ctx = (void *)obj + sizeof(*obj);
Guzman Lugo, Fernandoc7f4ab22010-12-15 00:54:03 +0000952 obj->da_start = pdata->da_start;
953 obj->da_end = pdata->da_end;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200954
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300955 spin_lock_init(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200956 mutex_init(&obj->mmap_lock);
957 spin_lock_init(&obj->page_table_lock);
958 INIT_LIST_HEAD(&obj->mmap);
959
960 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
961 if (!res) {
962 err = -ENODEV;
963 goto err_mem;
964 }
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200965
966 res = request_mem_region(res->start, resource_size(res),
967 dev_name(&pdev->dev));
968 if (!res) {
969 err = -EIO;
970 goto err_mem;
971 }
972
Aaro Koskinenda4a0f72011-03-14 12:28:32 +0000973 obj->regbase = ioremap(res->start, resource_size(res));
974 if (!obj->regbase) {
975 err = -ENOMEM;
976 goto err_ioremap;
977 }
978
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200979 irq = platform_get_irq(pdev, 0);
980 if (irq < 0) {
981 err = -ENODEV;
982 goto err_irq;
983 }
984 err = request_irq(irq, iommu_fault_handler, IRQF_SHARED,
985 dev_name(&pdev->dev), obj);
986 if (err < 0)
987 goto err_irq;
988 platform_set_drvdata(pdev, obj);
989
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600990 pm_runtime_irq_safe(obj->dev);
991 pm_runtime_enable(obj->dev);
992
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200993 dev_info(&pdev->dev, "%s registered\n", obj->name);
994 return 0;
995
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200996err_irq:
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200997 iounmap(obj->regbase);
Aaro Koskinenda4a0f72011-03-14 12:28:32 +0000998err_ioremap:
999 release_mem_region(res->start, resource_size(res));
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001000err_mem:
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001001 kfree(obj);
1002 return err;
1003}
1004
Greg Kroah-Hartmand34d6512012-12-21 15:05:21 -08001005static int omap_iommu_remove(struct platform_device *pdev)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001006{
1007 int irq;
1008 struct resource *res;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001009 struct omap_iommu *obj = platform_get_drvdata(pdev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001010
1011 platform_set_drvdata(pdev, NULL);
1012
1013 iopgtable_clear_entry_all(obj);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001014
1015 irq = platform_get_irq(pdev, 0);
1016 free_irq(irq, obj);
1017 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1018 release_mem_region(res->start, resource_size(res));
1019 iounmap(obj->regbase);
1020
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -06001021 pm_runtime_disable(obj->dev);
1022
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001023 dev_info(&pdev->dev, "%s removed\n", obj->name);
1024 kfree(obj);
1025 return 0;
1026}
1027
1028static struct platform_driver omap_iommu_driver = {
1029 .probe = omap_iommu_probe,
Greg Kroah-Hartmand34d6512012-12-21 15:05:21 -08001030 .remove = omap_iommu_remove,
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001031 .driver = {
1032 .name = "omap-iommu",
1033 },
1034};
1035
1036static void iopte_cachep_ctor(void *iopte)
1037{
1038 clean_dcache_area(iopte, IOPTE_TABLE_SIZE);
1039}
1040
Tony Lindgrened1c7de2012-11-02 12:24:06 -07001041static u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa,
1042 u32 flags)
1043{
1044 memset(e, 0, sizeof(*e));
1045
1046 e->da = da;
1047 e->pa = pa;
1048 e->valid = 1;
1049 /* FIXME: add OMAP1 support */
1050 e->pgsz = flags & MMU_CAM_PGSZ_MASK;
1051 e->endian = flags & MMU_RAM_ENDIAN_MASK;
1052 e->elsz = flags & MMU_RAM_ELSZ_MASK;
1053 e->mixed = flags & MMU_RAM_MIXED_MASK;
1054
1055 return iopgsz_to_bytes(e->pgsz);
1056}
1057
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001058static int omap_iommu_map(struct iommu_domain *domain, unsigned long da,
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02001059 phys_addr_t pa, size_t bytes, int prot)
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001060{
1061 struct omap_iommu_domain *omap_domain = domain->priv;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001062 struct omap_iommu *oiommu = omap_domain->iommu_dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001063 struct device *dev = oiommu->dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001064 struct iotlb_entry e;
1065 int omap_pgsz;
1066 u32 ret, flags;
1067
1068 /* we only support mapping a single iommu page for now */
1069 omap_pgsz = bytes_to_iopgsz(bytes);
1070 if (omap_pgsz < 0) {
1071 dev_err(dev, "invalid size to map: %d\n", bytes);
1072 return -EINVAL;
1073 }
1074
1075 dev_dbg(dev, "mapping da 0x%lx to pa 0x%x size 0x%x\n", da, pa, bytes);
1076
1077 flags = omap_pgsz | prot;
1078
1079 iotlb_init_entry(&e, da, pa, flags);
1080
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001081 ret = omap_iopgtable_store_entry(oiommu, &e);
Ohad Ben-Cohenb4550d42011-09-02 13:32:31 -04001082 if (ret)
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001083 dev_err(dev, "omap_iopgtable_store_entry failed: %d\n", ret);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001084
Ohad Ben-Cohenb4550d42011-09-02 13:32:31 -04001085 return ret;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001086}
1087
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02001088static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da,
1089 size_t size)
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001090{
1091 struct omap_iommu_domain *omap_domain = domain->priv;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001092 struct omap_iommu *oiommu = omap_domain->iommu_dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001093 struct device *dev = oiommu->dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001094
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02001095 dev_dbg(dev, "unmapping da 0x%lx size %u\n", da, size);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001096
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02001097 return iopgtable_clear_entry(oiommu, da);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001098}
1099
1100static int
1101omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
1102{
1103 struct omap_iommu_domain *omap_domain = domain->priv;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001104 struct omap_iommu *oiommu;
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +02001105 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001106 int ret = 0;
1107
1108 spin_lock(&omap_domain->lock);
1109
1110 /* only a single device is supported per domain for now */
1111 if (omap_domain->iommu_dev) {
1112 dev_err(dev, "iommu domain is already attached\n");
1113 ret = -EBUSY;
1114 goto out;
1115 }
1116
1117 /* get a handle to and enable the omap iommu */
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +02001118 oiommu = omap_iommu_attach(arch_data->name, omap_domain->pgtable);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001119 if (IS_ERR(oiommu)) {
1120 ret = PTR_ERR(oiommu);
1121 dev_err(dev, "can't get omap iommu: %d\n", ret);
1122 goto out;
1123 }
1124
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +02001125 omap_domain->iommu_dev = arch_data->iommu_dev = oiommu;
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001126 omap_domain->dev = dev;
Ohad Ben-Cohene7f10f02011-09-13 15:26:29 -04001127 oiommu->domain = domain;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001128
1129out:
1130 spin_unlock(&omap_domain->lock);
1131 return ret;
1132}
1133
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001134static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain,
1135 struct device *dev)
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001136{
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +02001137 struct omap_iommu *oiommu = dev_to_omap_iommu(dev);
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001138 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001139
1140 /* only a single device is supported per domain for now */
1141 if (omap_domain->iommu_dev != oiommu) {
1142 dev_err(dev, "invalid iommu device\n");
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001143 return;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001144 }
1145
1146 iopgtable_clear_entry_all(oiommu);
1147
1148 omap_iommu_detach(oiommu);
1149
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +02001150 omap_domain->iommu_dev = arch_data->iommu_dev = NULL;
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001151 omap_domain->dev = NULL;
1152}
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001153
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001154static void omap_iommu_detach_dev(struct iommu_domain *domain,
1155 struct device *dev)
1156{
1157 struct omap_iommu_domain *omap_domain = domain->priv;
1158
1159 spin_lock(&omap_domain->lock);
1160 _omap_iommu_detach_dev(omap_domain, dev);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001161 spin_unlock(&omap_domain->lock);
1162}
1163
1164static int omap_iommu_domain_init(struct iommu_domain *domain)
1165{
1166 struct omap_iommu_domain *omap_domain;
1167
1168 omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL);
1169 if (!omap_domain) {
1170 pr_err("kzalloc failed\n");
1171 goto out;
1172 }
1173
1174 omap_domain->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_KERNEL);
1175 if (!omap_domain->pgtable) {
1176 pr_err("kzalloc failed\n");
1177 goto fail_nomem;
1178 }
1179
1180 /*
1181 * should never fail, but please keep this around to ensure
1182 * we keep the hardware happy
1183 */
1184 BUG_ON(!IS_ALIGNED((long)omap_domain->pgtable, IOPGD_TABLE_SIZE));
1185
1186 clean_dcache_area(omap_domain->pgtable, IOPGD_TABLE_SIZE);
1187 spin_lock_init(&omap_domain->lock);
1188
1189 domain->priv = omap_domain;
1190
Joerg Roedel2c6edb02012-01-26 19:40:55 +01001191 domain->geometry.aperture_start = 0;
1192 domain->geometry.aperture_end = (1ULL << 32) - 1;
1193 domain->geometry.force_aperture = true;
1194
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001195 return 0;
1196
1197fail_nomem:
1198 kfree(omap_domain);
1199out:
1200 return -ENOMEM;
1201}
1202
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001203static void omap_iommu_domain_destroy(struct iommu_domain *domain)
1204{
1205 struct omap_iommu_domain *omap_domain = domain->priv;
1206
1207 domain->priv = NULL;
1208
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001209 /*
1210 * An iommu device is still attached
1211 * (currently, only one device can be attached) ?
1212 */
1213 if (omap_domain->iommu_dev)
1214 _omap_iommu_detach_dev(omap_domain, omap_domain->dev);
1215
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001216 kfree(omap_domain->pgtable);
1217 kfree(omap_domain);
1218}
1219
1220static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain,
Varun Sethibb5547ac2013-03-29 01:23:58 +05301221 dma_addr_t da)
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001222{
1223 struct omap_iommu_domain *omap_domain = domain->priv;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001224 struct omap_iommu *oiommu = omap_domain->iommu_dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001225 struct device *dev = oiommu->dev;
1226 u32 *pgd, *pte;
1227 phys_addr_t ret = 0;
1228
1229 iopgtable_lookup_entry(oiommu, da, &pgd, &pte);
1230
1231 if (pte) {
1232 if (iopte_is_small(*pte))
1233 ret = omap_iommu_translate(*pte, da, IOPTE_MASK);
1234 else if (iopte_is_large(*pte))
1235 ret = omap_iommu_translate(*pte, da, IOLARGE_MASK);
1236 else
Suman Anna2abfcfb2013-05-30 18:10:38 -05001237 dev_err(dev, "bogus pte 0x%x, da 0x%llx", *pte,
1238 (unsigned long long)da);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001239 } else {
1240 if (iopgd_is_section(*pgd))
1241 ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK);
1242 else if (iopgd_is_super(*pgd))
1243 ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK);
1244 else
Suman Anna2abfcfb2013-05-30 18:10:38 -05001245 dev_err(dev, "bogus pgd 0x%x, da 0x%llx", *pgd,
1246 (unsigned long long)da);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001247 }
1248
1249 return ret;
1250}
1251
1252static int omap_iommu_domain_has_cap(struct iommu_domain *domain,
1253 unsigned long cap)
1254{
1255 return 0;
1256}
1257
1258static struct iommu_ops omap_iommu_ops = {
1259 .domain_init = omap_iommu_domain_init,
1260 .domain_destroy = omap_iommu_domain_destroy,
1261 .attach_dev = omap_iommu_attach_dev,
1262 .detach_dev = omap_iommu_detach_dev,
1263 .map = omap_iommu_map,
1264 .unmap = omap_iommu_unmap,
1265 .iova_to_phys = omap_iommu_iova_to_phys,
1266 .domain_has_cap = omap_iommu_domain_has_cap,
Ohad Ben-Cohen66bc8cf2011-11-10 11:32:27 +02001267 .pgsize_bitmap = OMAP_IOMMU_PGSIZES,
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001268};
1269
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001270static int __init omap_iommu_init(void)
1271{
1272 struct kmem_cache *p;
1273 const unsigned long flags = SLAB_HWCACHE_ALIGN;
1274 size_t align = 1 << 10; /* L2 pagetable alignement */
1275
1276 p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags,
1277 iopte_cachep_ctor);
1278 if (!p)
1279 return -ENOMEM;
1280 iopte_cachep = p;
1281
Joerg Roedela65bc642011-09-06 17:56:07 +02001282 bus_set_iommu(&platform_bus_type, &omap_iommu_ops);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001283
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001284 return platform_driver_register(&omap_iommu_driver);
1285}
Ohad Ben-Cohen435792d2012-02-26 12:14:14 +02001286/* must be ready before omap3isp is probed */
1287subsys_initcall(omap_iommu_init);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001288
1289static void __exit omap_iommu_exit(void)
1290{
1291 kmem_cache_destroy(iopte_cachep);
1292
1293 platform_driver_unregister(&omap_iommu_driver);
1294}
1295module_exit(omap_iommu_exit);
1296
1297MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives");
1298MODULE_ALIAS("platform:omap-iommu");
1299MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
1300MODULE_LICENSE("GPL v2");