Amitkumar Karwar | d930fae | 2011-10-11 17:41:21 -0700 | [diff] [blame] | 1 | /* @file mwifiex_pcie.h |
| 2 | * |
| 3 | * @brief This file contains definitions for PCI-E interface. |
| 4 | * driver. |
| 5 | * |
Xinming Hu | 65da33f | 2014-06-19 21:38:57 -0700 | [diff] [blame] | 6 | * Copyright (C) 2011-2014, Marvell International Ltd. |
Amitkumar Karwar | d930fae | 2011-10-11 17:41:21 -0700 | [diff] [blame] | 7 | * |
| 8 | * This software file (the "File") is distributed by Marvell International |
| 9 | * Ltd. under the terms of the GNU General Public License Version 2, June 1991 |
| 10 | * (the "License"). You may use, redistribute and/or modify this File in |
| 11 | * accordance with the terms and conditions of the License, a copy of which |
| 12 | * is available by writing to the Free Software Foundation, Inc., |
| 13 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the |
| 14 | * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt. |
| 15 | * |
| 16 | * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE |
| 17 | * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE |
| 18 | * ARE EXPRESSLY DISCLAIMED. The License provides additional details about |
| 19 | * this warranty disclaimer. |
| 20 | */ |
| 21 | |
| 22 | #ifndef _MWIFIEX_PCIE_H |
| 23 | #define _MWIFIEX_PCIE_H |
| 24 | |
| 25 | #include <linux/pci.h> |
| 26 | #include <linux/pcieport_if.h> |
| 27 | #include <linux/interrupt.h> |
| 28 | |
Xinming Hu | 9a86232 | 2016-02-02 22:05:05 -0800 | [diff] [blame] | 29 | #include "decl.h" |
Amitkumar Karwar | d930fae | 2011-10-11 17:41:21 -0700 | [diff] [blame] | 30 | #include "main.h" |
| 31 | |
| 32 | #define PCIE8766_DEFAULT_FW_NAME "mrvl/pcie8766_uapsta.bin" |
Avinash Patil | ca8f211 | 2013-02-08 18:18:09 -0800 | [diff] [blame] | 33 | #define PCIE8897_DEFAULT_FW_NAME "mrvl/pcie8897_uapsta.bin" |
Zhaoyang Liu | 6d85ef0 | 2015-08-05 06:09:40 -0700 | [diff] [blame] | 34 | #define PCIE8997_DEFAULT_FW_NAME "mrvl/pcie8997_uapsta.bin" |
Avinash Patil | ca8f211 | 2013-02-08 18:18:09 -0800 | [diff] [blame] | 35 | |
| 36 | #define PCIE_VENDOR_ID_MARVELL (0x11ab) |
| 37 | #define PCIE_DEVICE_ID_MARVELL_88W8766P (0x2b30) |
| 38 | #define PCIE_DEVICE_ID_MARVELL_88W8897 (0x2b38) |
Zhaoyang Liu | 6d85ef0 | 2015-08-05 06:09:40 -0700 | [diff] [blame] | 39 | #define PCIE_DEVICE_ID_MARVELL_88W8997 (0x2b42) |
Amitkumar Karwar | d930fae | 2011-10-11 17:41:21 -0700 | [diff] [blame] | 40 | |
| 41 | /* Constants for Buffer Descriptor (BD) rings */ |
| 42 | #define MWIFIEX_MAX_TXRX_BD 0x20 |
| 43 | #define MWIFIEX_TXBD_MASK 0x3F |
| 44 | #define MWIFIEX_RXBD_MASK 0x3F |
| 45 | |
Avinash Patil | 2703a66 | 2014-09-12 20:08:49 +0530 | [diff] [blame] | 46 | #define MWIFIEX_MAX_EVT_BD 0x08 |
| 47 | #define MWIFIEX_EVTBD_MASK 0x0f |
Amitkumar Karwar | d930fae | 2011-10-11 17:41:21 -0700 | [diff] [blame] | 48 | |
| 49 | /* PCIE INTERNAL REGISTERS */ |
| 50 | #define PCIE_SCRATCH_0_REG 0xC10 |
| 51 | #define PCIE_SCRATCH_1_REG 0xC14 |
| 52 | #define PCIE_CPU_INT_EVENT 0xC18 |
| 53 | #define PCIE_CPU_INT_STATUS 0xC1C |
| 54 | #define PCIE_HOST_INT_STATUS 0xC30 |
| 55 | #define PCIE_HOST_INT_MASK 0xC34 |
| 56 | #define PCIE_HOST_INT_STATUS_MASK 0xC3C |
| 57 | #define PCIE_SCRATCH_2_REG 0xC40 |
| 58 | #define PCIE_SCRATCH_3_REG 0xC44 |
Bing Zhao | 428ca8a | 2012-04-12 19:00:35 -0700 | [diff] [blame] | 59 | #define PCIE_SCRATCH_4_REG 0xCD0 |
| 60 | #define PCIE_SCRATCH_5_REG 0xCD4 |
| 61 | #define PCIE_SCRATCH_6_REG 0xCD8 |
| 62 | #define PCIE_SCRATCH_7_REG 0xCDC |
| 63 | #define PCIE_SCRATCH_8_REG 0xCE0 |
| 64 | #define PCIE_SCRATCH_9_REG 0xCE4 |
| 65 | #define PCIE_SCRATCH_10_REG 0xCE8 |
| 66 | #define PCIE_SCRATCH_11_REG 0xCEC |
| 67 | #define PCIE_SCRATCH_12_REG 0xCF0 |
Avinash Patil | ca8f211 | 2013-02-08 18:18:09 -0800 | [diff] [blame] | 68 | #define PCIE_RD_DATA_PTR_Q0_Q1 0xC08C |
| 69 | #define PCIE_WR_DATA_PTR_Q0_Q1 0xC05C |
Amitkumar Karwar | d930fae | 2011-10-11 17:41:21 -0700 | [diff] [blame] | 70 | |
| 71 | #define CPU_INTR_DNLD_RDY BIT(0) |
| 72 | #define CPU_INTR_DOOR_BELL BIT(1) |
| 73 | #define CPU_INTR_SLEEP_CFM_DONE BIT(2) |
| 74 | #define CPU_INTR_RESET BIT(3) |
Avinash Patil | 2703a66 | 2014-09-12 20:08:49 +0530 | [diff] [blame] | 75 | #define CPU_INTR_EVENT_DONE BIT(5) |
Amitkumar Karwar | d930fae | 2011-10-11 17:41:21 -0700 | [diff] [blame] | 76 | |
| 77 | #define HOST_INTR_DNLD_DONE BIT(0) |
| 78 | #define HOST_INTR_UPLD_RDY BIT(1) |
| 79 | #define HOST_INTR_CMD_DONE BIT(2) |
| 80 | #define HOST_INTR_EVENT_RDY BIT(3) |
| 81 | #define HOST_INTR_MASK (HOST_INTR_DNLD_DONE | \ |
| 82 | HOST_INTR_UPLD_RDY | \ |
| 83 | HOST_INTR_CMD_DONE | \ |
| 84 | HOST_INTR_EVENT_RDY) |
| 85 | |
| 86 | #define MWIFIEX_BD_FLAG_ROLLOVER_IND BIT(7) |
| 87 | #define MWIFIEX_BD_FLAG_FIRST_DESC BIT(0) |
| 88 | #define MWIFIEX_BD_FLAG_LAST_DESC BIT(1) |
Avinash Patil | ca8f211 | 2013-02-08 18:18:09 -0800 | [diff] [blame] | 89 | #define MWIFIEX_BD_FLAG_SOP BIT(0) |
| 90 | #define MWIFIEX_BD_FLAG_EOP BIT(1) |
| 91 | #define MWIFIEX_BD_FLAG_XS_SOP BIT(2) |
| 92 | #define MWIFIEX_BD_FLAG_XS_EOP BIT(3) |
| 93 | #define MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND BIT(7) |
| 94 | #define MWIFIEX_BD_FLAG_RX_ROLLOVER_IND BIT(10) |
| 95 | #define MWIFIEX_BD_FLAG_TX_START_PTR BIT(16) |
| 96 | #define MWIFIEX_BD_FLAG_TX_ROLLOVER_IND BIT(26) |
Amitkumar Karwar | d930fae | 2011-10-11 17:41:21 -0700 | [diff] [blame] | 97 | |
| 98 | /* Max retry number of command write */ |
| 99 | #define MAX_WRITE_IOMEM_RETRY 2 |
| 100 | /* Define PCIE block size for firmware download */ |
| 101 | #define MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD 256 |
| 102 | /* FW awake cookie after FW ready */ |
| 103 | #define FW_AWAKE_COOKIE (0xAA55AA55) |
Avinash Patil | c4bc980 | 2014-03-18 22:19:17 -0700 | [diff] [blame] | 104 | #define MWIFIEX_DEF_SLEEP_COOKIE 0xBEEFBEEF |
| 105 | #define MWIFIEX_MAX_DELAY_COUNT 5 |
Amitkumar Karwar | d930fae | 2011-10-11 17:41:21 -0700 | [diff] [blame] | 106 | |
Avinash Patil | dd04e6a | 2013-02-08 18:18:06 -0800 | [diff] [blame] | 107 | struct mwifiex_pcie_card_reg { |
| 108 | u16 cmd_addr_lo; |
| 109 | u16 cmd_addr_hi; |
| 110 | u16 fw_status; |
| 111 | u16 cmd_size; |
| 112 | u16 cmdrsp_addr_lo; |
| 113 | u16 cmdrsp_addr_hi; |
| 114 | u16 tx_rdptr; |
| 115 | u16 tx_wrptr; |
| 116 | u16 rx_rdptr; |
| 117 | u16 rx_wrptr; |
| 118 | u16 evt_rdptr; |
| 119 | u16 evt_wrptr; |
| 120 | u16 drv_rdy; |
| 121 | u16 tx_start_ptr; |
| 122 | u32 tx_mask; |
| 123 | u32 tx_wrap_mask; |
| 124 | u32 rx_mask; |
| 125 | u32 rx_wrap_mask; |
| 126 | u32 tx_rollover_ind; |
| 127 | u32 rx_rollover_ind; |
| 128 | u32 evt_rollover_ind; |
| 129 | u8 ring_flag_sop; |
| 130 | u8 ring_flag_eop; |
| 131 | u8 ring_flag_xs_sop; |
| 132 | u8 ring_flag_xs_eop; |
| 133 | u32 ring_tx_start_ptr; |
| 134 | u8 pfu_enabled; |
Avinash Patil | 52301a8 | 2013-02-12 14:38:32 -0800 | [diff] [blame] | 135 | u8 sleep_cookie; |
Amitkumar Karwar | 92c2538 | 2014-06-19 21:38:52 -0700 | [diff] [blame] | 136 | u16 fw_dump_ctrl; |
| 137 | u16 fw_dump_start; |
| 138 | u16 fw_dump_end; |
Xinming Hu | 5063209 | 2016-02-02 22:05:06 -0800 | [diff] [blame^] | 139 | u8 fw_dump_host_ready; |
| 140 | u8 fw_dump_read_done; |
Xinming Hu | 99074fc | 2016-01-11 02:16:40 -0800 | [diff] [blame] | 141 | u8 msix_support; |
Avinash Patil | dd04e6a | 2013-02-08 18:18:06 -0800 | [diff] [blame] | 142 | }; |
| 143 | |
| 144 | static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = { |
| 145 | .cmd_addr_lo = PCIE_SCRATCH_0_REG, |
| 146 | .cmd_addr_hi = PCIE_SCRATCH_1_REG, |
| 147 | .cmd_size = PCIE_SCRATCH_2_REG, |
| 148 | .fw_status = PCIE_SCRATCH_3_REG, |
| 149 | .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG, |
| 150 | .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG, |
| 151 | .tx_rdptr = PCIE_SCRATCH_6_REG, |
| 152 | .tx_wrptr = PCIE_SCRATCH_7_REG, |
| 153 | .rx_rdptr = PCIE_SCRATCH_8_REG, |
| 154 | .rx_wrptr = PCIE_SCRATCH_9_REG, |
| 155 | .evt_rdptr = PCIE_SCRATCH_10_REG, |
| 156 | .evt_wrptr = PCIE_SCRATCH_11_REG, |
| 157 | .drv_rdy = PCIE_SCRATCH_12_REG, |
| 158 | .tx_start_ptr = 0, |
| 159 | .tx_mask = MWIFIEX_TXBD_MASK, |
| 160 | .tx_wrap_mask = 0, |
| 161 | .rx_mask = MWIFIEX_RXBD_MASK, |
| 162 | .rx_wrap_mask = 0, |
| 163 | .tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, |
| 164 | .rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, |
| 165 | .evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, |
| 166 | .ring_flag_sop = 0, |
| 167 | .ring_flag_eop = 0, |
| 168 | .ring_flag_xs_sop = 0, |
| 169 | .ring_flag_xs_eop = 0, |
| 170 | .ring_tx_start_ptr = 0, |
| 171 | .pfu_enabled = 0, |
Avinash Patil | 52301a8 | 2013-02-12 14:38:32 -0800 | [diff] [blame] | 172 | .sleep_cookie = 1, |
Xinming Hu | 99074fc | 2016-01-11 02:16:40 -0800 | [diff] [blame] | 173 | .msix_support = 0, |
Avinash Patil | dd04e6a | 2013-02-08 18:18:06 -0800 | [diff] [blame] | 174 | }; |
| 175 | |
Avinash Patil | ca8f211 | 2013-02-08 18:18:09 -0800 | [diff] [blame] | 176 | static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = { |
| 177 | .cmd_addr_lo = PCIE_SCRATCH_0_REG, |
| 178 | .cmd_addr_hi = PCIE_SCRATCH_1_REG, |
| 179 | .cmd_size = PCIE_SCRATCH_2_REG, |
| 180 | .fw_status = PCIE_SCRATCH_3_REG, |
| 181 | .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG, |
| 182 | .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG, |
| 183 | .tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1, |
| 184 | .tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1, |
| 185 | .rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1, |
| 186 | .rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1, |
| 187 | .evt_rdptr = PCIE_SCRATCH_10_REG, |
| 188 | .evt_wrptr = PCIE_SCRATCH_11_REG, |
| 189 | .drv_rdy = PCIE_SCRATCH_12_REG, |
| 190 | .tx_start_ptr = 16, |
| 191 | .tx_mask = 0x03FF0000, |
| 192 | .tx_wrap_mask = 0x07FF0000, |
| 193 | .rx_mask = 0x000003FF, |
| 194 | .rx_wrap_mask = 0x000007FF, |
| 195 | .tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND, |
| 196 | .rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND, |
| 197 | .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND, |
| 198 | .ring_flag_sop = MWIFIEX_BD_FLAG_SOP, |
| 199 | .ring_flag_eop = MWIFIEX_BD_FLAG_EOP, |
| 200 | .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP, |
| 201 | .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP, |
| 202 | .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR, |
| 203 | .pfu_enabled = 1, |
Avinash Patil | 52301a8 | 2013-02-12 14:38:32 -0800 | [diff] [blame] | 204 | .sleep_cookie = 0, |
Amitkumar Karwar | 92c2538 | 2014-06-19 21:38:52 -0700 | [diff] [blame] | 205 | .fw_dump_ctrl = 0xcf4, |
| 206 | .fw_dump_start = 0xcf8, |
Zhaoyang Liu | 6d85ef0 | 2015-08-05 06:09:40 -0700 | [diff] [blame] | 207 | .fw_dump_end = 0xcff, |
Xinming Hu | 5063209 | 2016-02-02 22:05:06 -0800 | [diff] [blame^] | 208 | .fw_dump_host_ready = 0xee, |
| 209 | .fw_dump_read_done = 0xfe, |
Xinming Hu | 99074fc | 2016-01-11 02:16:40 -0800 | [diff] [blame] | 210 | .msix_support = 0, |
Zhaoyang Liu | 6d85ef0 | 2015-08-05 06:09:40 -0700 | [diff] [blame] | 211 | }; |
| 212 | |
| 213 | static const struct mwifiex_pcie_card_reg mwifiex_reg_8997 = { |
| 214 | .cmd_addr_lo = PCIE_SCRATCH_0_REG, |
| 215 | .cmd_addr_hi = PCIE_SCRATCH_1_REG, |
| 216 | .cmd_size = PCIE_SCRATCH_2_REG, |
| 217 | .fw_status = PCIE_SCRATCH_3_REG, |
| 218 | .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG, |
| 219 | .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG, |
| 220 | .tx_rdptr = 0xC1A4, |
Amitkumar Karwar | ce0c58d | 2015-12-16 04:21:43 -0800 | [diff] [blame] | 221 | .tx_wrptr = 0xC174, |
| 222 | .rx_rdptr = 0xC174, |
Zhaoyang Liu | 6d85ef0 | 2015-08-05 06:09:40 -0700 | [diff] [blame] | 223 | .rx_wrptr = 0xC1A4, |
| 224 | .evt_rdptr = PCIE_SCRATCH_10_REG, |
| 225 | .evt_wrptr = PCIE_SCRATCH_11_REG, |
| 226 | .drv_rdy = PCIE_SCRATCH_12_REG, |
| 227 | .tx_start_ptr = 16, |
| 228 | .tx_mask = 0x0FFF0000, |
Amitkumar Karwar | ce0c58d | 2015-12-16 04:21:43 -0800 | [diff] [blame] | 229 | .tx_wrap_mask = 0x1FFF0000, |
Zhaoyang Liu | 6d85ef0 | 2015-08-05 06:09:40 -0700 | [diff] [blame] | 230 | .rx_mask = 0x00000FFF, |
Amitkumar Karwar | ce0c58d | 2015-12-16 04:21:43 -0800 | [diff] [blame] | 231 | .rx_wrap_mask = 0x00001FFF, |
Zhaoyang Liu | 6d85ef0 | 2015-08-05 06:09:40 -0700 | [diff] [blame] | 232 | .tx_rollover_ind = BIT(28), |
| 233 | .rx_rollover_ind = BIT(12), |
| 234 | .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND, |
| 235 | .ring_flag_sop = MWIFIEX_BD_FLAG_SOP, |
| 236 | .ring_flag_eop = MWIFIEX_BD_FLAG_EOP, |
| 237 | .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP, |
| 238 | .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP, |
| 239 | .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR, |
| 240 | .pfu_enabled = 1, |
| 241 | .sleep_cookie = 0, |
Xinming Hu | 99074fc | 2016-01-11 02:16:40 -0800 | [diff] [blame] | 242 | .msix_support = 1, |
Avinash Patil | ca8f211 | 2013-02-08 18:18:09 -0800 | [diff] [blame] | 243 | }; |
| 244 | |
Xinming Hu | 5063209 | 2016-02-02 22:05:06 -0800 | [diff] [blame^] | 245 | static struct memory_type_mapping mem_type_mapping_tbl_w8897[] = { |
| 246 | {"ITCM", NULL, 0, 0xF0}, |
| 247 | {"DTCM", NULL, 0, 0xF1}, |
| 248 | {"SQRAM", NULL, 0, 0xF2}, |
| 249 | {"IRAM", NULL, 0, 0xF3}, |
| 250 | {"APU", NULL, 0, 0xF4}, |
| 251 | {"CIU", NULL, 0, 0xF5}, |
| 252 | {"ICU", NULL, 0, 0xF6}, |
| 253 | {"MAC", NULL, 0, 0xF7}, |
| 254 | }; |
| 255 | |
Avinash Patil | dd04e6a | 2013-02-08 18:18:06 -0800 | [diff] [blame] | 256 | struct mwifiex_pcie_device { |
| 257 | const char *firmware; |
| 258 | const struct mwifiex_pcie_card_reg *reg; |
| 259 | u16 blksz_fw_dl; |
Amitkumar Karwar | 828cf22 | 2014-02-27 19:35:13 -0800 | [diff] [blame] | 260 | u16 tx_buf_size; |
Avinash Patil | b4e8aeb | 2015-02-11 23:12:26 +0530 | [diff] [blame] | 261 | bool can_dump_fw; |
Xinming Hu | 5063209 | 2016-02-02 22:05:06 -0800 | [diff] [blame^] | 262 | struct memory_type_mapping *mem_type_mapping_tbl; |
| 263 | u8 num_mem_types; |
Avinash Patil | 1fe192d | 2015-01-23 17:09:19 +0530 | [diff] [blame] | 264 | bool can_ext_scan; |
Avinash Patil | dd04e6a | 2013-02-08 18:18:06 -0800 | [diff] [blame] | 265 | }; |
| 266 | |
| 267 | static const struct mwifiex_pcie_device mwifiex_pcie8766 = { |
| 268 | .firmware = PCIE8766_DEFAULT_FW_NAME, |
| 269 | .reg = &mwifiex_reg_8766, |
| 270 | .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD, |
Amitkumar Karwar | 828cf22 | 2014-02-27 19:35:13 -0800 | [diff] [blame] | 271 | .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, |
Avinash Patil | b4e8aeb | 2015-02-11 23:12:26 +0530 | [diff] [blame] | 272 | .can_dump_fw = false, |
Avinash Patil | 1fe192d | 2015-01-23 17:09:19 +0530 | [diff] [blame] | 273 | .can_ext_scan = true, |
Avinash Patil | dd04e6a | 2013-02-08 18:18:06 -0800 | [diff] [blame] | 274 | }; |
| 275 | |
Avinash Patil | ca8f211 | 2013-02-08 18:18:09 -0800 | [diff] [blame] | 276 | static const struct mwifiex_pcie_device mwifiex_pcie8897 = { |
| 277 | .firmware = PCIE8897_DEFAULT_FW_NAME, |
| 278 | .reg = &mwifiex_reg_8897, |
| 279 | .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD, |
Amitkumar Karwar | 828cf22 | 2014-02-27 19:35:13 -0800 | [diff] [blame] | 280 | .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K, |
Avinash Patil | b4e8aeb | 2015-02-11 23:12:26 +0530 | [diff] [blame] | 281 | .can_dump_fw = true, |
Xinming Hu | 5063209 | 2016-02-02 22:05:06 -0800 | [diff] [blame^] | 282 | .mem_type_mapping_tbl = mem_type_mapping_tbl_w8897, |
| 283 | .num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8897), |
Avinash Patil | 1fe192d | 2015-01-23 17:09:19 +0530 | [diff] [blame] | 284 | .can_ext_scan = true, |
Avinash Patil | ca8f211 | 2013-02-08 18:18:09 -0800 | [diff] [blame] | 285 | }; |
| 286 | |
Zhaoyang Liu | 6d85ef0 | 2015-08-05 06:09:40 -0700 | [diff] [blame] | 287 | static const struct mwifiex_pcie_device mwifiex_pcie8997 = { |
| 288 | .firmware = PCIE8997_DEFAULT_FW_NAME, |
| 289 | .reg = &mwifiex_reg_8997, |
| 290 | .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD, |
| 291 | .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K, |
| 292 | .can_dump_fw = false, |
| 293 | .can_ext_scan = true, |
| 294 | }; |
| 295 | |
Avinash Patil | e05dc3e | 2013-02-08 18:18:08 -0800 | [diff] [blame] | 296 | struct mwifiex_evt_buf_desc { |
| 297 | u64 paddr; |
| 298 | u16 len; |
| 299 | u16 flags; |
| 300 | } __packed; |
| 301 | |
Amitkumar Karwar | d930fae | 2011-10-11 17:41:21 -0700 | [diff] [blame] | 302 | struct mwifiex_pcie_buf_desc { |
| 303 | u64 paddr; |
| 304 | u16 len; |
| 305 | u16 flags; |
| 306 | } __packed; |
| 307 | |
Avinash Patil | ca8f211 | 2013-02-08 18:18:09 -0800 | [diff] [blame] | 308 | struct mwifiex_pfu_buf_desc { |
| 309 | u16 flags; |
| 310 | u16 offset; |
| 311 | u16 frag_len; |
| 312 | u16 len; |
| 313 | u64 paddr; |
| 314 | u32 reserved; |
| 315 | } __packed; |
| 316 | |
Xinming Hu | 99074fc | 2016-01-11 02:16:40 -0800 | [diff] [blame] | 317 | #define MWIFIEX_NUM_MSIX_VECTORS 4 |
| 318 | |
| 319 | struct mwifiex_msix_context { |
| 320 | struct pci_dev *dev; |
| 321 | u16 msg_id; |
| 322 | }; |
| 323 | |
Amitkumar Karwar | d930fae | 2011-10-11 17:41:21 -0700 | [diff] [blame] | 324 | struct pcie_service_card { |
| 325 | struct pci_dev *dev; |
| 326 | struct mwifiex_adapter *adapter; |
Avinash Patil | dd04e6a | 2013-02-08 18:18:06 -0800 | [diff] [blame] | 327 | struct mwifiex_pcie_device pcie; |
Amitkumar Karwar | d930fae | 2011-10-11 17:41:21 -0700 | [diff] [blame] | 328 | |
Avinash Patil | fbd7e7a | 2013-01-03 21:21:31 -0800 | [diff] [blame] | 329 | u8 txbd_flush; |
Amitkumar Karwar | d930fae | 2011-10-11 17:41:21 -0700 | [diff] [blame] | 330 | u32 txbd_wrptr; |
| 331 | u32 txbd_rdptr; |
| 332 | u32 txbd_ring_size; |
| 333 | u8 *txbd_ring_vbase; |
Avinash Patil | fc33146 | 2013-01-03 21:21:30 -0800 | [diff] [blame] | 334 | dma_addr_t txbd_ring_pbase; |
Avinash Patil | e05dc3e | 2013-02-08 18:18:08 -0800 | [diff] [blame] | 335 | void *txbd_ring[MWIFIEX_MAX_TXRX_BD]; |
Amitkumar Karwar | d930fae | 2011-10-11 17:41:21 -0700 | [diff] [blame] | 336 | struct sk_buff *tx_buf_list[MWIFIEX_MAX_TXRX_BD]; |
| 337 | |
| 338 | u32 rxbd_wrptr; |
| 339 | u32 rxbd_rdptr; |
| 340 | u32 rxbd_ring_size; |
| 341 | u8 *rxbd_ring_vbase; |
Avinash Patil | fc33146 | 2013-01-03 21:21:30 -0800 | [diff] [blame] | 342 | dma_addr_t rxbd_ring_pbase; |
Avinash Patil | e05dc3e | 2013-02-08 18:18:08 -0800 | [diff] [blame] | 343 | void *rxbd_ring[MWIFIEX_MAX_TXRX_BD]; |
Amitkumar Karwar | d930fae | 2011-10-11 17:41:21 -0700 | [diff] [blame] | 344 | struct sk_buff *rx_buf_list[MWIFIEX_MAX_TXRX_BD]; |
| 345 | |
| 346 | u32 evtbd_wrptr; |
| 347 | u32 evtbd_rdptr; |
| 348 | u32 evtbd_ring_size; |
| 349 | u8 *evtbd_ring_vbase; |
Avinash Patil | fc33146 | 2013-01-03 21:21:30 -0800 | [diff] [blame] | 350 | dma_addr_t evtbd_ring_pbase; |
Avinash Patil | e05dc3e | 2013-02-08 18:18:08 -0800 | [diff] [blame] | 351 | void *evtbd_ring[MWIFIEX_MAX_EVT_BD]; |
Amitkumar Karwar | d930fae | 2011-10-11 17:41:21 -0700 | [diff] [blame] | 352 | struct sk_buff *evt_buf_list[MWIFIEX_MAX_EVT_BD]; |
| 353 | |
| 354 | struct sk_buff *cmd_buf; |
| 355 | struct sk_buff *cmdrsp_buf; |
Avinash Patil | fc33146 | 2013-01-03 21:21:30 -0800 | [diff] [blame] | 356 | u8 *sleep_cookie_vbase; |
| 357 | dma_addr_t sleep_cookie_pbase; |
Amitkumar Karwar | d930fae | 2011-10-11 17:41:21 -0700 | [diff] [blame] | 358 | void __iomem *pci_mmap; |
| 359 | void __iomem *pci_mmap1; |
Avinash Patil | 7be0f5b | 2015-12-16 04:21:45 -0800 | [diff] [blame] | 360 | int msi_enable; |
Xinming Hu | 99074fc | 2016-01-11 02:16:40 -0800 | [diff] [blame] | 361 | int msix_enable; |
| 362 | #ifdef CONFIG_PCI |
| 363 | struct msix_entry msix_entries[MWIFIEX_NUM_MSIX_VECTORS]; |
| 364 | #endif |
| 365 | struct mwifiex_msix_context msix_ctx[MWIFIEX_NUM_MSIX_VECTORS]; |
| 366 | struct mwifiex_msix_context share_irq_ctx; |
Amitkumar Karwar | d930fae | 2011-10-11 17:41:21 -0700 | [diff] [blame] | 367 | }; |
| 368 | |
Avinash Patil | fbd7e7a | 2013-01-03 21:21:31 -0800 | [diff] [blame] | 369 | static inline int |
| 370 | mwifiex_pcie_txbd_empty(struct pcie_service_card *card, u32 rdptr) |
| 371 | { |
Avinash Patil | dd04e6a | 2013-02-08 18:18:06 -0800 | [diff] [blame] | 372 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
| 373 | |
Avinash Patil | ca8f211 | 2013-02-08 18:18:09 -0800 | [diff] [blame] | 374 | switch (card->dev->device) { |
| 375 | case PCIE_DEVICE_ID_MARVELL_88W8766P: |
| 376 | if (((card->txbd_wrptr & reg->tx_mask) == |
| 377 | (rdptr & reg->tx_mask)) && |
| 378 | ((card->txbd_wrptr & reg->tx_rollover_ind) != |
| 379 | (rdptr & reg->tx_rollover_ind))) |
| 380 | return 1; |
| 381 | break; |
| 382 | case PCIE_DEVICE_ID_MARVELL_88W8897: |
Amitkumar Karwar | f3b35f2 | 2015-12-16 04:21:44 -0800 | [diff] [blame] | 383 | case PCIE_DEVICE_ID_MARVELL_88W8997: |
Avinash Patil | ca8f211 | 2013-02-08 18:18:09 -0800 | [diff] [blame] | 384 | if (((card->txbd_wrptr & reg->tx_mask) == |
| 385 | (rdptr & reg->tx_mask)) && |
| 386 | ((card->txbd_wrptr & reg->tx_rollover_ind) == |
Avinash Patil | dd04e6a | 2013-02-08 18:18:06 -0800 | [diff] [blame] | 387 | (rdptr & reg->tx_rollover_ind))) |
Avinash Patil | ca8f211 | 2013-02-08 18:18:09 -0800 | [diff] [blame] | 388 | return 1; |
| 389 | break; |
| 390 | } |
Avinash Patil | fbd7e7a | 2013-01-03 21:21:31 -0800 | [diff] [blame] | 391 | |
| 392 | return 0; |
| 393 | } |
| 394 | |
Avinash Patil | e7f767a | 2013-01-03 21:21:32 -0800 | [diff] [blame] | 395 | static inline int |
| 396 | mwifiex_pcie_txbd_not_full(struct pcie_service_card *card) |
| 397 | { |
Avinash Patil | dd04e6a | 2013-02-08 18:18:06 -0800 | [diff] [blame] | 398 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
| 399 | |
Avinash Patil | ca8f211 | 2013-02-08 18:18:09 -0800 | [diff] [blame] | 400 | switch (card->dev->device) { |
| 401 | case PCIE_DEVICE_ID_MARVELL_88W8766P: |
| 402 | if (((card->txbd_wrptr & reg->tx_mask) != |
| 403 | (card->txbd_rdptr & reg->tx_mask)) || |
| 404 | ((card->txbd_wrptr & reg->tx_rollover_ind) != |
| 405 | (card->txbd_rdptr & reg->tx_rollover_ind))) |
| 406 | return 1; |
| 407 | break; |
| 408 | case PCIE_DEVICE_ID_MARVELL_88W8897: |
Zhaoyang Liu | 6d85ef0 | 2015-08-05 06:09:40 -0700 | [diff] [blame] | 409 | case PCIE_DEVICE_ID_MARVELL_88W8997: |
Avinash Patil | ca8f211 | 2013-02-08 18:18:09 -0800 | [diff] [blame] | 410 | if (((card->txbd_wrptr & reg->tx_mask) != |
| 411 | (card->txbd_rdptr & reg->tx_mask)) || |
| 412 | ((card->txbd_wrptr & reg->tx_rollover_ind) == |
| 413 | (card->txbd_rdptr & reg->tx_rollover_ind))) |
| 414 | return 1; |
| 415 | break; |
| 416 | } |
Avinash Patil | e7f767a | 2013-01-03 21:21:32 -0800 | [diff] [blame] | 417 | |
| 418 | return 0; |
| 419 | } |
Amitkumar Karwar | 92c2538 | 2014-06-19 21:38:52 -0700 | [diff] [blame] | 420 | |
Amitkumar Karwar | d930fae | 2011-10-11 17:41:21 -0700 | [diff] [blame] | 421 | #endif /* _MWIFIEX_PCIE_H */ |