blob: 28366a90e1adfbec14b5679244676b1077c9926e [file] [log] [blame]
Mark Brownd2bedfe2009-07-27 14:45:52 +01001/*
2 * wm831x-core.c -- Device access for Wolfson WM831x PMICs
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
Mark Brown7e9f9fd2009-07-27 14:45:54 +010017#include <linux/bcd.h>
18#include <linux/delay.h>
Mark Brownd2bedfe2009-07-27 14:45:52 +010019#include <linux/mfd/core.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090020#include <linux/slab.h>
Mark Brown1df59812011-06-10 19:28:10 +010021#include <linux/err.h>
Mark Brownd2bedfe2009-07-27 14:45:52 +010022
23#include <linux/mfd/wm831x/core.h>
24#include <linux/mfd/wm831x/pdata.h>
Mark Brown7d4d0a32009-07-27 14:45:53 +010025#include <linux/mfd/wm831x/irq.h>
Mark Brown7e9f9fd2009-07-27 14:45:54 +010026#include <linux/mfd/wm831x/auxadc.h>
Mark Brown6704e512009-07-27 14:45:56 +010027#include <linux/mfd/wm831x/otp.h>
Mark Brown523d9cf2011-09-15 18:54:53 +020028#include <linux/mfd/wm831x/pmu.h>
Mark Brown698659d2009-07-27 14:45:57 +010029#include <linux/mfd/wm831x/regulator.h>
30
31/* Current settings - values are 2*2^(reg_val/4) microamps. These are
32 * exported since they are used by multiple drivers.
33 */
Mark Brown77169772009-11-30 13:24:18 +000034int wm831x_isinkv_values[WM831X_ISINK_MAX_ISEL + 1] = {
Mark Brown698659d2009-07-27 14:45:57 +010035 2,
36 2,
37 3,
38 3,
39 4,
40 5,
41 6,
42 7,
43 8,
44 10,
45 11,
46 13,
47 16,
48 19,
49 23,
50 27,
51 32,
52 38,
53 45,
54 54,
55 64,
56 76,
57 91,
58 108,
59 128,
60 152,
61 181,
62 215,
63 256,
64 304,
65 362,
66 431,
67 512,
68 609,
69 724,
70 861,
71 1024,
72 1218,
73 1448,
74 1722,
75 2048,
76 2435,
77 2896,
78 3444,
79 4096,
80 4871,
81 5793,
82 6889,
83 8192,
84 9742,
85 11585,
86 13777,
87 16384,
88 19484,
89 23170,
90 27554,
91};
92EXPORT_SYMBOL_GPL(wm831x_isinkv_values);
Mark Brownd2bedfe2009-07-27 14:45:52 +010093
Mark Brownd2bedfe2009-07-27 14:45:52 +010094static int wm831x_reg_locked(struct wm831x *wm831x, unsigned short reg)
95{
96 if (!wm831x->locked)
97 return 0;
98
99 switch (reg) {
100 case WM831X_WATCHDOG:
101 case WM831X_DC4_CONTROL:
102 case WM831X_ON_PIN_CONTROL:
103 case WM831X_BACKUP_CHARGER_CONTROL:
104 case WM831X_CHARGER_CONTROL_1:
105 case WM831X_CHARGER_CONTROL_2:
106 return 1;
107
108 default:
109 return 0;
110 }
111}
112
113/**
114 * wm831x_reg_unlock: Unlock user keyed registers
115 *
116 * The WM831x has a user key preventing writes to particularly
117 * critical registers. This function locks those registers,
118 * allowing writes to them.
119 */
120void wm831x_reg_lock(struct wm831x *wm831x)
121{
122 int ret;
123
124 ret = wm831x_reg_write(wm831x, WM831X_SECURITY_KEY, 0);
125 if (ret == 0) {
126 dev_vdbg(wm831x->dev, "Registers locked\n");
127
128 mutex_lock(&wm831x->io_lock);
129 WARN_ON(wm831x->locked);
130 wm831x->locked = 1;
131 mutex_unlock(&wm831x->io_lock);
132 } else {
133 dev_err(wm831x->dev, "Failed to lock registers: %d\n", ret);
134 }
135
136}
137EXPORT_SYMBOL_GPL(wm831x_reg_lock);
138
139/**
140 * wm831x_reg_unlock: Unlock user keyed registers
141 *
142 * The WM831x has a user key preventing writes to particularly
143 * critical registers. This function locks those registers,
144 * preventing spurious writes.
145 */
146int wm831x_reg_unlock(struct wm831x *wm831x)
147{
148 int ret;
149
150 /* 0x9716 is the value required to unlock the registers */
151 ret = wm831x_reg_write(wm831x, WM831X_SECURITY_KEY, 0x9716);
152 if (ret == 0) {
153 dev_vdbg(wm831x->dev, "Registers unlocked\n");
154
155 mutex_lock(&wm831x->io_lock);
156 WARN_ON(!wm831x->locked);
157 wm831x->locked = 0;
158 mutex_unlock(&wm831x->io_lock);
159 }
160
161 return ret;
162}
163EXPORT_SYMBOL_GPL(wm831x_reg_unlock);
164
Mark Brown2e47fff2011-07-21 17:30:08 +0100165static bool wm831x_reg_readable(struct device *dev, unsigned int reg)
166{
167 switch (reg) {
168 case WM831X_RESET_ID:
169 case WM831X_REVISION:
170 case WM831X_PARENT_ID:
171 case WM831X_SYSVDD_CONTROL:
172 case WM831X_THERMAL_MONITORING:
173 case WM831X_POWER_STATE:
174 case WM831X_WATCHDOG:
175 case WM831X_ON_PIN_CONTROL:
176 case WM831X_RESET_CONTROL:
177 case WM831X_CONTROL_INTERFACE:
178 case WM831X_SECURITY_KEY:
179 case WM831X_SOFTWARE_SCRATCH:
180 case WM831X_OTP_CONTROL:
181 case WM831X_GPIO_LEVEL:
182 case WM831X_SYSTEM_STATUS:
183 case WM831X_ON_SOURCE:
184 case WM831X_OFF_SOURCE:
185 case WM831X_SYSTEM_INTERRUPTS:
186 case WM831X_INTERRUPT_STATUS_1:
187 case WM831X_INTERRUPT_STATUS_2:
188 case WM831X_INTERRUPT_STATUS_3:
189 case WM831X_INTERRUPT_STATUS_4:
190 case WM831X_INTERRUPT_STATUS_5:
191 case WM831X_IRQ_CONFIG:
192 case WM831X_SYSTEM_INTERRUPTS_MASK:
193 case WM831X_INTERRUPT_STATUS_1_MASK:
194 case WM831X_INTERRUPT_STATUS_2_MASK:
195 case WM831X_INTERRUPT_STATUS_3_MASK:
196 case WM831X_INTERRUPT_STATUS_4_MASK:
197 case WM831X_INTERRUPT_STATUS_5_MASK:
198 case WM831X_RTC_WRITE_COUNTER:
199 case WM831X_RTC_TIME_1:
200 case WM831X_RTC_TIME_2:
201 case WM831X_RTC_ALARM_1:
202 case WM831X_RTC_ALARM_2:
203 case WM831X_RTC_CONTROL:
204 case WM831X_RTC_TRIM:
205 case WM831X_TOUCH_CONTROL_1:
206 case WM831X_TOUCH_CONTROL_2:
207 case WM831X_TOUCH_DATA_X:
208 case WM831X_TOUCH_DATA_Y:
209 case WM831X_TOUCH_DATA_Z:
210 case WM831X_AUXADC_DATA:
211 case WM831X_AUXADC_CONTROL:
212 case WM831X_AUXADC_SOURCE:
213 case WM831X_COMPARATOR_CONTROL:
214 case WM831X_COMPARATOR_1:
215 case WM831X_COMPARATOR_2:
216 case WM831X_COMPARATOR_3:
217 case WM831X_COMPARATOR_4:
218 case WM831X_GPIO1_CONTROL:
219 case WM831X_GPIO2_CONTROL:
220 case WM831X_GPIO3_CONTROL:
221 case WM831X_GPIO4_CONTROL:
222 case WM831X_GPIO5_CONTROL:
223 case WM831X_GPIO6_CONTROL:
224 case WM831X_GPIO7_CONTROL:
225 case WM831X_GPIO8_CONTROL:
226 case WM831X_GPIO9_CONTROL:
227 case WM831X_GPIO10_CONTROL:
228 case WM831X_GPIO11_CONTROL:
229 case WM831X_GPIO12_CONTROL:
230 case WM831X_GPIO13_CONTROL:
231 case WM831X_GPIO14_CONTROL:
232 case WM831X_GPIO15_CONTROL:
233 case WM831X_GPIO16_CONTROL:
234 case WM831X_CHARGER_CONTROL_1:
235 case WM831X_CHARGER_CONTROL_2:
236 case WM831X_CHARGER_STATUS:
237 case WM831X_BACKUP_CHARGER_CONTROL:
238 case WM831X_STATUS_LED_1:
239 case WM831X_STATUS_LED_2:
240 case WM831X_CURRENT_SINK_1:
241 case WM831X_CURRENT_SINK_2:
242 case WM831X_DCDC_ENABLE:
243 case WM831X_LDO_ENABLE:
244 case WM831X_DCDC_STATUS:
245 case WM831X_LDO_STATUS:
246 case WM831X_DCDC_UV_STATUS:
247 case WM831X_LDO_UV_STATUS:
248 case WM831X_DC1_CONTROL_1:
249 case WM831X_DC1_CONTROL_2:
250 case WM831X_DC1_ON_CONFIG:
251 case WM831X_DC1_SLEEP_CONTROL:
252 case WM831X_DC1_DVS_CONTROL:
253 case WM831X_DC2_CONTROL_1:
254 case WM831X_DC2_CONTROL_2:
255 case WM831X_DC2_ON_CONFIG:
256 case WM831X_DC2_SLEEP_CONTROL:
257 case WM831X_DC2_DVS_CONTROL:
258 case WM831X_DC3_CONTROL_1:
259 case WM831X_DC3_CONTROL_2:
260 case WM831X_DC3_ON_CONFIG:
261 case WM831X_DC3_SLEEP_CONTROL:
262 case WM831X_DC4_CONTROL:
263 case WM831X_DC4_SLEEP_CONTROL:
264 case WM831X_EPE1_CONTROL:
265 case WM831X_EPE2_CONTROL:
266 case WM831X_LDO1_CONTROL:
267 case WM831X_LDO1_ON_CONTROL:
268 case WM831X_LDO1_SLEEP_CONTROL:
269 case WM831X_LDO2_CONTROL:
270 case WM831X_LDO2_ON_CONTROL:
271 case WM831X_LDO2_SLEEP_CONTROL:
272 case WM831X_LDO3_CONTROL:
273 case WM831X_LDO3_ON_CONTROL:
274 case WM831X_LDO3_SLEEP_CONTROL:
275 case WM831X_LDO4_CONTROL:
276 case WM831X_LDO4_ON_CONTROL:
277 case WM831X_LDO4_SLEEP_CONTROL:
278 case WM831X_LDO5_CONTROL:
279 case WM831X_LDO5_ON_CONTROL:
280 case WM831X_LDO5_SLEEP_CONTROL:
281 case WM831X_LDO6_CONTROL:
282 case WM831X_LDO6_ON_CONTROL:
283 case WM831X_LDO6_SLEEP_CONTROL:
284 case WM831X_LDO7_CONTROL:
285 case WM831X_LDO7_ON_CONTROL:
286 case WM831X_LDO7_SLEEP_CONTROL:
287 case WM831X_LDO8_CONTROL:
288 case WM831X_LDO8_ON_CONTROL:
289 case WM831X_LDO8_SLEEP_CONTROL:
290 case WM831X_LDO9_CONTROL:
291 case WM831X_LDO9_ON_CONTROL:
292 case WM831X_LDO9_SLEEP_CONTROL:
293 case WM831X_LDO10_CONTROL:
294 case WM831X_LDO10_ON_CONTROL:
295 case WM831X_LDO10_SLEEP_CONTROL:
296 case WM831X_LDO11_ON_CONTROL:
297 case WM831X_LDO11_SLEEP_CONTROL:
298 case WM831X_POWER_GOOD_SOURCE_1:
299 case WM831X_POWER_GOOD_SOURCE_2:
300 case WM831X_CLOCK_CONTROL_1:
301 case WM831X_CLOCK_CONTROL_2:
302 case WM831X_FLL_CONTROL_1:
303 case WM831X_FLL_CONTROL_2:
304 case WM831X_FLL_CONTROL_3:
305 case WM831X_FLL_CONTROL_4:
306 case WM831X_FLL_CONTROL_5:
307 case WM831X_UNIQUE_ID_1:
308 case WM831X_UNIQUE_ID_2:
309 case WM831X_UNIQUE_ID_3:
310 case WM831X_UNIQUE_ID_4:
311 case WM831X_UNIQUE_ID_5:
312 case WM831X_UNIQUE_ID_6:
313 case WM831X_UNIQUE_ID_7:
314 case WM831X_UNIQUE_ID_8:
315 case WM831X_FACTORY_OTP_ID:
316 case WM831X_FACTORY_OTP_1:
317 case WM831X_FACTORY_OTP_2:
318 case WM831X_FACTORY_OTP_3:
319 case WM831X_FACTORY_OTP_4:
320 case WM831X_FACTORY_OTP_5:
321 case WM831X_CUSTOMER_OTP_ID:
322 case WM831X_DC1_OTP_CONTROL:
323 case WM831X_DC2_OTP_CONTROL:
324 case WM831X_DC3_OTP_CONTROL:
325 case WM831X_LDO1_2_OTP_CONTROL:
326 case WM831X_LDO3_4_OTP_CONTROL:
327 case WM831X_LDO5_6_OTP_CONTROL:
328 case WM831X_LDO7_8_OTP_CONTROL:
329 case WM831X_LDO9_10_OTP_CONTROL:
330 case WM831X_LDO11_EPE_CONTROL:
331 case WM831X_GPIO1_OTP_CONTROL:
332 case WM831X_GPIO2_OTP_CONTROL:
333 case WM831X_GPIO3_OTP_CONTROL:
334 case WM831X_GPIO4_OTP_CONTROL:
335 case WM831X_GPIO5_OTP_CONTROL:
336 case WM831X_GPIO6_OTP_CONTROL:
337 case WM831X_DBE_CHECK_DATA:
338 return true;
339 default:
340 return false;
341 }
342}
343
344static bool wm831x_reg_writeable(struct device *dev, unsigned int reg)
345{
346 struct wm831x *wm831x = dev_get_drvdata(dev);
347
348 if (wm831x_reg_locked(wm831x, reg))
349 return false;
350
351 switch (reg) {
352 case WM831X_SYSVDD_CONTROL:
353 case WM831X_THERMAL_MONITORING:
354 case WM831X_POWER_STATE:
355 case WM831X_WATCHDOG:
356 case WM831X_ON_PIN_CONTROL:
357 case WM831X_RESET_CONTROL:
358 case WM831X_CONTROL_INTERFACE:
359 case WM831X_SECURITY_KEY:
360 case WM831X_SOFTWARE_SCRATCH:
361 case WM831X_OTP_CONTROL:
362 case WM831X_GPIO_LEVEL:
363 case WM831X_INTERRUPT_STATUS_1:
364 case WM831X_INTERRUPT_STATUS_2:
365 case WM831X_INTERRUPT_STATUS_3:
366 case WM831X_INTERRUPT_STATUS_4:
367 case WM831X_INTERRUPT_STATUS_5:
368 case WM831X_IRQ_CONFIG:
369 case WM831X_SYSTEM_INTERRUPTS_MASK:
370 case WM831X_INTERRUPT_STATUS_1_MASK:
371 case WM831X_INTERRUPT_STATUS_2_MASK:
372 case WM831X_INTERRUPT_STATUS_3_MASK:
373 case WM831X_INTERRUPT_STATUS_4_MASK:
374 case WM831X_INTERRUPT_STATUS_5_MASK:
375 case WM831X_RTC_TIME_1:
376 case WM831X_RTC_TIME_2:
377 case WM831X_RTC_ALARM_1:
378 case WM831X_RTC_ALARM_2:
379 case WM831X_RTC_CONTROL:
380 case WM831X_RTC_TRIM:
381 case WM831X_TOUCH_CONTROL_1:
382 case WM831X_TOUCH_CONTROL_2:
383 case WM831X_AUXADC_CONTROL:
384 case WM831X_AUXADC_SOURCE:
385 case WM831X_COMPARATOR_CONTROL:
386 case WM831X_COMPARATOR_1:
387 case WM831X_COMPARATOR_2:
388 case WM831X_COMPARATOR_3:
389 case WM831X_COMPARATOR_4:
390 case WM831X_GPIO1_CONTROL:
391 case WM831X_GPIO2_CONTROL:
392 case WM831X_GPIO3_CONTROL:
393 case WM831X_GPIO4_CONTROL:
394 case WM831X_GPIO5_CONTROL:
395 case WM831X_GPIO6_CONTROL:
396 case WM831X_GPIO7_CONTROL:
397 case WM831X_GPIO8_CONTROL:
398 case WM831X_GPIO9_CONTROL:
399 case WM831X_GPIO10_CONTROL:
400 case WM831X_GPIO11_CONTROL:
401 case WM831X_GPIO12_CONTROL:
402 case WM831X_GPIO13_CONTROL:
403 case WM831X_GPIO14_CONTROL:
404 case WM831X_GPIO15_CONTROL:
405 case WM831X_GPIO16_CONTROL:
406 case WM831X_CHARGER_CONTROL_1:
407 case WM831X_CHARGER_CONTROL_2:
408 case WM831X_CHARGER_STATUS:
409 case WM831X_BACKUP_CHARGER_CONTROL:
410 case WM831X_STATUS_LED_1:
411 case WM831X_STATUS_LED_2:
412 case WM831X_CURRENT_SINK_1:
413 case WM831X_CURRENT_SINK_2:
414 case WM831X_DCDC_ENABLE:
415 case WM831X_LDO_ENABLE:
416 case WM831X_DC1_CONTROL_1:
417 case WM831X_DC1_CONTROL_2:
418 case WM831X_DC1_ON_CONFIG:
419 case WM831X_DC1_SLEEP_CONTROL:
420 case WM831X_DC1_DVS_CONTROL:
421 case WM831X_DC2_CONTROL_1:
422 case WM831X_DC2_CONTROL_2:
423 case WM831X_DC2_ON_CONFIG:
424 case WM831X_DC2_SLEEP_CONTROL:
425 case WM831X_DC2_DVS_CONTROL:
426 case WM831X_DC3_CONTROL_1:
427 case WM831X_DC3_CONTROL_2:
428 case WM831X_DC3_ON_CONFIG:
429 case WM831X_DC3_SLEEP_CONTROL:
430 case WM831X_DC4_CONTROL:
431 case WM831X_DC4_SLEEP_CONTROL:
432 case WM831X_EPE1_CONTROL:
433 case WM831X_EPE2_CONTROL:
434 case WM831X_LDO1_CONTROL:
435 case WM831X_LDO1_ON_CONTROL:
436 case WM831X_LDO1_SLEEP_CONTROL:
437 case WM831X_LDO2_CONTROL:
438 case WM831X_LDO2_ON_CONTROL:
439 case WM831X_LDO2_SLEEP_CONTROL:
440 case WM831X_LDO3_CONTROL:
441 case WM831X_LDO3_ON_CONTROL:
442 case WM831X_LDO3_SLEEP_CONTROL:
443 case WM831X_LDO4_CONTROL:
444 case WM831X_LDO4_ON_CONTROL:
445 case WM831X_LDO4_SLEEP_CONTROL:
446 case WM831X_LDO5_CONTROL:
447 case WM831X_LDO5_ON_CONTROL:
448 case WM831X_LDO5_SLEEP_CONTROL:
449 case WM831X_LDO6_CONTROL:
450 case WM831X_LDO6_ON_CONTROL:
451 case WM831X_LDO6_SLEEP_CONTROL:
452 case WM831X_LDO7_CONTROL:
453 case WM831X_LDO7_ON_CONTROL:
454 case WM831X_LDO7_SLEEP_CONTROL:
455 case WM831X_LDO8_CONTROL:
456 case WM831X_LDO8_ON_CONTROL:
457 case WM831X_LDO8_SLEEP_CONTROL:
458 case WM831X_LDO9_CONTROL:
459 case WM831X_LDO9_ON_CONTROL:
460 case WM831X_LDO9_SLEEP_CONTROL:
461 case WM831X_LDO10_CONTROL:
462 case WM831X_LDO10_ON_CONTROL:
463 case WM831X_LDO10_SLEEP_CONTROL:
464 case WM831X_LDO11_ON_CONTROL:
465 case WM831X_LDO11_SLEEP_CONTROL:
466 case WM831X_POWER_GOOD_SOURCE_1:
467 case WM831X_POWER_GOOD_SOURCE_2:
468 case WM831X_CLOCK_CONTROL_1:
469 case WM831X_CLOCK_CONTROL_2:
470 case WM831X_FLL_CONTROL_1:
471 case WM831X_FLL_CONTROL_2:
472 case WM831X_FLL_CONTROL_3:
473 case WM831X_FLL_CONTROL_4:
474 case WM831X_FLL_CONTROL_5:
475 return true;
476 default:
477 return false;
478 }
479}
480
481static bool wm831x_reg_volatile(struct device *dev, unsigned int reg)
482{
483 switch (reg) {
484 case WM831X_SYSTEM_STATUS:
485 case WM831X_ON_SOURCE:
486 case WM831X_OFF_SOURCE:
487 case WM831X_GPIO_LEVEL:
488 case WM831X_SYSTEM_INTERRUPTS:
489 case WM831X_INTERRUPT_STATUS_1:
490 case WM831X_INTERRUPT_STATUS_2:
491 case WM831X_INTERRUPT_STATUS_3:
492 case WM831X_INTERRUPT_STATUS_4:
493 case WM831X_INTERRUPT_STATUS_5:
494 case WM831X_RTC_TIME_1:
495 case WM831X_RTC_TIME_2:
496 case WM831X_TOUCH_DATA_X:
497 case WM831X_TOUCH_DATA_Y:
498 case WM831X_TOUCH_DATA_Z:
499 case WM831X_AUXADC_DATA:
500 case WM831X_CHARGER_STATUS:
501 case WM831X_DCDC_STATUS:
502 case WM831X_LDO_STATUS:
503 case WM831X_DCDC_UV_STATUS:
504 case WM831X_LDO_UV_STATUS:
505 return true;
506 default:
507 return false;
508 }
509}
510
Mark Brownd2bedfe2009-07-27 14:45:52 +0100511/**
512 * wm831x_reg_read: Read a single WM831x register.
513 *
514 * @wm831x: Device to read from.
515 * @reg: Register to read.
516 */
517int wm831x_reg_read(struct wm831x *wm831x, unsigned short reg)
518{
Mark Brown1df59812011-06-10 19:28:10 +0100519 unsigned int val;
Mark Brownd2bedfe2009-07-27 14:45:52 +0100520 int ret;
521
Mark Brown1df59812011-06-10 19:28:10 +0100522 ret = regmap_read(wm831x->regmap, reg, &val);
Mark Brownd2bedfe2009-07-27 14:45:52 +0100523
524 if (ret < 0)
525 return ret;
526 else
527 return val;
528}
529EXPORT_SYMBOL_GPL(wm831x_reg_read);
530
531/**
532 * wm831x_bulk_read: Read multiple WM831x registers
533 *
534 * @wm831x: Device to read from
535 * @reg: First register
536 * @count: Number of registers
537 * @buf: Buffer to fill.
538 */
539int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg,
540 int count, u16 *buf)
541{
Mark Brown1df59812011-06-10 19:28:10 +0100542 return regmap_bulk_read(wm831x->regmap, reg, buf, count);
Mark Brownd2bedfe2009-07-27 14:45:52 +0100543}
544EXPORT_SYMBOL_GPL(wm831x_bulk_read);
545
546static int wm831x_write(struct wm831x *wm831x, unsigned short reg,
547 int bytes, void *src)
548{
549 u16 *buf = src;
Mark Brown1df59812011-06-10 19:28:10 +0100550 int i, ret;
Mark Brownd2bedfe2009-07-27 14:45:52 +0100551
552 BUG_ON(bytes % 2);
553 BUG_ON(bytes <= 0);
554
555 for (i = 0; i < bytes / 2; i++) {
556 if (wm831x_reg_locked(wm831x, reg))
557 return -EPERM;
558
559 dev_vdbg(wm831x->dev, "Write %04x to R%d(0x%x)\n",
560 buf[i], reg + i, reg + i);
Mark Brown1df59812011-06-10 19:28:10 +0100561 ret = regmap_write(wm831x->regmap, reg + i, buf[i]);
Mark Brown5391b5c2011-12-05 12:01:07 +0000562 if (ret != 0)
563 return ret;
Mark Brownd2bedfe2009-07-27 14:45:52 +0100564 }
565
Mark Brown1df59812011-06-10 19:28:10 +0100566 return 0;
Mark Brownd2bedfe2009-07-27 14:45:52 +0100567}
568
569/**
570 * wm831x_reg_write: Write a single WM831x register.
571 *
572 * @wm831x: Device to write to.
573 * @reg: Register to write to.
574 * @val: Value to write.
575 */
576int wm831x_reg_write(struct wm831x *wm831x, unsigned short reg,
577 unsigned short val)
578{
579 int ret;
580
581 mutex_lock(&wm831x->io_lock);
582
583 ret = wm831x_write(wm831x, reg, 2, &val);
584
585 mutex_unlock(&wm831x->io_lock);
586
587 return ret;
588}
589EXPORT_SYMBOL_GPL(wm831x_reg_write);
590
591/**
592 * wm831x_set_bits: Set the value of a bitfield in a WM831x register
593 *
594 * @wm831x: Device to write to.
595 * @reg: Register to write to.
596 * @mask: Mask of bits to set.
597 * @val: Value to set (unshifted)
598 */
599int wm831x_set_bits(struct wm831x *wm831x, unsigned short reg,
600 unsigned short mask, unsigned short val)
601{
602 int ret;
Mark Brownd2bedfe2009-07-27 14:45:52 +0100603
604 mutex_lock(&wm831x->io_lock);
605
Mark Brown1df59812011-06-10 19:28:10 +0100606 if (!wm831x_reg_locked(wm831x, reg))
607 ret = regmap_update_bits(wm831x->regmap, reg, mask, val);
608 else
609 ret = -EPERM;
Mark Brownd2bedfe2009-07-27 14:45:52 +0100610
Mark Brownd2bedfe2009-07-27 14:45:52 +0100611 mutex_unlock(&wm831x->io_lock);
612
613 return ret;
614}
615EXPORT_SYMBOL_GPL(wm831x_set_bits);
616
617static struct resource wm831x_dcdc1_resources[] = {
618 {
619 .start = WM831X_DC1_CONTROL_1,
620 .end = WM831X_DC1_DVS_CONTROL,
Mark Brown56560982012-08-07 19:42:47 +0100621 .flags = IORESOURCE_REG,
Mark Brownd2bedfe2009-07-27 14:45:52 +0100622 },
623 {
624 .name = "UV",
625 .start = WM831X_IRQ_UV_DC1,
626 .end = WM831X_IRQ_UV_DC1,
627 .flags = IORESOURCE_IRQ,
628 },
629 {
630 .name = "HC",
631 .start = WM831X_IRQ_HC_DC1,
632 .end = WM831X_IRQ_HC_DC1,
633 .flags = IORESOURCE_IRQ,
634 },
635};
636
637
638static struct resource wm831x_dcdc2_resources[] = {
639 {
640 .start = WM831X_DC2_CONTROL_1,
641 .end = WM831X_DC2_DVS_CONTROL,
Mark Brown56560982012-08-07 19:42:47 +0100642 .flags = IORESOURCE_REG,
Mark Brownd2bedfe2009-07-27 14:45:52 +0100643 },
644 {
645 .name = "UV",
646 .start = WM831X_IRQ_UV_DC2,
647 .end = WM831X_IRQ_UV_DC2,
648 .flags = IORESOURCE_IRQ,
649 },
650 {
651 .name = "HC",
652 .start = WM831X_IRQ_HC_DC2,
653 .end = WM831X_IRQ_HC_DC2,
654 .flags = IORESOURCE_IRQ,
655 },
656};
657
658static struct resource wm831x_dcdc3_resources[] = {
659 {
660 .start = WM831X_DC3_CONTROL_1,
661 .end = WM831X_DC3_SLEEP_CONTROL,
Mark Brown56560982012-08-07 19:42:47 +0100662 .flags = IORESOURCE_REG,
Mark Brownd2bedfe2009-07-27 14:45:52 +0100663 },
664 {
665 .name = "UV",
666 .start = WM831X_IRQ_UV_DC3,
667 .end = WM831X_IRQ_UV_DC3,
668 .flags = IORESOURCE_IRQ,
669 },
670};
671
672static struct resource wm831x_dcdc4_resources[] = {
673 {
674 .start = WM831X_DC4_CONTROL,
675 .end = WM831X_DC4_SLEEP_CONTROL,
Mark Brown56560982012-08-07 19:42:47 +0100676 .flags = IORESOURCE_REG,
Mark Brownd2bedfe2009-07-27 14:45:52 +0100677 },
678 {
679 .name = "UV",
680 .start = WM831X_IRQ_UV_DC4,
681 .end = WM831X_IRQ_UV_DC4,
682 .flags = IORESOURCE_IRQ,
683 },
684};
685
Mark Brownd4e0a892009-10-01 15:41:07 +0100686static struct resource wm8320_dcdc4_buck_resources[] = {
687 {
688 .start = WM831X_DC4_CONTROL,
689 .end = WM832X_DC4_SLEEP_CONTROL,
Mark Brown56560982012-08-07 19:42:47 +0100690 .flags = IORESOURCE_REG,
Mark Brownd4e0a892009-10-01 15:41:07 +0100691 },
692 {
693 .name = "UV",
694 .start = WM831X_IRQ_UV_DC4,
695 .end = WM831X_IRQ_UV_DC4,
696 .flags = IORESOURCE_IRQ,
697 },
698};
699
Mark Brownd2bedfe2009-07-27 14:45:52 +0100700static struct resource wm831x_gpio_resources[] = {
701 {
702 .start = WM831X_IRQ_GPIO_1,
703 .end = WM831X_IRQ_GPIO_16,
704 .flags = IORESOURCE_IRQ,
705 },
706};
707
708static struct resource wm831x_isink1_resources[] = {
709 {
710 .start = WM831X_CURRENT_SINK_1,
711 .end = WM831X_CURRENT_SINK_1,
Mark Brown56560982012-08-07 19:42:47 +0100712 .flags = IORESOURCE_REG,
Mark Brownd2bedfe2009-07-27 14:45:52 +0100713 },
714 {
715 .start = WM831X_IRQ_CS1,
716 .end = WM831X_IRQ_CS1,
717 .flags = IORESOURCE_IRQ,
718 },
719};
720
721static struct resource wm831x_isink2_resources[] = {
722 {
723 .start = WM831X_CURRENT_SINK_2,
724 .end = WM831X_CURRENT_SINK_2,
Mark Brown56560982012-08-07 19:42:47 +0100725 .flags = IORESOURCE_REG,
Mark Brownd2bedfe2009-07-27 14:45:52 +0100726 },
727 {
728 .start = WM831X_IRQ_CS2,
729 .end = WM831X_IRQ_CS2,
730 .flags = IORESOURCE_IRQ,
731 },
732};
733
734static struct resource wm831x_ldo1_resources[] = {
735 {
736 .start = WM831X_LDO1_CONTROL,
737 .end = WM831X_LDO1_SLEEP_CONTROL,
Mark Brown56560982012-08-07 19:42:47 +0100738 .flags = IORESOURCE_REG,
Mark Brownd2bedfe2009-07-27 14:45:52 +0100739 },
740 {
741 .name = "UV",
742 .start = WM831X_IRQ_UV_LDO1,
743 .end = WM831X_IRQ_UV_LDO1,
744 .flags = IORESOURCE_IRQ,
745 },
746};
747
748static struct resource wm831x_ldo2_resources[] = {
749 {
750 .start = WM831X_LDO2_CONTROL,
751 .end = WM831X_LDO2_SLEEP_CONTROL,
Mark Brown56560982012-08-07 19:42:47 +0100752 .flags = IORESOURCE_REG,
Mark Brownd2bedfe2009-07-27 14:45:52 +0100753 },
754 {
755 .name = "UV",
756 .start = WM831X_IRQ_UV_LDO2,
757 .end = WM831X_IRQ_UV_LDO2,
758 .flags = IORESOURCE_IRQ,
759 },
760};
761
762static struct resource wm831x_ldo3_resources[] = {
763 {
764 .start = WM831X_LDO3_CONTROL,
765 .end = WM831X_LDO3_SLEEP_CONTROL,
Mark Brown56560982012-08-07 19:42:47 +0100766 .flags = IORESOURCE_REG,
Mark Brownd2bedfe2009-07-27 14:45:52 +0100767 },
768 {
769 .name = "UV",
770 .start = WM831X_IRQ_UV_LDO3,
771 .end = WM831X_IRQ_UV_LDO3,
772 .flags = IORESOURCE_IRQ,
773 },
774};
775
776static struct resource wm831x_ldo4_resources[] = {
777 {
778 .start = WM831X_LDO4_CONTROL,
779 .end = WM831X_LDO4_SLEEP_CONTROL,
Mark Brown56560982012-08-07 19:42:47 +0100780 .flags = IORESOURCE_REG,
Mark Brownd2bedfe2009-07-27 14:45:52 +0100781 },
782 {
783 .name = "UV",
784 .start = WM831X_IRQ_UV_LDO4,
785 .end = WM831X_IRQ_UV_LDO4,
786 .flags = IORESOURCE_IRQ,
787 },
788};
789
790static struct resource wm831x_ldo5_resources[] = {
791 {
792 .start = WM831X_LDO5_CONTROL,
793 .end = WM831X_LDO5_SLEEP_CONTROL,
Mark Brown56560982012-08-07 19:42:47 +0100794 .flags = IORESOURCE_REG,
Mark Brownd2bedfe2009-07-27 14:45:52 +0100795 },
796 {
797 .name = "UV",
798 .start = WM831X_IRQ_UV_LDO5,
799 .end = WM831X_IRQ_UV_LDO5,
800 .flags = IORESOURCE_IRQ,
801 },
802};
803
804static struct resource wm831x_ldo6_resources[] = {
805 {
806 .start = WM831X_LDO6_CONTROL,
807 .end = WM831X_LDO6_SLEEP_CONTROL,
Mark Brown56560982012-08-07 19:42:47 +0100808 .flags = IORESOURCE_REG,
Mark Brownd2bedfe2009-07-27 14:45:52 +0100809 },
810 {
811 .name = "UV",
812 .start = WM831X_IRQ_UV_LDO6,
813 .end = WM831X_IRQ_UV_LDO6,
814 .flags = IORESOURCE_IRQ,
815 },
816};
817
818static struct resource wm831x_ldo7_resources[] = {
819 {
820 .start = WM831X_LDO7_CONTROL,
821 .end = WM831X_LDO7_SLEEP_CONTROL,
Mark Brown56560982012-08-07 19:42:47 +0100822 .flags = IORESOURCE_REG,
Mark Brownd2bedfe2009-07-27 14:45:52 +0100823 },
824 {
825 .name = "UV",
826 .start = WM831X_IRQ_UV_LDO7,
827 .end = WM831X_IRQ_UV_LDO7,
828 .flags = IORESOURCE_IRQ,
829 },
830};
831
832static struct resource wm831x_ldo8_resources[] = {
833 {
834 .start = WM831X_LDO8_CONTROL,
835 .end = WM831X_LDO8_SLEEP_CONTROL,
Mark Brown56560982012-08-07 19:42:47 +0100836 .flags = IORESOURCE_REG,
Mark Brownd2bedfe2009-07-27 14:45:52 +0100837 },
838 {
839 .name = "UV",
840 .start = WM831X_IRQ_UV_LDO8,
841 .end = WM831X_IRQ_UV_LDO8,
842 .flags = IORESOURCE_IRQ,
843 },
844};
845
846static struct resource wm831x_ldo9_resources[] = {
847 {
848 .start = WM831X_LDO9_CONTROL,
849 .end = WM831X_LDO9_SLEEP_CONTROL,
Mark Brown56560982012-08-07 19:42:47 +0100850 .flags = IORESOURCE_REG,
Mark Brownd2bedfe2009-07-27 14:45:52 +0100851 },
852 {
853 .name = "UV",
854 .start = WM831X_IRQ_UV_LDO9,
855 .end = WM831X_IRQ_UV_LDO9,
856 .flags = IORESOURCE_IRQ,
857 },
858};
859
860static struct resource wm831x_ldo10_resources[] = {
861 {
862 .start = WM831X_LDO10_CONTROL,
863 .end = WM831X_LDO10_SLEEP_CONTROL,
Mark Brown56560982012-08-07 19:42:47 +0100864 .flags = IORESOURCE_REG,
Mark Brownd2bedfe2009-07-27 14:45:52 +0100865 },
866 {
867 .name = "UV",
868 .start = WM831X_IRQ_UV_LDO10,
869 .end = WM831X_IRQ_UV_LDO10,
870 .flags = IORESOURCE_IRQ,
871 },
872};
873
874static struct resource wm831x_ldo11_resources[] = {
875 {
876 .start = WM831X_LDO11_ON_CONTROL,
877 .end = WM831X_LDO11_SLEEP_CONTROL,
Mark Brown56560982012-08-07 19:42:47 +0100878 .flags = IORESOURCE_REG,
Mark Brownd2bedfe2009-07-27 14:45:52 +0100879 },
880};
881
882static struct resource wm831x_on_resources[] = {
883 {
884 .start = WM831X_IRQ_ON,
885 .end = WM831X_IRQ_ON,
886 .flags = IORESOURCE_IRQ,
887 },
888};
889
890
891static struct resource wm831x_power_resources[] = {
892 {
893 .name = "SYSLO",
894 .start = WM831X_IRQ_PPM_SYSLO,
895 .end = WM831X_IRQ_PPM_SYSLO,
896 .flags = IORESOURCE_IRQ,
897 },
898 {
899 .name = "PWR SRC",
900 .start = WM831X_IRQ_PPM_PWR_SRC,
901 .end = WM831X_IRQ_PPM_PWR_SRC,
902 .flags = IORESOURCE_IRQ,
903 },
904 {
905 .name = "USB CURR",
906 .start = WM831X_IRQ_PPM_USB_CURR,
907 .end = WM831X_IRQ_PPM_USB_CURR,
908 .flags = IORESOURCE_IRQ,
909 },
910 {
911 .name = "BATT HOT",
912 .start = WM831X_IRQ_CHG_BATT_HOT,
913 .end = WM831X_IRQ_CHG_BATT_HOT,
914 .flags = IORESOURCE_IRQ,
915 },
916 {
917 .name = "BATT COLD",
918 .start = WM831X_IRQ_CHG_BATT_COLD,
919 .end = WM831X_IRQ_CHG_BATT_COLD,
920 .flags = IORESOURCE_IRQ,
921 },
922 {
923 .name = "BATT FAIL",
924 .start = WM831X_IRQ_CHG_BATT_FAIL,
925 .end = WM831X_IRQ_CHG_BATT_FAIL,
926 .flags = IORESOURCE_IRQ,
927 },
928 {
929 .name = "OV",
930 .start = WM831X_IRQ_CHG_OV,
931 .end = WM831X_IRQ_CHG_OV,
932 .flags = IORESOURCE_IRQ,
933 },
934 {
935 .name = "END",
936 .start = WM831X_IRQ_CHG_END,
937 .end = WM831X_IRQ_CHG_END,
938 .flags = IORESOURCE_IRQ,
939 },
940 {
941 .name = "TO",
942 .start = WM831X_IRQ_CHG_TO,
943 .end = WM831X_IRQ_CHG_TO,
944 .flags = IORESOURCE_IRQ,
945 },
946 {
947 .name = "MODE",
948 .start = WM831X_IRQ_CHG_MODE,
949 .end = WM831X_IRQ_CHG_MODE,
950 .flags = IORESOURCE_IRQ,
951 },
952 {
953 .name = "START",
954 .start = WM831X_IRQ_CHG_START,
955 .end = WM831X_IRQ_CHG_START,
956 .flags = IORESOURCE_IRQ,
957 },
958};
959
960static struct resource wm831x_rtc_resources[] = {
961 {
962 .name = "PER",
963 .start = WM831X_IRQ_RTC_PER,
964 .end = WM831X_IRQ_RTC_PER,
965 .flags = IORESOURCE_IRQ,
966 },
967 {
968 .name = "ALM",
969 .start = WM831X_IRQ_RTC_ALM,
970 .end = WM831X_IRQ_RTC_ALM,
971 .flags = IORESOURCE_IRQ,
972 },
973};
974
975static struct resource wm831x_status1_resources[] = {
976 {
977 .start = WM831X_STATUS_LED_1,
978 .end = WM831X_STATUS_LED_1,
Mark Brown56560982012-08-07 19:42:47 +0100979 .flags = IORESOURCE_REG,
Mark Brownd2bedfe2009-07-27 14:45:52 +0100980 },
981};
982
983static struct resource wm831x_status2_resources[] = {
984 {
985 .start = WM831X_STATUS_LED_2,
986 .end = WM831X_STATUS_LED_2,
Mark Brown56560982012-08-07 19:42:47 +0100987 .flags = IORESOURCE_REG,
Mark Brownd2bedfe2009-07-27 14:45:52 +0100988 },
989};
990
991static struct resource wm831x_touch_resources[] = {
992 {
993 .name = "TCHPD",
994 .start = WM831X_IRQ_TCHPD,
995 .end = WM831X_IRQ_TCHPD,
996 .flags = IORESOURCE_IRQ,
997 },
998 {
999 .name = "TCHDATA",
1000 .start = WM831X_IRQ_TCHDATA,
1001 .end = WM831X_IRQ_TCHDATA,
1002 .flags = IORESOURCE_IRQ,
1003 },
1004};
1005
1006static struct resource wm831x_wdt_resources[] = {
1007 {
1008 .start = WM831X_IRQ_WDOG_TO,
1009 .end = WM831X_IRQ_WDOG_TO,
1010 .flags = IORESOURCE_IRQ,
1011 },
1012};
1013
Geert Uytterhoevenad59de42013-11-18 14:33:04 +01001014static const struct mfd_cell wm8310_devs[] = {
Mark Brownd2bedfe2009-07-27 14:45:52 +01001015 {
Mark Brownc26964e2009-10-01 15:41:06 +01001016 .name = "wm831x-backup",
1017 },
1018 {
Mark Brownd2bedfe2009-07-27 14:45:52 +01001019 .name = "wm831x-buckv",
1020 .id = 1,
1021 .num_resources = ARRAY_SIZE(wm831x_dcdc1_resources),
1022 .resources = wm831x_dcdc1_resources,
1023 },
1024 {
1025 .name = "wm831x-buckv",
1026 .id = 2,
1027 .num_resources = ARRAY_SIZE(wm831x_dcdc2_resources),
1028 .resources = wm831x_dcdc2_resources,
1029 },
1030 {
1031 .name = "wm831x-buckp",
1032 .id = 3,
1033 .num_resources = ARRAY_SIZE(wm831x_dcdc3_resources),
1034 .resources = wm831x_dcdc3_resources,
1035 },
1036 {
1037 .name = "wm831x-boostp",
1038 .id = 4,
1039 .num_resources = ARRAY_SIZE(wm831x_dcdc4_resources),
1040 .resources = wm831x_dcdc4_resources,
1041 },
1042 {
Mark Browna5e06782011-06-24 12:17:07 +01001043 .name = "wm831x-clk",
1044 },
1045 {
Mark Brownd2bedfe2009-07-27 14:45:52 +01001046 .name = "wm831x-epe",
1047 .id = 1,
1048 },
1049 {
1050 .name = "wm831x-epe",
1051 .id = 2,
1052 },
1053 {
1054 .name = "wm831x-gpio",
1055 .num_resources = ARRAY_SIZE(wm831x_gpio_resources),
1056 .resources = wm831x_gpio_resources,
1057 },
1058 {
1059 .name = "wm831x-hwmon",
1060 },
1061 {
1062 .name = "wm831x-isink",
1063 .id = 1,
1064 .num_resources = ARRAY_SIZE(wm831x_isink1_resources),
1065 .resources = wm831x_isink1_resources,
1066 },
1067 {
1068 .name = "wm831x-isink",
1069 .id = 2,
1070 .num_resources = ARRAY_SIZE(wm831x_isink2_resources),
1071 .resources = wm831x_isink2_resources,
1072 },
1073 {
1074 .name = "wm831x-ldo",
1075 .id = 1,
1076 .num_resources = ARRAY_SIZE(wm831x_ldo1_resources),
1077 .resources = wm831x_ldo1_resources,
1078 },
1079 {
1080 .name = "wm831x-ldo",
1081 .id = 2,
1082 .num_resources = ARRAY_SIZE(wm831x_ldo2_resources),
1083 .resources = wm831x_ldo2_resources,
1084 },
1085 {
1086 .name = "wm831x-ldo",
1087 .id = 3,
1088 .num_resources = ARRAY_SIZE(wm831x_ldo3_resources),
1089 .resources = wm831x_ldo3_resources,
1090 },
1091 {
1092 .name = "wm831x-ldo",
1093 .id = 4,
1094 .num_resources = ARRAY_SIZE(wm831x_ldo4_resources),
1095 .resources = wm831x_ldo4_resources,
1096 },
1097 {
1098 .name = "wm831x-ldo",
1099 .id = 5,
1100 .num_resources = ARRAY_SIZE(wm831x_ldo5_resources),
1101 .resources = wm831x_ldo5_resources,
1102 },
1103 {
1104 .name = "wm831x-ldo",
1105 .id = 6,
1106 .num_resources = ARRAY_SIZE(wm831x_ldo6_resources),
1107 .resources = wm831x_ldo6_resources,
1108 },
1109 {
1110 .name = "wm831x-aldo",
1111 .id = 7,
1112 .num_resources = ARRAY_SIZE(wm831x_ldo7_resources),
1113 .resources = wm831x_ldo7_resources,
1114 },
1115 {
1116 .name = "wm831x-aldo",
1117 .id = 8,
1118 .num_resources = ARRAY_SIZE(wm831x_ldo8_resources),
1119 .resources = wm831x_ldo8_resources,
1120 },
1121 {
1122 .name = "wm831x-aldo",
1123 .id = 9,
1124 .num_resources = ARRAY_SIZE(wm831x_ldo9_resources),
1125 .resources = wm831x_ldo9_resources,
1126 },
1127 {
1128 .name = "wm831x-aldo",
1129 .id = 10,
1130 .num_resources = ARRAY_SIZE(wm831x_ldo10_resources),
1131 .resources = wm831x_ldo10_resources,
1132 },
1133 {
1134 .name = "wm831x-alive-ldo",
1135 .id = 11,
1136 .num_resources = ARRAY_SIZE(wm831x_ldo11_resources),
1137 .resources = wm831x_ldo11_resources,
1138 },
1139 {
1140 .name = "wm831x-on",
1141 .num_resources = ARRAY_SIZE(wm831x_on_resources),
1142 .resources = wm831x_on_resources,
1143 },
1144 {
1145 .name = "wm831x-power",
1146 .num_resources = ARRAY_SIZE(wm831x_power_resources),
1147 .resources = wm831x_power_resources,
1148 },
1149 {
Mark Brownd2bedfe2009-07-27 14:45:52 +01001150 .name = "wm831x-status",
1151 .id = 1,
1152 .num_resources = ARRAY_SIZE(wm831x_status1_resources),
1153 .resources = wm831x_status1_resources,
1154 },
1155 {
1156 .name = "wm831x-status",
1157 .id = 2,
1158 .num_resources = ARRAY_SIZE(wm831x_status2_resources),
1159 .resources = wm831x_status2_resources,
1160 },
1161 {
1162 .name = "wm831x-watchdog",
1163 .num_resources = ARRAY_SIZE(wm831x_wdt_resources),
1164 .resources = wm831x_wdt_resources,
1165 },
1166};
1167
Geert Uytterhoevenad59de42013-11-18 14:33:04 +01001168static const struct mfd_cell wm8311_devs[] = {
Mark Brownd2bedfe2009-07-27 14:45:52 +01001169 {
Mark Brownc26964e2009-10-01 15:41:06 +01001170 .name = "wm831x-backup",
1171 },
1172 {
Mark Brownd2bedfe2009-07-27 14:45:52 +01001173 .name = "wm831x-buckv",
1174 .id = 1,
1175 .num_resources = ARRAY_SIZE(wm831x_dcdc1_resources),
1176 .resources = wm831x_dcdc1_resources,
1177 },
1178 {
1179 .name = "wm831x-buckv",
1180 .id = 2,
1181 .num_resources = ARRAY_SIZE(wm831x_dcdc2_resources),
1182 .resources = wm831x_dcdc2_resources,
1183 },
1184 {
1185 .name = "wm831x-buckp",
1186 .id = 3,
1187 .num_resources = ARRAY_SIZE(wm831x_dcdc3_resources),
1188 .resources = wm831x_dcdc3_resources,
1189 },
1190 {
1191 .name = "wm831x-boostp",
1192 .id = 4,
1193 .num_resources = ARRAY_SIZE(wm831x_dcdc4_resources),
1194 .resources = wm831x_dcdc4_resources,
1195 },
1196 {
Mark Browna5e06782011-06-24 12:17:07 +01001197 .name = "wm831x-clk",
1198 },
1199 {
Mark Brownd2bedfe2009-07-27 14:45:52 +01001200 .name = "wm831x-epe",
1201 .id = 1,
1202 },
1203 {
1204 .name = "wm831x-epe",
1205 .id = 2,
1206 },
1207 {
1208 .name = "wm831x-gpio",
1209 .num_resources = ARRAY_SIZE(wm831x_gpio_resources),
1210 .resources = wm831x_gpio_resources,
1211 },
1212 {
1213 .name = "wm831x-hwmon",
1214 },
1215 {
1216 .name = "wm831x-isink",
1217 .id = 1,
1218 .num_resources = ARRAY_SIZE(wm831x_isink1_resources),
1219 .resources = wm831x_isink1_resources,
1220 },
1221 {
1222 .name = "wm831x-isink",
1223 .id = 2,
1224 .num_resources = ARRAY_SIZE(wm831x_isink2_resources),
1225 .resources = wm831x_isink2_resources,
1226 },
1227 {
1228 .name = "wm831x-ldo",
1229 .id = 1,
1230 .num_resources = ARRAY_SIZE(wm831x_ldo1_resources),
1231 .resources = wm831x_ldo1_resources,
1232 },
1233 {
1234 .name = "wm831x-ldo",
1235 .id = 2,
1236 .num_resources = ARRAY_SIZE(wm831x_ldo2_resources),
1237 .resources = wm831x_ldo2_resources,
1238 },
1239 {
1240 .name = "wm831x-ldo",
1241 .id = 3,
1242 .num_resources = ARRAY_SIZE(wm831x_ldo3_resources),
1243 .resources = wm831x_ldo3_resources,
1244 },
1245 {
1246 .name = "wm831x-ldo",
1247 .id = 4,
1248 .num_resources = ARRAY_SIZE(wm831x_ldo4_resources),
1249 .resources = wm831x_ldo4_resources,
1250 },
1251 {
1252 .name = "wm831x-ldo",
1253 .id = 5,
1254 .num_resources = ARRAY_SIZE(wm831x_ldo5_resources),
1255 .resources = wm831x_ldo5_resources,
1256 },
1257 {
1258 .name = "wm831x-aldo",
1259 .id = 7,
1260 .num_resources = ARRAY_SIZE(wm831x_ldo7_resources),
1261 .resources = wm831x_ldo7_resources,
1262 },
1263 {
1264 .name = "wm831x-alive-ldo",
1265 .id = 11,
1266 .num_resources = ARRAY_SIZE(wm831x_ldo11_resources),
1267 .resources = wm831x_ldo11_resources,
1268 },
1269 {
1270 .name = "wm831x-on",
1271 .num_resources = ARRAY_SIZE(wm831x_on_resources),
1272 .resources = wm831x_on_resources,
1273 },
1274 {
1275 .name = "wm831x-power",
1276 .num_resources = ARRAY_SIZE(wm831x_power_resources),
1277 .resources = wm831x_power_resources,
1278 },
1279 {
Mark Brownd2bedfe2009-07-27 14:45:52 +01001280 .name = "wm831x-status",
1281 .id = 1,
1282 .num_resources = ARRAY_SIZE(wm831x_status1_resources),
1283 .resources = wm831x_status1_resources,
1284 },
1285 {
1286 .name = "wm831x-status",
1287 .id = 2,
1288 .num_resources = ARRAY_SIZE(wm831x_status2_resources),
1289 .resources = wm831x_status2_resources,
1290 },
1291 {
Mark Brownd2bedfe2009-07-27 14:45:52 +01001292 .name = "wm831x-watchdog",
1293 .num_resources = ARRAY_SIZE(wm831x_wdt_resources),
1294 .resources = wm831x_wdt_resources,
1295 },
1296};
1297
Geert Uytterhoevenad59de42013-11-18 14:33:04 +01001298static const struct mfd_cell wm8312_devs[] = {
Mark Brownd2bedfe2009-07-27 14:45:52 +01001299 {
Mark Brownc26964e2009-10-01 15:41:06 +01001300 .name = "wm831x-backup",
1301 },
1302 {
Mark Brownd2bedfe2009-07-27 14:45:52 +01001303 .name = "wm831x-buckv",
1304 .id = 1,
1305 .num_resources = ARRAY_SIZE(wm831x_dcdc1_resources),
1306 .resources = wm831x_dcdc1_resources,
1307 },
1308 {
1309 .name = "wm831x-buckv",
1310 .id = 2,
1311 .num_resources = ARRAY_SIZE(wm831x_dcdc2_resources),
1312 .resources = wm831x_dcdc2_resources,
1313 },
1314 {
1315 .name = "wm831x-buckp",
1316 .id = 3,
1317 .num_resources = ARRAY_SIZE(wm831x_dcdc3_resources),
1318 .resources = wm831x_dcdc3_resources,
1319 },
1320 {
1321 .name = "wm831x-boostp",
1322 .id = 4,
1323 .num_resources = ARRAY_SIZE(wm831x_dcdc4_resources),
1324 .resources = wm831x_dcdc4_resources,
1325 },
1326 {
Mark Browna5e06782011-06-24 12:17:07 +01001327 .name = "wm831x-clk",
1328 },
1329 {
Mark Brownd2bedfe2009-07-27 14:45:52 +01001330 .name = "wm831x-epe",
1331 .id = 1,
1332 },
1333 {
1334 .name = "wm831x-epe",
1335 .id = 2,
1336 },
1337 {
1338 .name = "wm831x-gpio",
1339 .num_resources = ARRAY_SIZE(wm831x_gpio_resources),
1340 .resources = wm831x_gpio_resources,
1341 },
1342 {
1343 .name = "wm831x-hwmon",
1344 },
1345 {
1346 .name = "wm831x-isink",
1347 .id = 1,
1348 .num_resources = ARRAY_SIZE(wm831x_isink1_resources),
1349 .resources = wm831x_isink1_resources,
1350 },
1351 {
1352 .name = "wm831x-isink",
1353 .id = 2,
1354 .num_resources = ARRAY_SIZE(wm831x_isink2_resources),
1355 .resources = wm831x_isink2_resources,
1356 },
1357 {
1358 .name = "wm831x-ldo",
1359 .id = 1,
1360 .num_resources = ARRAY_SIZE(wm831x_ldo1_resources),
1361 .resources = wm831x_ldo1_resources,
1362 },
1363 {
1364 .name = "wm831x-ldo",
1365 .id = 2,
1366 .num_resources = ARRAY_SIZE(wm831x_ldo2_resources),
1367 .resources = wm831x_ldo2_resources,
1368 },
1369 {
1370 .name = "wm831x-ldo",
1371 .id = 3,
1372 .num_resources = ARRAY_SIZE(wm831x_ldo3_resources),
1373 .resources = wm831x_ldo3_resources,
1374 },
1375 {
1376 .name = "wm831x-ldo",
1377 .id = 4,
1378 .num_resources = ARRAY_SIZE(wm831x_ldo4_resources),
1379 .resources = wm831x_ldo4_resources,
1380 },
1381 {
1382 .name = "wm831x-ldo",
1383 .id = 5,
1384 .num_resources = ARRAY_SIZE(wm831x_ldo5_resources),
1385 .resources = wm831x_ldo5_resources,
1386 },
1387 {
1388 .name = "wm831x-ldo",
1389 .id = 6,
1390 .num_resources = ARRAY_SIZE(wm831x_ldo6_resources),
1391 .resources = wm831x_ldo6_resources,
1392 },
1393 {
1394 .name = "wm831x-aldo",
1395 .id = 7,
1396 .num_resources = ARRAY_SIZE(wm831x_ldo7_resources),
1397 .resources = wm831x_ldo7_resources,
1398 },
1399 {
1400 .name = "wm831x-aldo",
1401 .id = 8,
1402 .num_resources = ARRAY_SIZE(wm831x_ldo8_resources),
1403 .resources = wm831x_ldo8_resources,
1404 },
1405 {
1406 .name = "wm831x-aldo",
1407 .id = 9,
1408 .num_resources = ARRAY_SIZE(wm831x_ldo9_resources),
1409 .resources = wm831x_ldo9_resources,
1410 },
1411 {
1412 .name = "wm831x-aldo",
1413 .id = 10,
1414 .num_resources = ARRAY_SIZE(wm831x_ldo10_resources),
1415 .resources = wm831x_ldo10_resources,
1416 },
1417 {
1418 .name = "wm831x-alive-ldo",
1419 .id = 11,
1420 .num_resources = ARRAY_SIZE(wm831x_ldo11_resources),
1421 .resources = wm831x_ldo11_resources,
1422 },
1423 {
1424 .name = "wm831x-on",
1425 .num_resources = ARRAY_SIZE(wm831x_on_resources),
1426 .resources = wm831x_on_resources,
1427 },
1428 {
1429 .name = "wm831x-power",
1430 .num_resources = ARRAY_SIZE(wm831x_power_resources),
1431 .resources = wm831x_power_resources,
1432 },
1433 {
Mark Brownd2bedfe2009-07-27 14:45:52 +01001434 .name = "wm831x-status",
1435 .id = 1,
1436 .num_resources = ARRAY_SIZE(wm831x_status1_resources),
1437 .resources = wm831x_status1_resources,
1438 },
1439 {
1440 .name = "wm831x-status",
1441 .id = 2,
1442 .num_resources = ARRAY_SIZE(wm831x_status2_resources),
1443 .resources = wm831x_status2_resources,
1444 },
1445 {
Mark Brownd2bedfe2009-07-27 14:45:52 +01001446 .name = "wm831x-watchdog",
1447 .num_resources = ARRAY_SIZE(wm831x_wdt_resources),
1448 .resources = wm831x_wdt_resources,
1449 },
1450};
1451
Geert Uytterhoevenad59de42013-11-18 14:33:04 +01001452static const struct mfd_cell wm8320_devs[] = {
Mark Brownd4e0a892009-10-01 15:41:07 +01001453 {
1454 .name = "wm831x-backup",
1455 },
1456 {
1457 .name = "wm831x-buckv",
1458 .id = 1,
1459 .num_resources = ARRAY_SIZE(wm831x_dcdc1_resources),
1460 .resources = wm831x_dcdc1_resources,
1461 },
1462 {
1463 .name = "wm831x-buckv",
1464 .id = 2,
1465 .num_resources = ARRAY_SIZE(wm831x_dcdc2_resources),
1466 .resources = wm831x_dcdc2_resources,
1467 },
1468 {
1469 .name = "wm831x-buckp",
1470 .id = 3,
1471 .num_resources = ARRAY_SIZE(wm831x_dcdc3_resources),
1472 .resources = wm831x_dcdc3_resources,
1473 },
1474 {
1475 .name = "wm831x-buckp",
1476 .id = 4,
1477 .num_resources = ARRAY_SIZE(wm8320_dcdc4_buck_resources),
1478 .resources = wm8320_dcdc4_buck_resources,
1479 },
1480 {
Mark Browna5e06782011-06-24 12:17:07 +01001481 .name = "wm831x-clk",
1482 },
1483 {
Mark Brownd4e0a892009-10-01 15:41:07 +01001484 .name = "wm831x-gpio",
1485 .num_resources = ARRAY_SIZE(wm831x_gpio_resources),
1486 .resources = wm831x_gpio_resources,
1487 },
1488 {
1489 .name = "wm831x-hwmon",
1490 },
1491 {
1492 .name = "wm831x-ldo",
1493 .id = 1,
1494 .num_resources = ARRAY_SIZE(wm831x_ldo1_resources),
1495 .resources = wm831x_ldo1_resources,
1496 },
1497 {
1498 .name = "wm831x-ldo",
1499 .id = 2,
1500 .num_resources = ARRAY_SIZE(wm831x_ldo2_resources),
1501 .resources = wm831x_ldo2_resources,
1502 },
1503 {
1504 .name = "wm831x-ldo",
1505 .id = 3,
1506 .num_resources = ARRAY_SIZE(wm831x_ldo3_resources),
1507 .resources = wm831x_ldo3_resources,
1508 },
1509 {
1510 .name = "wm831x-ldo",
1511 .id = 4,
1512 .num_resources = ARRAY_SIZE(wm831x_ldo4_resources),
1513 .resources = wm831x_ldo4_resources,
1514 },
1515 {
1516 .name = "wm831x-ldo",
1517 .id = 5,
1518 .num_resources = ARRAY_SIZE(wm831x_ldo5_resources),
1519 .resources = wm831x_ldo5_resources,
1520 },
1521 {
1522 .name = "wm831x-ldo",
1523 .id = 6,
1524 .num_resources = ARRAY_SIZE(wm831x_ldo6_resources),
1525 .resources = wm831x_ldo6_resources,
1526 },
1527 {
1528 .name = "wm831x-aldo",
1529 .id = 7,
1530 .num_resources = ARRAY_SIZE(wm831x_ldo7_resources),
1531 .resources = wm831x_ldo7_resources,
1532 },
1533 {
1534 .name = "wm831x-aldo",
1535 .id = 8,
1536 .num_resources = ARRAY_SIZE(wm831x_ldo8_resources),
1537 .resources = wm831x_ldo8_resources,
1538 },
1539 {
1540 .name = "wm831x-aldo",
1541 .id = 9,
1542 .num_resources = ARRAY_SIZE(wm831x_ldo9_resources),
1543 .resources = wm831x_ldo9_resources,
1544 },
1545 {
1546 .name = "wm831x-aldo",
1547 .id = 10,
1548 .num_resources = ARRAY_SIZE(wm831x_ldo10_resources),
1549 .resources = wm831x_ldo10_resources,
1550 },
1551 {
1552 .name = "wm831x-alive-ldo",
1553 .id = 11,
1554 .num_resources = ARRAY_SIZE(wm831x_ldo11_resources),
1555 .resources = wm831x_ldo11_resources,
1556 },
1557 {
1558 .name = "wm831x-on",
1559 .num_resources = ARRAY_SIZE(wm831x_on_resources),
1560 .resources = wm831x_on_resources,
1561 },
1562 {
Mark Brownd4e0a892009-10-01 15:41:07 +01001563 .name = "wm831x-status",
1564 .id = 1,
1565 .num_resources = ARRAY_SIZE(wm831x_status1_resources),
1566 .resources = wm831x_status1_resources,
1567 },
1568 {
1569 .name = "wm831x-status",
1570 .id = 2,
1571 .num_resources = ARRAY_SIZE(wm831x_status2_resources),
1572 .resources = wm831x_status2_resources,
1573 },
1574 {
1575 .name = "wm831x-watchdog",
1576 .num_resources = ARRAY_SIZE(wm831x_wdt_resources),
1577 .resources = wm831x_wdt_resources,
1578 },
1579};
1580
Geert Uytterhoevenad59de42013-11-18 14:33:04 +01001581static const struct mfd_cell touch_devs[] = {
Mark Brown266a5e02011-06-02 19:18:49 +01001582 {
1583 .name = "wm831x-touch",
1584 .num_resources = ARRAY_SIZE(wm831x_touch_resources),
1585 .resources = wm831x_touch_resources,
1586 },
1587};
1588
Geert Uytterhoevenad59de42013-11-18 14:33:04 +01001589static const struct mfd_cell rtc_devs[] = {
Mark Brownb9d03d92011-06-02 19:18:50 +01001590 {
1591 .name = "wm831x-rtc",
1592 .num_resources = ARRAY_SIZE(wm831x_rtc_resources),
1593 .resources = wm831x_rtc_resources,
1594 },
1595};
Mark Brown266a5e02011-06-02 19:18:49 +01001596
Geert Uytterhoevenad59de42013-11-18 14:33:04 +01001597static const struct mfd_cell backlight_devs[] = {
Mark Brown63aed852009-07-27 14:45:55 +01001598 {
1599 .name = "wm831x-backlight",
1600 },
1601};
1602
Mark Brown1df59812011-06-10 19:28:10 +01001603struct regmap_config wm831x_regmap_config = {
1604 .reg_bits = 16,
1605 .val_bits = 16,
Mark Brown2e47fff2011-07-21 17:30:08 +01001606
Mark Brown7cccbdc2011-10-09 13:38:06 +01001607 .cache_type = REGCACHE_RBTREE,
1608
Mark Brown2e47fff2011-07-21 17:30:08 +01001609 .max_register = WM831X_DBE_CHECK_DATA,
1610 .readable_reg = wm831x_reg_readable,
1611 .writeable_reg = wm831x_reg_writeable,
1612 .volatile_reg = wm831x_reg_volatile,
Mark Brown1df59812011-06-10 19:28:10 +01001613};
1614EXPORT_SYMBOL_GPL(wm831x_regmap_config);
1615
Mark Brownd2bedfe2009-07-27 14:45:52 +01001616/*
1617 * Instantiate the generic non-control parts of the device.
1618 */
Mark Browne5b48682010-10-19 23:57:56 +02001619int wm831x_device_init(struct wm831x *wm831x, unsigned long id, int irq)
Mark Brownd2bedfe2009-07-27 14:45:52 +01001620{
Jingoo Han334a41c2013-07-30 17:10:05 +09001621 struct wm831x_pdata *pdata = dev_get_platdata(wm831x->dev);
Mark Browneb503dc2011-06-02 19:18:48 +01001622 int rev, wm831x_num;
Mark Brownd2bedfe2009-07-27 14:45:52 +01001623 enum wm831x_parent parent;
Mark Brown0b14c222011-04-04 11:04:42 +09001624 int ret, i;
Mark Brownd2bedfe2009-07-27 14:45:52 +01001625
1626 mutex_init(&wm831x->io_lock);
1627 mutex_init(&wm831x->key_lock);
1628 dev_set_drvdata(wm831x->dev, wm831x);
Mark Brown523d9cf2011-09-15 18:54:53 +02001629 wm831x->soft_shutdown = pdata->soft_shutdown;
Mark Brownd2bedfe2009-07-27 14:45:52 +01001630
1631 ret = wm831x_reg_read(wm831x, WM831X_PARENT_ID);
1632 if (ret < 0) {
1633 dev_err(wm831x->dev, "Failed to read parent ID: %d\n", ret);
Mark Brown130a7032012-01-30 20:08:06 +00001634 goto err;
Mark Brownd2bedfe2009-07-27 14:45:52 +01001635 }
Mark Brownb93cef52010-12-02 16:25:43 +00001636 switch (ret) {
1637 case 0x6204:
1638 case 0x6246:
1639 break;
1640 default:
Mark Brownd2bedfe2009-07-27 14:45:52 +01001641 dev_err(wm831x->dev, "Device is not a WM831x: ID %x\n", ret);
1642 ret = -EINVAL;
Mark Brown130a7032012-01-30 20:08:06 +00001643 goto err;
Mark Brownd2bedfe2009-07-27 14:45:52 +01001644 }
1645
1646 ret = wm831x_reg_read(wm831x, WM831X_REVISION);
1647 if (ret < 0) {
1648 dev_err(wm831x->dev, "Failed to read revision: %d\n", ret);
Mark Brown130a7032012-01-30 20:08:06 +00001649 goto err;
Mark Brownd2bedfe2009-07-27 14:45:52 +01001650 }
1651 rev = (ret & WM831X_PARENT_REV_MASK) >> WM831X_PARENT_REV_SHIFT;
1652
1653 ret = wm831x_reg_read(wm831x, WM831X_RESET_ID);
1654 if (ret < 0) {
1655 dev_err(wm831x->dev, "Failed to read device ID: %d\n", ret);
Mark Brown130a7032012-01-30 20:08:06 +00001656 goto err;
Mark Brownd2bedfe2009-07-27 14:45:52 +01001657 }
1658
Mark Brown894362f2009-10-01 15:41:04 +01001659 /* Some engineering samples do not have the ID set, rely on
1660 * the device being registered correctly.
1661 */
1662 if (ret == 0) {
1663 dev_info(wm831x->dev, "Device is an engineering sample\n");
1664 ret = id;
1665 }
1666
Mark Brownd2bedfe2009-07-27 14:45:52 +01001667 switch (ret) {
Mark Brown894362f2009-10-01 15:41:04 +01001668 case WM8310:
Mark Brownd2bedfe2009-07-27 14:45:52 +01001669 parent = WM8310;
Mark Brown6f2ecaa2009-10-01 15:41:05 +01001670 wm831x->num_gpio = 16;
Mark Brownb03b4d7c2010-04-08 10:02:39 +02001671 wm831x->charger_irq_wake = 1;
Mark Brownf92e8f82010-02-17 18:45:25 +00001672 if (rev > 0) {
1673 wm831x->has_gpio_ena = 1;
1674 wm831x->has_cs_sts = 1;
1675 }
1676
Mark Brown894362f2009-10-01 15:41:04 +01001677 dev_info(wm831x->dev, "WM8310 revision %c\n", 'A' + rev);
Mark Brownd2bedfe2009-07-27 14:45:52 +01001678 break;
1679
Mark Brown894362f2009-10-01 15:41:04 +01001680 case WM8311:
Mark Brownd2bedfe2009-07-27 14:45:52 +01001681 parent = WM8311;
Mark Brown6f2ecaa2009-10-01 15:41:05 +01001682 wm831x->num_gpio = 16;
Mark Brownb03b4d7c2010-04-08 10:02:39 +02001683 wm831x->charger_irq_wake = 1;
Mark Brownf92e8f82010-02-17 18:45:25 +00001684 if (rev > 0) {
1685 wm831x->has_gpio_ena = 1;
1686 wm831x->has_cs_sts = 1;
1687 }
1688
Mark Brown894362f2009-10-01 15:41:04 +01001689 dev_info(wm831x->dev, "WM8311 revision %c\n", 'A' + rev);
Mark Brownd2bedfe2009-07-27 14:45:52 +01001690 break;
1691
Mark Brown894362f2009-10-01 15:41:04 +01001692 case WM8312:
Mark Brownd2bedfe2009-07-27 14:45:52 +01001693 parent = WM8312;
Mark Brown6f2ecaa2009-10-01 15:41:05 +01001694 wm831x->num_gpio = 16;
Mark Brownb03b4d7c2010-04-08 10:02:39 +02001695 wm831x->charger_irq_wake = 1;
Mark Brownf92e8f82010-02-17 18:45:25 +00001696 if (rev > 0) {
1697 wm831x->has_gpio_ena = 1;
1698 wm831x->has_cs_sts = 1;
1699 }
1700
Mark Brown894362f2009-10-01 15:41:04 +01001701 dev_info(wm831x->dev, "WM8312 revision %c\n", 'A' + rev);
Mark Brownd2bedfe2009-07-27 14:45:52 +01001702 break;
1703
Mark Brownd4e0a892009-10-01 15:41:07 +01001704 case WM8320:
1705 parent = WM8320;
1706 wm831x->num_gpio = 12;
1707 dev_info(wm831x->dev, "WM8320 revision %c\n", 'A' + rev);
1708 break;
1709
Mark Brown88913522010-07-21 14:23:37 +01001710 case WM8321:
1711 parent = WM8321;
1712 wm831x->num_gpio = 12;
1713 dev_info(wm831x->dev, "WM8321 revision %c\n", 'A' + rev);
1714 break;
1715
Mark Brown0b315882010-09-28 09:13:39 -07001716 case WM8325:
1717 parent = WM8325;
1718 wm831x->num_gpio = 12;
1719 dev_info(wm831x->dev, "WM8325 revision %c\n", 'A' + rev);
1720 break;
1721
Mark Brown412dc112010-11-24 18:01:41 +00001722 case WM8326:
1723 parent = WM8326;
1724 wm831x->num_gpio = 12;
1725 dev_info(wm831x->dev, "WM8326 revision %c\n", 'A' + rev);
1726 break;
1727
Mark Brownd2bedfe2009-07-27 14:45:52 +01001728 default:
1729 dev_err(wm831x->dev, "Unknown WM831x device %04x\n", ret);
1730 ret = -EINVAL;
Mark Brown130a7032012-01-30 20:08:06 +00001731 goto err;
Mark Brownd2bedfe2009-07-27 14:45:52 +01001732 }
1733
1734 /* This will need revisiting in future but is OK for all
1735 * current parts.
1736 */
1737 if (parent != id)
Mark Brown894362f2009-10-01 15:41:04 +01001738 dev_warn(wm831x->dev, "Device was registered as a WM%lx\n",
Mark Brownd2bedfe2009-07-27 14:45:52 +01001739 id);
1740
1741 /* Bootstrap the user key */
1742 ret = wm831x_reg_read(wm831x, WM831X_SECURITY_KEY);
1743 if (ret < 0) {
1744 dev_err(wm831x->dev, "Failed to read security key: %d\n", ret);
Mark Brown130a7032012-01-30 20:08:06 +00001745 goto err;
Mark Brownd2bedfe2009-07-27 14:45:52 +01001746 }
1747 if (ret != 0) {
1748 dev_warn(wm831x->dev, "Security key had non-zero value %x\n",
1749 ret);
1750 wm831x_reg_write(wm831x, WM831X_SECURITY_KEY, 0);
1751 }
1752 wm831x->locked = 1;
1753
1754 if (pdata && pdata->pre_init) {
1755 ret = pdata->pre_init(wm831x);
1756 if (ret != 0) {
1757 dev_err(wm831x->dev, "pre_init() failed: %d\n", ret);
Mark Brown130a7032012-01-30 20:08:06 +00001758 goto err;
Mark Brownd2bedfe2009-07-27 14:45:52 +01001759 }
1760 }
1761
Mark Brown0b14c222011-04-04 11:04:42 +09001762 if (pdata) {
1763 for (i = 0; i < ARRAY_SIZE(pdata->gpio_defaults); i++) {
1764 if (!pdata->gpio_defaults[i])
1765 continue;
1766
1767 wm831x_reg_write(wm831x,
1768 WM831X_GPIO1_CONTROL + i,
1769 pdata->gpio_defaults[i] & 0xffff);
1770 }
1771 }
1772
Mark Browneb503dc2011-06-02 19:18:48 +01001773 /* Multiply by 10 as we have many subdevices of the same type */
1774 if (pdata && pdata->wm831x_num)
1775 wm831x_num = pdata->wm831x_num * 10;
1776 else
1777 wm831x_num = -1;
1778
Mark Brown7d4d0a32009-07-27 14:45:53 +01001779 ret = wm831x_irq_init(wm831x, irq);
1780 if (ret != 0)
Mark Brown130a7032012-01-30 20:08:06 +00001781 goto err;
Mark Brown7d4d0a32009-07-27 14:45:53 +01001782
Mark Browne69b6de2011-06-02 19:18:53 +01001783 wm831x_auxadc_init(wm831x);
Mark Brown473fe732010-02-23 11:08:06 +00001784
Mark Brownd2bedfe2009-07-27 14:45:52 +01001785 /* The core device is up, instantiate the subdevices. */
1786 switch (parent) {
1787 case WM8310:
Mark Browneb503dc2011-06-02 19:18:48 +01001788 ret = mfd_add_devices(wm831x->dev, wm831x_num,
Mark Brownd2bedfe2009-07-27 14:45:52 +01001789 wm8310_devs, ARRAY_SIZE(wm8310_devs),
Mark Brown55692af2012-09-11 15:16:36 +08001790 NULL, 0, NULL);
Mark Brownd2bedfe2009-07-27 14:45:52 +01001791 break;
1792
1793 case WM8311:
Mark Browneb503dc2011-06-02 19:18:48 +01001794 ret = mfd_add_devices(wm831x->dev, wm831x_num,
Mark Brownd2bedfe2009-07-27 14:45:52 +01001795 wm8311_devs, ARRAY_SIZE(wm8311_devs),
Mark Brown55692af2012-09-11 15:16:36 +08001796 NULL, 0, NULL);
Mark Brown266a5e02011-06-02 19:18:49 +01001797 if (!pdata || !pdata->disable_touch)
1798 mfd_add_devices(wm831x->dev, wm831x_num,
1799 touch_devs, ARRAY_SIZE(touch_devs),
Mark Brown55692af2012-09-11 15:16:36 +08001800 NULL, 0, NULL);
Mark Brownd2bedfe2009-07-27 14:45:52 +01001801 break;
1802
1803 case WM8312:
Mark Browneb503dc2011-06-02 19:18:48 +01001804 ret = mfd_add_devices(wm831x->dev, wm831x_num,
Mark Brownd2bedfe2009-07-27 14:45:52 +01001805 wm8312_devs, ARRAY_SIZE(wm8312_devs),
Mark Brown55692af2012-09-11 15:16:36 +08001806 NULL, 0, NULL);
Mark Brown266a5e02011-06-02 19:18:49 +01001807 if (!pdata || !pdata->disable_touch)
1808 mfd_add_devices(wm831x->dev, wm831x_num,
1809 touch_devs, ARRAY_SIZE(touch_devs),
Mark Brown55692af2012-09-11 15:16:36 +08001810 NULL, 0, NULL);
Mark Brownd2bedfe2009-07-27 14:45:52 +01001811 break;
1812
Mark Brownd4e0a892009-10-01 15:41:07 +01001813 case WM8320:
Mark Brown88913522010-07-21 14:23:37 +01001814 case WM8321:
Mark Brown0b315882010-09-28 09:13:39 -07001815 case WM8325:
Mark Brown412dc112010-11-24 18:01:41 +00001816 case WM8326:
Mark Browneb503dc2011-06-02 19:18:48 +01001817 ret = mfd_add_devices(wm831x->dev, wm831x_num,
Mark Brown0b315882010-09-28 09:13:39 -07001818 wm8320_devs, ARRAY_SIZE(wm8320_devs),
Mark Brown55692af2012-09-11 15:16:36 +08001819 NULL, 0, NULL);
Mark Brown0b315882010-09-28 09:13:39 -07001820 break;
1821
Mark Brownd2bedfe2009-07-27 14:45:52 +01001822 default:
1823 /* If this happens the bus probe function is buggy */
1824 BUG();
1825 }
1826
1827 if (ret != 0) {
1828 dev_err(wm831x->dev, "Failed to add children\n");
Mark Brown7d4d0a32009-07-27 14:45:53 +01001829 goto err_irq;
Mark Brownd2bedfe2009-07-27 14:45:52 +01001830 }
1831
Mark Brownb9d03d92011-06-02 19:18:50 +01001832 /* The RTC can only be used if the 32.768kHz crystal is
1833 * enabled; this can't be controlled by software at runtime.
1834 */
1835 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
1836 if (ret < 0) {
1837 dev_err(wm831x->dev, "Failed to read clock status: %d\n", ret);
1838 goto err_irq;
1839 }
1840
1841 if (ret & WM831X_XTAL_ENA) {
1842 ret = mfd_add_devices(wm831x->dev, wm831x_num,
1843 rtc_devs, ARRAY_SIZE(rtc_devs),
Mark Brown55692af2012-09-11 15:16:36 +08001844 NULL, 0, NULL);
Mark Brownb9d03d92011-06-02 19:18:50 +01001845 if (ret != 0) {
1846 dev_err(wm831x->dev, "Failed to add RTC: %d\n", ret);
1847 goto err_irq;
1848 }
1849 } else {
1850 dev_info(wm831x->dev, "32.768kHz clock disabled, no RTC\n");
1851 }
1852
Mark Brown63aed852009-07-27 14:45:55 +01001853 if (pdata && pdata->backlight) {
1854 /* Treat errors as non-critical */
Mark Browneb503dc2011-06-02 19:18:48 +01001855 ret = mfd_add_devices(wm831x->dev, wm831x_num, backlight_devs,
Mark Brown5fb4d382009-11-11 16:10:22 +00001856 ARRAY_SIZE(backlight_devs), NULL,
Mark Brown55692af2012-09-11 15:16:36 +08001857 0, NULL);
Mark Brown63aed852009-07-27 14:45:55 +01001858 if (ret < 0)
1859 dev_err(wm831x->dev, "Failed to add backlight: %d\n",
1860 ret);
1861 }
1862
Mark Brown6704e512009-07-27 14:45:56 +01001863 wm831x_otp_init(wm831x);
1864
Mark Brownd2bedfe2009-07-27 14:45:52 +01001865 if (pdata && pdata->post_init) {
1866 ret = pdata->post_init(wm831x);
1867 if (ret != 0) {
1868 dev_err(wm831x->dev, "post_init() failed: %d\n", ret);
Mark Brown7d4d0a32009-07-27 14:45:53 +01001869 goto err_irq;
Mark Brownd2bedfe2009-07-27 14:45:52 +01001870 }
1871 }
1872
1873 return 0;
1874
Mark Brown7d4d0a32009-07-27 14:45:53 +01001875err_irq:
1876 wm831x_irq_exit(wm831x);
Mark Brown130a7032012-01-30 20:08:06 +00001877err:
Mark Brownd2bedfe2009-07-27 14:45:52 +01001878 mfd_remove_devices(wm831x->dev);
Mark Brownd2bedfe2009-07-27 14:45:52 +01001879 return ret;
1880}
1881
Mark Browne5b48682010-10-19 23:57:56 +02001882void wm831x_device_exit(struct wm831x *wm831x)
Mark Brownd2bedfe2009-07-27 14:45:52 +01001883{
Mark Brown6704e512009-07-27 14:45:56 +01001884 wm831x_otp_exit(wm831x);
Mark Brownd2bedfe2009-07-27 14:45:52 +01001885 mfd_remove_devices(wm831x->dev);
Mark Browncd997582012-05-14 23:14:24 +02001886 free_irq(wm831x_irq(wm831x, WM831X_IRQ_AUXADC_DATA), wm831x);
Mark Brown7d4d0a32009-07-27 14:45:53 +01001887 wm831x_irq_exit(wm831x);
Mark Brownd2bedfe2009-07-27 14:45:52 +01001888}
1889
Mark Browne5b48682010-10-19 23:57:56 +02001890int wm831x_device_suspend(struct wm831x *wm831x)
Mark Brownb03b4d7c2010-04-08 10:02:39 +02001891{
1892 int reg, mask;
1893
1894 /* If the charger IRQs are a wake source then make sure we ack
1895 * them even if they're not actively being used (eg, no power
1896 * driver or no IRQ line wired up) then acknowledge the
1897 * interrupts otherwise suspend won't last very long.
1898 */
1899 if (wm831x->charger_irq_wake) {
1900 reg = wm831x_reg_read(wm831x, WM831X_INTERRUPT_STATUS_2_MASK);
1901
1902 mask = WM831X_CHG_BATT_HOT_EINT |
1903 WM831X_CHG_BATT_COLD_EINT |
1904 WM831X_CHG_BATT_FAIL_EINT |
1905 WM831X_CHG_OV_EINT | WM831X_CHG_END_EINT |
1906 WM831X_CHG_TO_EINT | WM831X_CHG_MODE_EINT |
1907 WM831X_CHG_START_EINT;
1908
1909 /* If any of the interrupts are masked read the statuses */
1910 if (reg & mask)
1911 reg = wm831x_reg_read(wm831x,
1912 WM831X_INTERRUPT_STATUS_2);
1913
1914 if (reg & mask) {
1915 dev_info(wm831x->dev,
1916 "Acknowledging masked charger IRQs: %x\n",
1917 reg & mask);
1918 wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_2,
1919 reg & mask);
1920 }
1921 }
1922
1923 return 0;
1924}
1925
Mark Brown523d9cf2011-09-15 18:54:53 +02001926void wm831x_device_shutdown(struct wm831x *wm831x)
1927{
1928 if (wm831x->soft_shutdown) {
1929 dev_info(wm831x->dev, "Initiating shutdown...\n");
1930 wm831x_set_bits(wm831x, WM831X_POWER_STATE, WM831X_CHIP_ON, 0);
1931 }
1932}
1933EXPORT_SYMBOL_GPL(wm831x_device_shutdown);
1934
Mark Browne5b48682010-10-19 23:57:56 +02001935MODULE_DESCRIPTION("Core support for the WM831X AudioPlus PMIC");
Mark Brownd2bedfe2009-07-27 14:45:52 +01001936MODULE_LICENSE("GPL");
1937MODULE_AUTHOR("Mark Brown");