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David Howells0bc42d72010-10-27 17:28:41 +01001#
2# MN10300 CPU cache options
3#
4
5choice
6 prompt "CPU Caching mode"
7 default MN10300_CACHE_WBACK
8 help
9 This option determines the caching mode for the kernel.
10
11 Write-Back caching mode involves the all reads and writes causing
12 the affected cacheline to be read into the cache first before being
13 operated upon. Memory is not then updated by a write until the cache
14 is filled and a cacheline needs to be displaced from the cache to
15 make room. Only at that point is it written back.
16
17 Write-Through caching only fetches cachelines from memory on a
18 read. Writes always get written directly to memory. If the affected
19 cacheline is also in cache, it will be updated too.
20
21 The final option is to turn of caching entirely.
22
23config MN10300_CACHE_WBACK
24 bool "Write-Back"
25
26config MN10300_CACHE_WTHRU
27 bool "Write-Through"
28
29config MN10300_CACHE_DISABLED
30 bool "Disabled"
31
32endchoice
David Howells344af922010-10-27 17:28:42 +010033
34config MN10300_CACHE_ENABLED
35 def_bool y if !MN10300_CACHE_DISABLED
David Howells518d4bb2010-10-27 17:28:43 +010036
37
38choice
39 prompt "CPU cache flush/invalidate method"
40 default MN10300_CACHE_MANAGE_BY_TAG
41 depends on MN10300_CACHE_ENABLED
42 help
43 This determines the method by which CPU cache flushing and
44 invalidation is performed.
45
46config MN10300_CACHE_MANAGE_BY_TAG
47 bool "Use the cache tag registers directly"
48
49endchoice
50
51config MN10300_CACHE_INV_BY_TAG
52 def_bool y if MN10300_CACHE_MANAGE_BY_TAG && MN10300_CACHE_ENABLED
53
54config MN10300_CACHE_FLUSH_BY_TAG
55 def_bool y if MN10300_CACHE_MANAGE_BY_TAG && MN10300_CACHE_WBACK