Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015 Cavium, Inc. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms of version 2 of the GNU General Public License |
| 6 | * as published by the Free Software Foundation. |
| 7 | */ |
| 8 | |
| 9 | #ifndef NICVF_QUEUES_H |
| 10 | #define NICVF_QUEUES_H |
| 11 | |
| 12 | #include <linux/netdevice.h> |
| 13 | #include "q_struct.h" |
| 14 | |
| 15 | #define MAX_QUEUE_SET 128 |
| 16 | #define MAX_RCV_QUEUES_PER_QS 8 |
| 17 | #define MAX_RCV_BUF_DESC_RINGS_PER_QS 2 |
| 18 | #define MAX_SND_QUEUES_PER_QS 8 |
| 19 | #define MAX_CMP_QUEUES_PER_QS 8 |
| 20 | |
| 21 | /* VF's queue interrupt ranges */ |
| 22 | #define NICVF_INTR_ID_CQ 0 |
| 23 | #define NICVF_INTR_ID_SQ 8 |
| 24 | #define NICVF_INTR_ID_RBDR 16 |
| 25 | #define NICVF_INTR_ID_MISC 18 |
| 26 | #define NICVF_INTR_ID_QS_ERR 19 |
| 27 | |
| 28 | #define for_each_cq_irq(irq) \ |
| 29 | for (irq = NICVF_INTR_ID_CQ; irq < NICVF_INTR_ID_SQ; irq++) |
| 30 | #define for_each_sq_irq(irq) \ |
| 31 | for (irq = NICVF_INTR_ID_SQ; irq < NICVF_INTR_ID_RBDR; irq++) |
| 32 | #define for_each_rbdr_irq(irq) \ |
| 33 | for (irq = NICVF_INTR_ID_RBDR; irq < NICVF_INTR_ID_MISC; irq++) |
| 34 | |
| 35 | #define RBDR_SIZE0 0ULL /* 8K entries */ |
| 36 | #define RBDR_SIZE1 1ULL /* 16K entries */ |
| 37 | #define RBDR_SIZE2 2ULL /* 32K entries */ |
| 38 | #define RBDR_SIZE3 3ULL /* 64K entries */ |
| 39 | #define RBDR_SIZE4 4ULL /* 126K entries */ |
| 40 | #define RBDR_SIZE5 5ULL /* 256K entries */ |
| 41 | #define RBDR_SIZE6 6ULL /* 512K entries */ |
| 42 | |
| 43 | #define SND_QUEUE_SIZE0 0ULL /* 1K entries */ |
| 44 | #define SND_QUEUE_SIZE1 1ULL /* 2K entries */ |
| 45 | #define SND_QUEUE_SIZE2 2ULL /* 4K entries */ |
| 46 | #define SND_QUEUE_SIZE3 3ULL /* 8K entries */ |
| 47 | #define SND_QUEUE_SIZE4 4ULL /* 16K entries */ |
| 48 | #define SND_QUEUE_SIZE5 5ULL /* 32K entries */ |
| 49 | #define SND_QUEUE_SIZE6 6ULL /* 64K entries */ |
| 50 | |
| 51 | #define CMP_QUEUE_SIZE0 0ULL /* 1K entries */ |
| 52 | #define CMP_QUEUE_SIZE1 1ULL /* 2K entries */ |
| 53 | #define CMP_QUEUE_SIZE2 2ULL /* 4K entries */ |
| 54 | #define CMP_QUEUE_SIZE3 3ULL /* 8K entries */ |
| 55 | #define CMP_QUEUE_SIZE4 4ULL /* 16K entries */ |
| 56 | #define CMP_QUEUE_SIZE5 5ULL /* 32K entries */ |
| 57 | #define CMP_QUEUE_SIZE6 6ULL /* 64K entries */ |
| 58 | |
| 59 | /* Default queue count per QS, its lengths and threshold values */ |
| 60 | #define RBDR_CNT 1 |
| 61 | #define RCV_QUEUE_CNT 8 |
| 62 | #define SND_QUEUE_CNT 8 |
| 63 | #define CMP_QUEUE_CNT 8 /* Max of RCV and SND qcount */ |
| 64 | |
Sunil Goutham | 32c1b96 | 2015-07-29 16:49:38 +0300 | [diff] [blame] | 65 | #define SND_QSIZE SND_QUEUE_SIZE2 |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 66 | #define SND_QUEUE_LEN (1ULL << (SND_QSIZE + 10)) |
| 67 | #define MAX_SND_QUEUE_LEN (1ULL << (SND_QUEUE_SIZE6 + 10)) |
| 68 | #define SND_QUEUE_THRESH 2ULL |
| 69 | #define MIN_SQ_DESC_PER_PKT_XMIT 2 |
| 70 | /* Since timestamp not enabled, otherwise 2 */ |
| 71 | #define MAX_CQE_PER_PKT_XMIT 1 |
| 72 | |
Sunil Goutham | 32c1b96 | 2015-07-29 16:49:38 +0300 | [diff] [blame] | 73 | /* Keep CQ and SQ sizes same, if timestamping |
| 74 | * is enabled this equation will change. |
| 75 | */ |
| 76 | #define CMP_QSIZE CMP_QUEUE_SIZE2 |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 77 | #define CMP_QUEUE_LEN (1ULL << (CMP_QSIZE + 10)) |
| 78 | #define CMP_QUEUE_CQE_THRESH 0 |
Sunil Goutham | 006394a | 2015-12-02 15:36:15 +0530 | [diff] [blame] | 79 | #define CMP_QUEUE_TIMER_THRESH 80 /* ~2usec */ |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 80 | |
| 81 | #define RBDR_SIZE RBDR_SIZE0 |
| 82 | #define RCV_BUF_COUNT (1ULL << (RBDR_SIZE + 13)) |
| 83 | #define MAX_RCV_BUF_COUNT (1ULL << (RBDR_SIZE6 + 13)) |
| 84 | #define RBDR_THRESH (RCV_BUF_COUNT / 2) |
| 85 | #define DMA_BUFFER_LEN 2048 /* In multiples of 128bytes */ |
| 86 | #define RCV_FRAG_LEN (SKB_DATA_ALIGN(DMA_BUFFER_LEN + NET_SKB_PAD) + \ |
| 87 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + \ |
| 88 | (NICVF_RCV_BUF_ALIGN_BYTES * 2)) |
| 89 | #define RCV_DATA_OFFSET NICVF_RCV_BUF_ALIGN_BYTES |
| 90 | |
| 91 | #define MAX_CQES_FOR_TX ((SND_QUEUE_LEN / MIN_SQ_DESC_PER_PKT_XMIT) * \ |
| 92 | MAX_CQE_PER_PKT_XMIT) |
Sunil Goutham | 32c1b96 | 2015-07-29 16:49:38 +0300 | [diff] [blame] | 93 | /* Calculate number of CQEs to reserve for all SQEs. |
| 94 | * Its 1/256th level of CQ size. |
| 95 | * '+ 1' to account for pipelining |
| 96 | */ |
| 97 | #define RQ_CQ_DROP ((256 / (CMP_QUEUE_LEN / \ |
| 98 | (CMP_QUEUE_LEN - MAX_CQES_FOR_TX))) + 1) |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 99 | |
| 100 | /* Descriptor size in bytes */ |
| 101 | #define SND_QUEUE_DESC_SIZE 16 |
| 102 | #define CMP_QUEUE_DESC_SIZE 512 |
| 103 | |
| 104 | /* Buffer / descriptor alignments */ |
| 105 | #define NICVF_RCV_BUF_ALIGN 7 |
| 106 | #define NICVF_RCV_BUF_ALIGN_BYTES (1ULL << NICVF_RCV_BUF_ALIGN) |
| 107 | #define NICVF_CQ_BASE_ALIGN_BYTES 512 /* 9 bits */ |
| 108 | #define NICVF_SQ_BASE_ALIGN_BYTES 128 /* 7 bits */ |
| 109 | |
| 110 | #define NICVF_ALIGNED_ADDR(ADDR, ALIGN_BYTES) ALIGN(ADDR, ALIGN_BYTES) |
| 111 | #define NICVF_ADDR_ALIGN_LEN(ADDR, BYTES)\ |
| 112 | (NICVF_ALIGNED_ADDR(ADDR, BYTES) - BYTES) |
| 113 | #define NICVF_RCV_BUF_ALIGN_LEN(X)\ |
| 114 | (NICVF_ALIGNED_ADDR(X, NICVF_RCV_BUF_ALIGN_BYTES) - X) |
| 115 | |
| 116 | /* Queue enable/disable */ |
| 117 | #define NICVF_SQ_EN BIT_ULL(19) |
| 118 | |
| 119 | /* Queue reset */ |
| 120 | #define NICVF_CQ_RESET BIT_ULL(41) |
| 121 | #define NICVF_SQ_RESET BIT_ULL(17) |
| 122 | #define NICVF_RBDR_RESET BIT_ULL(43) |
| 123 | |
| 124 | enum CQ_RX_ERRLVL_E { |
| 125 | CQ_ERRLVL_MAC, |
| 126 | CQ_ERRLVL_L2, |
| 127 | CQ_ERRLVL_L3, |
| 128 | CQ_ERRLVL_L4, |
| 129 | }; |
| 130 | |
| 131 | enum CQ_RX_ERROP_E { |
| 132 | CQ_RX_ERROP_RE_NONE = 0x0, |
| 133 | CQ_RX_ERROP_RE_PARTIAL = 0x1, |
| 134 | CQ_RX_ERROP_RE_JABBER = 0x2, |
| 135 | CQ_RX_ERROP_RE_FCS = 0x7, |
| 136 | CQ_RX_ERROP_RE_TERMINATE = 0x9, |
| 137 | CQ_RX_ERROP_RE_RX_CTL = 0xb, |
| 138 | CQ_RX_ERROP_PREL2_ERR = 0x1f, |
| 139 | CQ_RX_ERROP_L2_FRAGMENT = 0x20, |
| 140 | CQ_RX_ERROP_L2_OVERRUN = 0x21, |
| 141 | CQ_RX_ERROP_L2_PFCS = 0x22, |
| 142 | CQ_RX_ERROP_L2_PUNY = 0x23, |
| 143 | CQ_RX_ERROP_L2_MAL = 0x24, |
| 144 | CQ_RX_ERROP_L2_OVERSIZE = 0x25, |
| 145 | CQ_RX_ERROP_L2_UNDERSIZE = 0x26, |
| 146 | CQ_RX_ERROP_L2_LENMISM = 0x27, |
| 147 | CQ_RX_ERROP_L2_PCLP = 0x28, |
| 148 | CQ_RX_ERROP_IP_NOT = 0x41, |
| 149 | CQ_RX_ERROP_IP_CSUM_ERR = 0x42, |
| 150 | CQ_RX_ERROP_IP_MAL = 0x43, |
| 151 | CQ_RX_ERROP_IP_MALD = 0x44, |
| 152 | CQ_RX_ERROP_IP_HOP = 0x45, |
| 153 | CQ_RX_ERROP_L3_ICRC = 0x46, |
| 154 | CQ_RX_ERROP_L3_PCLP = 0x47, |
| 155 | CQ_RX_ERROP_L4_MAL = 0x61, |
| 156 | CQ_RX_ERROP_L4_CHK = 0x62, |
| 157 | CQ_RX_ERROP_UDP_LEN = 0x63, |
| 158 | CQ_RX_ERROP_L4_PORT = 0x64, |
| 159 | CQ_RX_ERROP_TCP_FLAG = 0x65, |
| 160 | CQ_RX_ERROP_TCP_OFFSET = 0x66, |
| 161 | CQ_RX_ERROP_L4_PCLP = 0x67, |
| 162 | CQ_RX_ERROP_RBDR_TRUNC = 0x70, |
| 163 | }; |
| 164 | |
| 165 | enum CQ_TX_ERROP_E { |
| 166 | CQ_TX_ERROP_GOOD = 0x0, |
| 167 | CQ_TX_ERROP_DESC_FAULT = 0x10, |
| 168 | CQ_TX_ERROP_HDR_CONS_ERR = 0x11, |
| 169 | CQ_TX_ERROP_SUBDC_ERR = 0x12, |
| 170 | CQ_TX_ERROP_IMM_SIZE_OFLOW = 0x80, |
| 171 | CQ_TX_ERROP_DATA_SEQUENCE_ERR = 0x81, |
| 172 | CQ_TX_ERROP_MEM_SEQUENCE_ERR = 0x82, |
| 173 | CQ_TX_ERROP_LOCK_VIOL = 0x83, |
| 174 | CQ_TX_ERROP_DATA_FAULT = 0x84, |
| 175 | CQ_TX_ERROP_TSTMP_CONFLICT = 0x85, |
| 176 | CQ_TX_ERROP_TSTMP_TIMEOUT = 0x86, |
| 177 | CQ_TX_ERROP_MEM_FAULT = 0x87, |
| 178 | CQ_TX_ERROP_CK_OVERLAP = 0x88, |
| 179 | CQ_TX_ERROP_CK_OFLOW = 0x89, |
| 180 | CQ_TX_ERROP_ENUM_LAST = 0x8a, |
| 181 | }; |
| 182 | |
| 183 | struct cmp_queue_stats { |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 184 | struct tx_stats { |
| 185 | u64 good; |
| 186 | u64 desc_fault; |
| 187 | u64 hdr_cons_err; |
| 188 | u64 subdesc_err; |
| 189 | u64 imm_size_oflow; |
| 190 | u64 data_seq_err; |
| 191 | u64 mem_seq_err; |
| 192 | u64 lock_viol; |
| 193 | u64 data_fault; |
| 194 | u64 tstmp_conflict; |
| 195 | u64 tstmp_timeout; |
| 196 | u64 mem_fault; |
| 197 | u64 csum_overlap; |
| 198 | u64 csum_overflow; |
| 199 | } tx; |
| 200 | } ____cacheline_aligned_in_smp; |
| 201 | |
| 202 | enum RQ_SQ_STATS { |
| 203 | RQ_SQ_STATS_OCTS, |
| 204 | RQ_SQ_STATS_PKTS, |
| 205 | }; |
| 206 | |
| 207 | struct rx_tx_queue_stats { |
| 208 | u64 bytes; |
| 209 | u64 pkts; |
| 210 | } ____cacheline_aligned_in_smp; |
| 211 | |
| 212 | struct q_desc_mem { |
| 213 | dma_addr_t dma; |
| 214 | u64 size; |
| 215 | u16 q_len; |
| 216 | dma_addr_t phys_base; |
| 217 | void *base; |
| 218 | void *unalign_base; |
| 219 | }; |
| 220 | |
| 221 | struct rbdr { |
| 222 | bool enable; |
| 223 | u32 dma_size; |
| 224 | u32 frag_len; |
| 225 | u32 thresh; /* Threshold level for interrupt */ |
| 226 | void *desc; |
| 227 | u32 head; |
| 228 | u32 tail; |
| 229 | struct q_desc_mem dmem; |
| 230 | } ____cacheline_aligned_in_smp; |
| 231 | |
| 232 | struct rcv_queue { |
| 233 | bool enable; |
| 234 | struct rbdr *rbdr_start; |
| 235 | struct rbdr *rbdr_cont; |
| 236 | bool en_tcp_reassembly; |
| 237 | u8 cq_qs; /* CQ's QS to which this RQ is assigned */ |
| 238 | u8 cq_idx; /* CQ index (0 to 7) in the QS */ |
| 239 | u8 cont_rbdr_qs; /* Continue buffer ptrs - QS num */ |
| 240 | u8 cont_qs_rbdr_idx; /* RBDR idx in the cont QS */ |
| 241 | u8 start_rbdr_qs; /* First buffer ptrs - QS num */ |
| 242 | u8 start_qs_rbdr_idx; /* RBDR idx in the above QS */ |
| 243 | u8 caching; |
| 244 | struct rx_tx_queue_stats stats; |
| 245 | } ____cacheline_aligned_in_smp; |
| 246 | |
| 247 | struct cmp_queue { |
| 248 | bool enable; |
| 249 | u16 thresh; |
| 250 | spinlock_t lock; /* lock to serialize processing CQEs */ |
| 251 | void *desc; |
| 252 | struct q_desc_mem dmem; |
| 253 | struct cmp_queue_stats stats; |
Sunil Goutham | 39ad6ee | 2015-08-30 12:29:14 +0300 | [diff] [blame] | 254 | int irq; |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 255 | } ____cacheline_aligned_in_smp; |
| 256 | |
| 257 | struct snd_queue { |
| 258 | bool enable; |
| 259 | u8 cq_qs; /* CQ's QS to which this SQ is pointing */ |
| 260 | u8 cq_idx; /* CQ index (0 to 7) in the above QS */ |
| 261 | u16 thresh; |
| 262 | atomic_t free_cnt; |
| 263 | u32 head; |
| 264 | u32 tail; |
| 265 | u64 *skbuff; |
| 266 | void *desc; |
| 267 | |
| 268 | #define TSO_HEADER_SIZE 128 |
| 269 | /* For TSO segment's header */ |
| 270 | char *tso_hdrs; |
| 271 | dma_addr_t tso_hdrs_phys; |
| 272 | |
| 273 | cpumask_t affinity_mask; |
| 274 | struct q_desc_mem dmem; |
| 275 | struct rx_tx_queue_stats stats; |
| 276 | } ____cacheline_aligned_in_smp; |
| 277 | |
| 278 | struct queue_set { |
| 279 | bool enable; |
| 280 | bool be_en; |
| 281 | u8 vnic_id; |
| 282 | u8 rq_cnt; |
| 283 | u8 cq_cnt; |
| 284 | u64 cq_len; |
| 285 | u8 sq_cnt; |
| 286 | u64 sq_len; |
| 287 | u8 rbdr_cnt; |
| 288 | u64 rbdr_len; |
| 289 | struct rcv_queue rq[MAX_RCV_QUEUES_PER_QS]; |
| 290 | struct cmp_queue cq[MAX_CMP_QUEUES_PER_QS]; |
| 291 | struct snd_queue sq[MAX_SND_QUEUES_PER_QS]; |
| 292 | struct rbdr rbdr[MAX_RCV_BUF_DESC_RINGS_PER_QS]; |
| 293 | } ____cacheline_aligned_in_smp; |
| 294 | |
| 295 | #define GET_RBDR_DESC(RING, idx)\ |
| 296 | (&(((struct rbdr_entry_t *)((RING)->desc))[idx])) |
| 297 | #define GET_SQ_DESC(RING, idx)\ |
| 298 | (&(((struct sq_hdr_subdesc *)((RING)->desc))[idx])) |
| 299 | #define GET_CQ_DESC(RING, idx)\ |
| 300 | (&(((union cq_desc_t *)((RING)->desc))[idx])) |
| 301 | |
| 302 | /* CQ status bits */ |
| 303 | #define CQ_WR_FULL BIT(26) |
| 304 | #define CQ_WR_DISABLE BIT(25) |
| 305 | #define CQ_WR_FAULT BIT(24) |
| 306 | #define CQ_CQE_COUNT (0xFFFF << 0) |
| 307 | |
| 308 | #define CQ_ERR_MASK (CQ_WR_FULL | CQ_WR_DISABLE | CQ_WR_FAULT) |
| 309 | |
Sunil Goutham | aa2e259 | 2015-08-30 12:29:13 +0300 | [diff] [blame] | 310 | void nicvf_config_vlan_stripping(struct nicvf *nic, |
| 311 | netdev_features_t features); |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 312 | int nicvf_set_qset_resources(struct nicvf *nic); |
| 313 | int nicvf_config_data_transfer(struct nicvf *nic, bool enable); |
| 314 | void nicvf_qset_config(struct nicvf *nic, bool enable); |
| 315 | void nicvf_cmp_queue_config(struct nicvf *nic, struct queue_set *qs, |
| 316 | int qidx, bool enable); |
| 317 | |
| 318 | void nicvf_sq_enable(struct nicvf *nic, struct snd_queue *sq, int qidx); |
| 319 | void nicvf_sq_disable(struct nicvf *nic, int qidx); |
| 320 | void nicvf_put_sq_desc(struct snd_queue *sq, int desc_cnt); |
| 321 | void nicvf_sq_free_used_descs(struct net_device *netdev, |
| 322 | struct snd_queue *sq, int qidx); |
| 323 | int nicvf_sq_append_skb(struct nicvf *nic, struct sk_buff *skb); |
| 324 | |
| 325 | struct sk_buff *nicvf_get_rcv_skb(struct nicvf *nic, struct cqe_rx_t *cqe_rx); |
| 326 | void nicvf_rbdr_task(unsigned long data); |
| 327 | void nicvf_rbdr_work(struct work_struct *work); |
| 328 | |
| 329 | void nicvf_enable_intr(struct nicvf *nic, int int_type, int q_idx); |
| 330 | void nicvf_disable_intr(struct nicvf *nic, int int_type, int q_idx); |
| 331 | void nicvf_clear_intr(struct nicvf *nic, int int_type, int q_idx); |
| 332 | int nicvf_is_intr_enabled(struct nicvf *nic, int int_type, int q_idx); |
| 333 | |
| 334 | /* Register access APIs */ |
| 335 | void nicvf_reg_write(struct nicvf *nic, u64 offset, u64 val); |
| 336 | u64 nicvf_reg_read(struct nicvf *nic, u64 offset); |
| 337 | void nicvf_qset_reg_write(struct nicvf *nic, u64 offset, u64 val); |
| 338 | u64 nicvf_qset_reg_read(struct nicvf *nic, u64 offset); |
| 339 | void nicvf_queue_reg_write(struct nicvf *nic, u64 offset, |
| 340 | u64 qidx, u64 val); |
| 341 | u64 nicvf_queue_reg_read(struct nicvf *nic, |
| 342 | u64 offset, u64 qidx); |
| 343 | |
| 344 | /* Stats */ |
| 345 | void nicvf_update_rq_stats(struct nicvf *nic, int rq_idx); |
| 346 | void nicvf_update_sq_stats(struct nicvf *nic, int sq_idx); |
| 347 | int nicvf_check_cqe_rx_errs(struct nicvf *nic, |
| 348 | struct cmp_queue *cq, struct cqe_rx_t *cqe_rx); |
| 349 | int nicvf_check_cqe_tx_errs(struct nicvf *nic, |
| 350 | struct cmp_queue *cq, struct cqe_send_t *cqe_tx); |
| 351 | #endif /* NICVF_QUEUES_H */ |