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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Manuel Lauss0c694de2008-12-21 09:26:23 +01002 * Copyright (C) 2008 Manuel Lauss <mano@roarinelk.homelinux.net>
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 *
Manuel Lauss0c694de2008-12-21 09:26:23 +01004 * Previous incarnations were:
Sergei Shtylyov01675092008-03-24 23:15:50 +03005 * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -07006 * Copied and modified Carsten Langgaard's time.c
7 *
8 * Carsten Langgaard, carstenl@mips.com
9 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
10 *
11 * ########################################################################
12 *
13 * This program is free software; you can distribute it and/or modify it
14 * under the terms of the GNU General Public License (Version 2) as
15 * published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 * for more details.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
25 *
26 * ########################################################################
27 *
Manuel Lauss0c694de2008-12-21 09:26:23 +010028 * Clocksource/event using the 32.768kHz-clocked Counter1 ('RTC' in the
29 * databooks). Firmware/Board init code must enable the counters in the
30 * counter control register, otherwise the CP0 counter clocksource/event
31 * will be installed instead (and use of 'wait' instruction is prohibited).
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 */
33
Manuel Lauss0c694de2008-12-21 09:26:23 +010034#include <linux/clockchips.h>
35#include <linux/clocksource.h>
36#include <linux/interrupt.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070037#include <linux/spinlock.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070038
Manuel Lauss2882b0c2009-08-22 18:09:27 +020039#include <asm/processor.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070040#include <asm/time.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070041#include <asm/mach-au1x00/au1000.h>
42
Manuel Lauss0c694de2008-12-21 09:26:23 +010043/* 32kHz clock enabled and detected */
44#define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)
45
Manuel Laussad058e92009-04-22 08:01:48 +020046static cycle_t au1x_counter1_read(struct clocksource *cs)
Manuel Lauss0c694de2008-12-21 09:26:23 +010047{
48 return au_readl(SYS_RTCREAD);
49}
50
51static struct clocksource au1x_counter1_clocksource = {
52 .name = "alchemy-counter1",
53 .read = au1x_counter1_read,
54 .mask = CLOCKSOURCE_MASK(32),
55 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
56 .rating = 100,
57};
58
59static int au1x_rtcmatch2_set_next_event(unsigned long delta,
60 struct clock_event_device *cd)
61{
62 delta += au_readl(SYS_RTCREAD);
63 /* wait for register access */
64 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M21)
65 ;
66 au_writel(delta, SYS_RTCMATCH2);
67 au_sync();
68
69 return 0;
70}
71
72static void au1x_rtcmatch2_set_mode(enum clock_event_mode mode,
73 struct clock_event_device *cd)
74{
75}
76
77static irqreturn_t au1x_rtcmatch2_irq(int irq, void *dev_id)
78{
79 struct clock_event_device *cd = dev_id;
80 cd->event_handler(cd);
81 return IRQ_HANDLED;
82}
83
84static struct clock_event_device au1x_rtcmatch2_clockdev = {
85 .name = "rtcmatch2",
86 .features = CLOCK_EVT_FEAT_ONESHOT,
87 .rating = 100,
88 .irq = AU1000_RTC_MATCH2_INT,
89 .set_next_event = au1x_rtcmatch2_set_next_event,
90 .set_mode = au1x_rtcmatch2_set_mode,
Rusty Russell51c870a2009-09-24 09:34:35 -060091 .cpumask = cpu_all_mask,
Manuel Lauss0c694de2008-12-21 09:26:23 +010092};
93
94static struct irqaction au1x_rtcmatch2_irqaction = {
95 .handler = au1x_rtcmatch2_irq,
96 .flags = IRQF_DISABLED | IRQF_TIMER,
97 .name = "timer",
98 .dev_id = &au1x_rtcmatch2_clockdev,
99};
100
Ralf Baechlebc2f2a22007-10-26 12:58:02 +0100101void __init plat_time_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102{
Manuel Lauss0c694de2008-12-21 09:26:23 +0100103 struct clock_event_device *cd = &au1x_rtcmatch2_clockdev;
104 unsigned long t;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105
Manuel Lauss0c694de2008-12-21 09:26:23 +0100106 /* Check if firmware (YAMON, ...) has enabled 32kHz and clock
107 * has been detected. If so install the rtcmatch2 clocksource,
108 * otherwise don't bother. Note that both bits being set is by
109 * no means a definite guarantee that the counters actually work
110 * (the 32S bit seems to be stuck set to 1 once a single clock-
111 * edge is detected, hence the timeouts).
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112 */
Manuel Lauss0c694de2008-12-21 09:26:23 +0100113 if (CNTR_OK != (au_readl(SYS_COUNTER_CNTRL) & CNTR_OK))
114 goto cntr_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700115
Manuel Lauss0c694de2008-12-21 09:26:23 +0100116 /*
117 * setup counter 1 (RTC) to tick at full speed
118 */
119 t = 0xffffff;
Roel Kluin4b0d3f52009-01-31 12:23:34 +0100120 while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S) && --t)
Manuel Lauss0c694de2008-12-21 09:26:23 +0100121 asm volatile ("nop");
122 if (!t)
123 goto cntr_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700124
Manuel Lauss0c694de2008-12-21 09:26:23 +0100125 au_writel(0, SYS_RTCTRIM); /* 32.768 kHz */
126 au_sync();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700127
Manuel Lauss0c694de2008-12-21 09:26:23 +0100128 t = 0xffffff;
Roel Kluin4b0d3f52009-01-31 12:23:34 +0100129 while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && --t)
Manuel Lauss0c694de2008-12-21 09:26:23 +0100130 asm volatile ("nop");
131 if (!t)
132 goto cntr_err;
133 au_writel(0, SYS_RTCWRITE);
134 au_sync();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135
Manuel Lauss0c694de2008-12-21 09:26:23 +0100136 t = 0xffffff;
Roel Kluin4b0d3f52009-01-31 12:23:34 +0100137 while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && --t)
Manuel Lauss0c694de2008-12-21 09:26:23 +0100138 asm volatile ("nop");
139 if (!t)
140 goto cntr_err;
141
142 /* register counter1 clocksource and event device */
143 clocksource_set_clock(&au1x_counter1_clocksource, 32768);
144 clocksource_register(&au1x_counter1_clocksource);
145
146 cd->shift = 32;
147 cd->mult = div_sc(32768, NSEC_PER_SEC, cd->shift);
148 cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd);
149 cd->min_delta_ns = clockevent_delta2ns(8, cd); /* ~0.25ms */
150 clockevents_register_device(cd);
151 setup_irq(AU1000_RTC_MATCH2_INT, &au1x_rtcmatch2_irqaction);
152
153 printk(KERN_INFO "Alchemy clocksource installed\n");
154
Manuel Lauss0c694de2008-12-21 09:26:23 +0100155 return;
156
157cntr_err:
Manuel Lauss2882b0c2009-08-22 18:09:27 +0200158 /*
159 * MIPS kernel assigns 'au1k_wait' to 'cpu_wait' before this
160 * function is called. Because the Alchemy counters are unusable
161 * the C0 timekeeping code is installed and use of the 'wait'
162 * instruction must be prohibited, which is done most easily by
163 * assigning NULL to cpu_wait.
164 */
165 cpu_wait = NULL;
Manuel Lauss0c694de2008-12-21 09:26:23 +0100166 r4k_clockevent_init();
167 init_r4k_clocksource();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168}