blob: 19e1bdd674165739b66dab05cb04e7527f174b79 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001#ifndef __UM_CACHE_H
2#define __UM_CACHE_H
3
Linus Torvalds1da177e2005-04-16 15:20:36 -07004
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -08005#if defined(CONFIG_UML_X86) && !defined(CONFIG_64BIT)
6# define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT)
7#elif defined(CONFIG_UML_X86) /* 64-bit */
8# define L1_CACHE_SHIFT 6 /* Should be 7 on Intel */
9#else
10/* XXX: this was taken from x86, now it's completely random. Luckily only
11 * affects SMP padding. */
12# define L1_CACHE_SHIFT 5
13#endif
14
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080015#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
Linus Torvalds1da177e2005-04-16 15:20:36 -070016
17#endif