Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 1 | /* |
| 2 | * drivers/ata/sata_fsl.c |
| 3 | * |
| 4 | * Freescale 3.0Gbps SATA device driver |
| 5 | * |
| 6 | * Author: Ashish Kalra <ashish.kalra@freescale.com> |
| 7 | * Li Yang <leoli@freescale.com> |
| 8 | * |
| 9 | * Copyright (c) 2006-2007 Freescale Semiconductor, Inc. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify it |
| 12 | * under the terms of the GNU General Public License as published by the |
| 13 | * Free Software Foundation; either version 2 of the License, or (at your |
| 14 | * option) any later version. |
| 15 | * |
| 16 | */ |
| 17 | |
| 18 | #include <linux/kernel.h> |
| 19 | #include <linux/module.h> |
| 20 | #include <linux/platform_device.h> |
| 21 | |
| 22 | #include <scsi/scsi_host.h> |
| 23 | #include <scsi/scsi_cmnd.h> |
| 24 | #include <linux/libata.h> |
| 25 | #include <asm/io.h> |
| 26 | #include <linux/of_platform.h> |
| 27 | |
| 28 | /* Controller information */ |
| 29 | enum { |
| 30 | SATA_FSL_QUEUE_DEPTH = 16, |
| 31 | SATA_FSL_MAX_PRD = 63, |
| 32 | SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1, |
| 33 | SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */ |
| 34 | |
| 35 | SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
| 36 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | |
Li Yang | 1bf617b | 2007-10-31 19:27:53 +0800 | [diff] [blame] | 37 | ATA_FLAG_NCQ), |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 38 | |
| 39 | SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH, |
| 40 | SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */ |
| 41 | SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE), |
| 42 | |
| 43 | /* |
| 44 | * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and |
| 45 | * chained indirect PRDEs upto a max count of 63. |
| 46 | * We are allocating an array of 63 PRDEs contigiously, but PRDE#15 will |
| 47 | * be setup as an indirect descriptor, pointing to it's next |
| 48 | * (contigious) PRDE. Though chained indirect PRDE arrays are |
| 49 | * supported,it will be more efficient to use a direct PRDT and |
| 50 | * a single chain/link to indirect PRDE array/PRDT. |
| 51 | */ |
| 52 | |
| 53 | SATA_FSL_CMD_DESC_CFIS_SZ = 32, |
| 54 | SATA_FSL_CMD_DESC_SFIS_SZ = 32, |
| 55 | SATA_FSL_CMD_DESC_ACMD_SZ = 16, |
| 56 | SATA_FSL_CMD_DESC_RSRVD = 16, |
| 57 | |
| 58 | SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ + |
| 59 | SATA_FSL_CMD_DESC_SFIS_SZ + |
| 60 | SATA_FSL_CMD_DESC_ACMD_SZ + |
| 61 | SATA_FSL_CMD_DESC_RSRVD + |
| 62 | SATA_FSL_MAX_PRD * 16), |
| 63 | |
| 64 | SATA_FSL_CMD_DESC_OFFSET_TO_PRDT = |
| 65 | (SATA_FSL_CMD_DESC_CFIS_SZ + |
| 66 | SATA_FSL_CMD_DESC_SFIS_SZ + |
| 67 | SATA_FSL_CMD_DESC_ACMD_SZ + |
| 68 | SATA_FSL_CMD_DESC_RSRVD), |
| 69 | |
| 70 | SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS), |
| 71 | SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE + |
| 72 | SATA_FSL_CMD_DESC_AR_SZ), |
| 73 | |
| 74 | /* |
| 75 | * MPC8315 has two SATA controllers, SATA1 & SATA2 |
| 76 | * (one port per controller) |
| 77 | * MPC837x has 2/4 controllers, one port per controller |
| 78 | */ |
| 79 | |
| 80 | SATA_FSL_MAX_PORTS = 1, |
| 81 | |
| 82 | SATA_FSL_IRQ_FLAG = IRQF_SHARED, |
| 83 | }; |
| 84 | |
| 85 | /* |
| 86 | * Host Controller command register set - per port |
| 87 | */ |
| 88 | enum { |
| 89 | CQ = 0, |
| 90 | CA = 8, |
| 91 | CC = 0x10, |
| 92 | CE = 0x18, |
| 93 | DE = 0x20, |
| 94 | CHBA = 0x24, |
| 95 | HSTATUS = 0x28, |
| 96 | HCONTROL = 0x2C, |
| 97 | CQPMP = 0x30, |
| 98 | SIGNATURE = 0x34, |
| 99 | ICC = 0x38, |
| 100 | |
| 101 | /* |
| 102 | * Host Status Register (HStatus) bitdefs |
| 103 | */ |
| 104 | ONLINE = (1 << 31), |
| 105 | GOING_OFFLINE = (1 << 30), |
| 106 | BIST_ERR = (1 << 29), |
| 107 | |
| 108 | FATAL_ERR_HC_MASTER_ERR = (1 << 18), |
| 109 | FATAL_ERR_PARITY_ERR_TX = (1 << 17), |
| 110 | FATAL_ERR_PARITY_ERR_RX = (1 << 16), |
| 111 | FATAL_ERR_DATA_UNDERRUN = (1 << 13), |
| 112 | FATAL_ERR_DATA_OVERRUN = (1 << 12), |
| 113 | FATAL_ERR_CRC_ERR_TX = (1 << 11), |
| 114 | FATAL_ERR_CRC_ERR_RX = (1 << 10), |
| 115 | FATAL_ERR_FIFO_OVRFL_TX = (1 << 9), |
| 116 | FATAL_ERR_FIFO_OVRFL_RX = (1 << 8), |
| 117 | |
| 118 | FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR | |
| 119 | FATAL_ERR_PARITY_ERR_TX | |
| 120 | FATAL_ERR_PARITY_ERR_RX | |
| 121 | FATAL_ERR_DATA_UNDERRUN | |
| 122 | FATAL_ERR_DATA_OVERRUN | |
| 123 | FATAL_ERR_CRC_ERR_TX | |
| 124 | FATAL_ERR_CRC_ERR_RX | |
| 125 | FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX, |
| 126 | |
| 127 | INT_ON_FATAL_ERR = (1 << 5), |
| 128 | INT_ON_PHYRDY_CHG = (1 << 4), |
| 129 | |
| 130 | INT_ON_SIGNATURE_UPDATE = (1 << 3), |
| 131 | INT_ON_SNOTIFY_UPDATE = (1 << 2), |
| 132 | INT_ON_SINGL_DEVICE_ERR = (1 << 1), |
| 133 | INT_ON_CMD_COMPLETE = 1, |
| 134 | |
| 135 | INT_ON_ERROR = INT_ON_FATAL_ERR | |
| 136 | INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR, |
| 137 | |
| 138 | /* |
| 139 | * Host Control Register (HControl) bitdefs |
| 140 | */ |
| 141 | HCONTROL_ONLINE_PHY_RST = (1 << 31), |
| 142 | HCONTROL_FORCE_OFFLINE = (1 << 30), |
| 143 | HCONTROL_PARITY_PROT_MOD = (1 << 14), |
| 144 | HCONTROL_DPATH_PARITY = (1 << 12), |
| 145 | HCONTROL_SNOOP_ENABLE = (1 << 10), |
| 146 | HCONTROL_PMP_ATTACHED = (1 << 9), |
| 147 | HCONTROL_COPYOUT_STATFIS = (1 << 8), |
| 148 | IE_ON_FATAL_ERR = (1 << 5), |
| 149 | IE_ON_PHYRDY_CHG = (1 << 4), |
| 150 | IE_ON_SIGNATURE_UPDATE = (1 << 3), |
| 151 | IE_ON_SNOTIFY_UPDATE = (1 << 2), |
| 152 | IE_ON_SINGL_DEVICE_ERR = (1 << 1), |
| 153 | IE_ON_CMD_COMPLETE = 1, |
| 154 | |
| 155 | DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG | |
| 156 | IE_ON_SIGNATURE_UPDATE | |
| 157 | IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE, |
| 158 | |
| 159 | EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31), |
| 160 | DATA_SNOOP_ENABLE = (1 << 22), |
| 161 | }; |
| 162 | |
| 163 | /* |
| 164 | * SATA Superset Registers |
| 165 | */ |
| 166 | enum { |
| 167 | SSTATUS = 0, |
| 168 | SERROR = 4, |
| 169 | SCONTROL = 8, |
| 170 | SNOTIFY = 0xC, |
| 171 | }; |
| 172 | |
| 173 | /* |
| 174 | * Control Status Register Set |
| 175 | */ |
| 176 | enum { |
| 177 | TRANSCFG = 0, |
| 178 | TRANSSTATUS = 4, |
| 179 | LINKCFG = 8, |
| 180 | LINKCFG1 = 0xC, |
| 181 | LINKCFG2 = 0x10, |
| 182 | LINKSTATUS = 0x14, |
| 183 | LINKSTATUS1 = 0x18, |
| 184 | PHYCTRLCFG = 0x1C, |
| 185 | COMMANDSTAT = 0x20, |
| 186 | }; |
| 187 | |
| 188 | /* PHY (link-layer) configuration control */ |
| 189 | enum { |
| 190 | PHY_BIST_ENABLE = 0x01, |
| 191 | }; |
| 192 | |
| 193 | /* |
| 194 | * Command Header Table entry, i.e, command slot |
| 195 | * 4 Dwords per command slot, command header size == 64 Dwords. |
| 196 | */ |
| 197 | struct cmdhdr_tbl_entry { |
| 198 | u32 cda; |
| 199 | u32 prde_fis_len; |
| 200 | u32 ttl; |
| 201 | u32 desc_info; |
| 202 | }; |
| 203 | |
| 204 | /* |
| 205 | * Description information bitdefs |
| 206 | */ |
| 207 | enum { |
| 208 | VENDOR_SPECIFIC_BIST = (1 << 10), |
| 209 | CMD_DESC_SNOOP_ENABLE = (1 << 9), |
| 210 | FPDMA_QUEUED_CMD = (1 << 8), |
| 211 | SRST_CMD = (1 << 7), |
| 212 | BIST = (1 << 6), |
| 213 | ATAPI_CMD = (1 << 5), |
| 214 | }; |
| 215 | |
| 216 | /* |
| 217 | * Command Descriptor |
| 218 | */ |
| 219 | struct command_desc { |
| 220 | u8 cfis[8 * 4]; |
| 221 | u8 sfis[8 * 4]; |
| 222 | u8 acmd[4 * 4]; |
| 223 | u8 fill[4 * 4]; |
| 224 | u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4]; |
| 225 | u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4]; |
| 226 | }; |
| 227 | |
| 228 | /* |
| 229 | * Physical region table descriptor(PRD) |
| 230 | */ |
| 231 | |
| 232 | struct prde { |
| 233 | u32 dba; |
| 234 | u8 fill[2 * 4]; |
| 235 | u32 ddc_and_ext; |
| 236 | }; |
| 237 | |
| 238 | /* |
| 239 | * ata_port private data |
| 240 | * This is our per-port instance data. |
| 241 | */ |
| 242 | struct sata_fsl_port_priv { |
| 243 | struct cmdhdr_tbl_entry *cmdslot; |
| 244 | dma_addr_t cmdslot_paddr; |
| 245 | struct command_desc *cmdentry; |
| 246 | dma_addr_t cmdentry_paddr; |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 247 | }; |
| 248 | |
| 249 | /* |
| 250 | * ata_port->host_set private data |
| 251 | */ |
| 252 | struct sata_fsl_host_priv { |
| 253 | void __iomem *hcr_base; |
| 254 | void __iomem *ssr_base; |
| 255 | void __iomem *csr_base; |
Li Yang | 79b3edc | 2007-10-31 19:27:55 +0800 | [diff] [blame] | 256 | int irq; |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 257 | }; |
| 258 | |
| 259 | static inline unsigned int sata_fsl_tag(unsigned int tag, |
Li Yang | 520d3a1 | 2007-10-31 19:28:01 +0800 | [diff] [blame] | 260 | void __iomem *hcr_base) |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 261 | { |
| 262 | /* We let libATA core do actual (queue) tag allocation */ |
| 263 | |
| 264 | /* all non NCQ/queued commands should have tag#0 */ |
| 265 | if (ata_tag_internal(tag)) { |
| 266 | DPRINTK("mapping internal cmds to tag#0\n"); |
| 267 | return 0; |
| 268 | } |
| 269 | |
| 270 | if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) { |
| 271 | DPRINTK("tag %d invalid : out of range\n", tag); |
| 272 | return 0; |
| 273 | } |
| 274 | |
| 275 | if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) { |
| 276 | DPRINTK("tag %d invalid : in use!!\n", tag); |
| 277 | return 0; |
| 278 | } |
| 279 | |
| 280 | return tag; |
| 281 | } |
| 282 | |
| 283 | static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp, |
| 284 | unsigned int tag, u32 desc_info, |
| 285 | u32 data_xfer_len, u8 num_prde, |
| 286 | u8 fis_len) |
| 287 | { |
| 288 | dma_addr_t cmd_descriptor_address; |
| 289 | |
| 290 | cmd_descriptor_address = pp->cmdentry_paddr + |
| 291 | tag * SATA_FSL_CMD_DESC_SIZE; |
| 292 | |
| 293 | /* NOTE: both data_xfer_len & fis_len are Dword counts */ |
| 294 | |
| 295 | pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address); |
| 296 | pp->cmdslot[tag].prde_fis_len = |
| 297 | cpu_to_le32((num_prde << 16) | (fis_len << 2)); |
| 298 | pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03); |
Li Yang | 520d3a1 | 2007-10-31 19:28:01 +0800 | [diff] [blame] | 299 | pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F)); |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 300 | |
| 301 | VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n", |
| 302 | pp->cmdslot[tag].cda, |
| 303 | pp->cmdslot[tag].prde_fis_len, |
| 304 | pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info); |
| 305 | |
| 306 | } |
| 307 | |
| 308 | static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc, |
Li Yang | 520d3a1 | 2007-10-31 19:28:01 +0800 | [diff] [blame] | 309 | u32 *ttl, dma_addr_t cmd_desc_paddr) |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 310 | { |
| 311 | struct scatterlist *sg; |
| 312 | unsigned int num_prde = 0; |
| 313 | u32 ttl_dwords = 0; |
| 314 | |
| 315 | /* |
| 316 | * NOTE : direct & indirect prdt's are contigiously allocated |
| 317 | */ |
| 318 | struct prde *prd = (struct prde *)&((struct command_desc *) |
| 319 | cmd_desc)->prdt; |
| 320 | |
| 321 | struct prde *prd_ptr_to_indirect_ext = NULL; |
| 322 | unsigned indirect_ext_segment_sz = 0; |
| 323 | dma_addr_t indirect_ext_segment_paddr; |
Tejun Heo | ff2aeb1 | 2007-12-05 16:43:11 +0900 | [diff] [blame] | 324 | unsigned int si; |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 325 | |
Anton Vorontsov | b1f5dc4 | 2008-02-22 19:54:25 +0300 | [diff] [blame] | 326 | VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd); |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 327 | |
| 328 | indirect_ext_segment_paddr = cmd_desc_paddr + |
| 329 | SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16; |
| 330 | |
Tejun Heo | ff2aeb1 | 2007-12-05 16:43:11 +0900 | [diff] [blame] | 331 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 332 | dma_addr_t sg_addr = sg_dma_address(sg); |
| 333 | u32 sg_len = sg_dma_len(sg); |
| 334 | |
| 335 | VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%x, sg_len = %d\n", |
| 336 | sg_addr, sg_len); |
| 337 | |
| 338 | /* warn if each s/g element is not dword aligned */ |
| 339 | if (sg_addr & 0x03) |
| 340 | ata_port_printk(qc->ap, KERN_ERR, |
| 341 | "s/g addr unaligned : 0x%x\n", sg_addr); |
| 342 | if (sg_len & 0x03) |
| 343 | ata_port_printk(qc->ap, KERN_ERR, |
| 344 | "s/g len unaligned : 0x%x\n", sg_len); |
| 345 | |
James Bottomley | 37198e3 | 2008-02-05 14:06:27 +0900 | [diff] [blame] | 346 | if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) && |
| 347 | sg_next(sg) != NULL) { |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 348 | VPRINTK("setting indirect prde\n"); |
| 349 | prd_ptr_to_indirect_ext = prd; |
| 350 | prd->dba = cpu_to_le32(indirect_ext_segment_paddr); |
| 351 | indirect_ext_segment_sz = 0; |
| 352 | ++prd; |
| 353 | ++num_prde; |
| 354 | } |
| 355 | |
| 356 | ttl_dwords += sg_len; |
| 357 | prd->dba = cpu_to_le32(sg_addr); |
| 358 | prd->ddc_and_ext = |
| 359 | cpu_to_le32(DATA_SNOOP_ENABLE | (sg_len & ~0x03)); |
| 360 | |
| 361 | VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n", |
| 362 | ttl_dwords, prd->dba, prd->ddc_and_ext); |
| 363 | |
| 364 | ++num_prde; |
| 365 | ++prd; |
| 366 | if (prd_ptr_to_indirect_ext) |
| 367 | indirect_ext_segment_sz += sg_len; |
| 368 | } |
| 369 | |
| 370 | if (prd_ptr_to_indirect_ext) { |
| 371 | /* set indirect extension flag along with indirect ext. size */ |
| 372 | prd_ptr_to_indirect_ext->ddc_and_ext = |
| 373 | cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG | |
| 374 | DATA_SNOOP_ENABLE | |
| 375 | (indirect_ext_segment_sz & ~0x03))); |
| 376 | } |
| 377 | |
| 378 | *ttl = ttl_dwords; |
| 379 | return num_prde; |
| 380 | } |
| 381 | |
| 382 | static void sata_fsl_qc_prep(struct ata_queued_cmd *qc) |
| 383 | { |
| 384 | struct ata_port *ap = qc->ap; |
| 385 | struct sata_fsl_port_priv *pp = ap->private_data; |
| 386 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; |
| 387 | void __iomem *hcr_base = host_priv->hcr_base; |
| 388 | unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); |
| 389 | struct command_desc *cd; |
| 390 | u32 desc_info = CMD_DESC_SNOOP_ENABLE; |
| 391 | u32 num_prde = 0; |
| 392 | u32 ttl_dwords = 0; |
| 393 | dma_addr_t cd_paddr; |
| 394 | |
| 395 | cd = (struct command_desc *)pp->cmdentry + tag; |
| 396 | cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE; |
| 397 | |
Li Yang | 520d3a1 | 2007-10-31 19:28:01 +0800 | [diff] [blame] | 398 | ata_tf_to_fis(&qc->tf, 0, 1, (u8 *) &cd->cfis); |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 399 | |
| 400 | VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n", |
| 401 | cd->cfis[0], cd->cfis[1], cd->cfis[2]); |
| 402 | |
| 403 | if (qc->tf.protocol == ATA_PROT_NCQ) { |
| 404 | VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n", |
| 405 | cd->cfis[3], cd->cfis[11]); |
| 406 | } |
| 407 | |
| 408 | /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */ |
Tejun Heo | 405e66b | 2007-11-27 19:28:53 +0900 | [diff] [blame] | 409 | if (ata_is_atapi(qc->tf.protocol)) { |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 410 | desc_info |= ATAPI_CMD; |
| 411 | memset((void *)&cd->acmd, 0, 32); |
| 412 | memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len); |
| 413 | } |
| 414 | |
| 415 | if (qc->flags & ATA_QCFLAG_DMAMAP) |
| 416 | num_prde = sata_fsl_fill_sg(qc, (void *)cd, |
| 417 | &ttl_dwords, cd_paddr); |
| 418 | |
| 419 | if (qc->tf.protocol == ATA_PROT_NCQ) |
| 420 | desc_info |= FPDMA_QUEUED_CMD; |
| 421 | |
| 422 | sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords, |
| 423 | num_prde, 5); |
| 424 | |
| 425 | VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n", |
| 426 | desc_info, ttl_dwords, num_prde); |
| 427 | } |
| 428 | |
| 429 | static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc) |
| 430 | { |
| 431 | struct ata_port *ap = qc->ap; |
| 432 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; |
| 433 | void __iomem *hcr_base = host_priv->hcr_base; |
| 434 | unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); |
| 435 | |
| 436 | VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n", |
| 437 | ioread32(CQ + hcr_base), |
| 438 | ioread32(CA + hcr_base), |
| 439 | ioread32(CE + hcr_base), ioread32(CC + hcr_base)); |
| 440 | |
| 441 | /* Simply queue command to the controller/device */ |
| 442 | iowrite32(1 << tag, CQ + hcr_base); |
| 443 | |
| 444 | VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n", |
| 445 | tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base)); |
| 446 | |
| 447 | VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n", |
| 448 | ioread32(CE + hcr_base), |
| 449 | ioread32(DE + hcr_base), |
Anton Vorontsov | b1f5dc4 | 2008-02-22 19:54:25 +0300 | [diff] [blame] | 450 | ioread32(CC + hcr_base), |
| 451 | ioread32(COMMANDSTAT + host_priv->csr_base)); |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 452 | |
| 453 | return 0; |
| 454 | } |
| 455 | |
Tejun Heo | 4c9bf4e | 2008-04-07 22:47:20 +0900 | [diff] [blame] | 456 | static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc) |
| 457 | { |
| 458 | struct sata_fsl_port_priv *pp = qc->ap->private_data; |
| 459 | struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data; |
| 460 | void __iomem *hcr_base = host_priv->hcr_base; |
| 461 | unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); |
| 462 | struct command_desc *cd; |
| 463 | |
| 464 | cd = pp->cmdentry + tag; |
| 465 | |
| 466 | ata_tf_from_fis(cd->sfis, &qc->result_tf); |
| 467 | return true; |
| 468 | } |
| 469 | |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 470 | static int sata_fsl_scr_write(struct ata_port *ap, unsigned int sc_reg_in, |
| 471 | u32 val) |
| 472 | { |
| 473 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; |
| 474 | void __iomem *ssr_base = host_priv->ssr_base; |
| 475 | unsigned int sc_reg; |
| 476 | |
| 477 | switch (sc_reg_in) { |
| 478 | case SCR_STATUS: |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 479 | case SCR_ERROR: |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 480 | case SCR_CONTROL: |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 481 | case SCR_ACTIVE: |
Jeff Garzik | 9465d53 | 2007-10-31 19:27:57 +0800 | [diff] [blame] | 482 | sc_reg = sc_reg_in; |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 483 | break; |
| 484 | default: |
| 485 | return -EINVAL; |
| 486 | } |
| 487 | |
| 488 | VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg); |
| 489 | |
Jeff Garzik | 2a52e8d | 2007-10-31 19:27:58 +0800 | [diff] [blame] | 490 | iowrite32(val, ssr_base + (sc_reg * 4)); |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 491 | return 0; |
| 492 | } |
| 493 | |
| 494 | static int sata_fsl_scr_read(struct ata_port *ap, unsigned int sc_reg_in, |
| 495 | u32 *val) |
| 496 | { |
| 497 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; |
| 498 | void __iomem *ssr_base = host_priv->ssr_base; |
| 499 | unsigned int sc_reg; |
| 500 | |
| 501 | switch (sc_reg_in) { |
| 502 | case SCR_STATUS: |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 503 | case SCR_ERROR: |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 504 | case SCR_CONTROL: |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 505 | case SCR_ACTIVE: |
Jeff Garzik | 9465d53 | 2007-10-31 19:27:57 +0800 | [diff] [blame] | 506 | sc_reg = sc_reg_in; |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 507 | break; |
| 508 | default: |
| 509 | return -EINVAL; |
| 510 | } |
| 511 | |
| 512 | VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg); |
| 513 | |
Jeff Garzik | 2a52e8d | 2007-10-31 19:27:58 +0800 | [diff] [blame] | 514 | *val = ioread32(ssr_base + (sc_reg * 4)); |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 515 | return 0; |
| 516 | } |
| 517 | |
| 518 | static void sata_fsl_freeze(struct ata_port *ap) |
| 519 | { |
| 520 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; |
| 521 | void __iomem *hcr_base = host_priv->hcr_base; |
| 522 | u32 temp; |
| 523 | |
| 524 | VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n", |
| 525 | ioread32(CQ + hcr_base), |
| 526 | ioread32(CA + hcr_base), |
| 527 | ioread32(CE + hcr_base), ioread32(DE + hcr_base)); |
Anton Vorontsov | b1f5dc4 | 2008-02-22 19:54:25 +0300 | [diff] [blame] | 528 | VPRINTK("CmdStat = 0x%x\n", |
| 529 | ioread32(host_priv->csr_base + COMMANDSTAT)); |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 530 | |
| 531 | /* disable interrupts on the controller/port */ |
| 532 | temp = ioread32(hcr_base + HCONTROL); |
| 533 | iowrite32((temp & ~0x3F), hcr_base + HCONTROL); |
| 534 | |
| 535 | VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n", |
| 536 | ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); |
| 537 | } |
| 538 | |
| 539 | static void sata_fsl_thaw(struct ata_port *ap) |
| 540 | { |
| 541 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; |
| 542 | void __iomem *hcr_base = host_priv->hcr_base; |
| 543 | u32 temp; |
| 544 | |
| 545 | /* ack. any pending IRQs for this controller/port */ |
| 546 | temp = ioread32(hcr_base + HSTATUS); |
| 547 | |
| 548 | VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F)); |
| 549 | |
| 550 | if (temp & 0x3F) |
| 551 | iowrite32((temp & 0x3F), hcr_base + HSTATUS); |
| 552 | |
| 553 | /* enable interrupts on the controller/port */ |
| 554 | temp = ioread32(hcr_base + HCONTROL); |
| 555 | iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); |
| 556 | |
| 557 | VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n", |
| 558 | ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); |
| 559 | } |
| 560 | |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 561 | static int sata_fsl_port_start(struct ata_port *ap) |
| 562 | { |
| 563 | struct device *dev = ap->host->dev; |
| 564 | struct sata_fsl_port_priv *pp; |
| 565 | int retval; |
| 566 | void *mem; |
| 567 | dma_addr_t mem_dma; |
| 568 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; |
| 569 | void __iomem *hcr_base = host_priv->hcr_base; |
| 570 | u32 temp; |
| 571 | |
| 572 | pp = kzalloc(sizeof(*pp), GFP_KERNEL); |
| 573 | if (!pp) |
| 574 | return -ENOMEM; |
| 575 | |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 576 | mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma, |
| 577 | GFP_KERNEL); |
| 578 | if (!mem) { |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 579 | kfree(pp); |
| 580 | return -ENOMEM; |
| 581 | } |
| 582 | memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ); |
| 583 | |
| 584 | pp->cmdslot = mem; |
| 585 | pp->cmdslot_paddr = mem_dma; |
| 586 | |
| 587 | mem += SATA_FSL_CMD_SLOT_SIZE; |
| 588 | mem_dma += SATA_FSL_CMD_SLOT_SIZE; |
| 589 | |
| 590 | pp->cmdentry = mem; |
| 591 | pp->cmdentry_paddr = mem_dma; |
| 592 | |
| 593 | ap->private_data = pp; |
| 594 | |
| 595 | VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n", |
| 596 | pp->cmdslot_paddr, pp->cmdentry_paddr); |
| 597 | |
| 598 | /* Now, update the CHBA register in host controller cmd register set */ |
| 599 | iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); |
| 600 | |
| 601 | /* |
| 602 | * Now, we can bring the controller on-line & also initiate |
| 603 | * the COMINIT sequence, we simply return here and the boot-probing |
| 604 | * & device discovery process is re-initiated by libATA using a |
| 605 | * Softreset EH (dummy) session. Hence, boot probing and device |
| 606 | * discovey will be part of sata_fsl_softreset() callback. |
| 607 | */ |
| 608 | |
| 609 | temp = ioread32(hcr_base + HCONTROL); |
| 610 | iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL); |
| 611 | |
| 612 | VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); |
| 613 | VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); |
| 614 | VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA)); |
| 615 | |
ashish kalra | e7eac96 | 2007-10-31 19:28:02 +0800 | [diff] [blame] | 616 | #ifdef CONFIG_MPC8315_DS |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 617 | /* |
| 618 | * Workaround for 8315DS board 3gbps link-up issue, |
| 619 | * currently limit SATA port to GEN1 speed |
| 620 | */ |
| 621 | sata_fsl_scr_read(ap, SCR_CONTROL, &temp); |
| 622 | temp &= ~(0xF << 4); |
| 623 | temp |= (0x1 << 4); |
| 624 | sata_fsl_scr_write(ap, SCR_CONTROL, temp); |
| 625 | |
| 626 | sata_fsl_scr_read(ap, SCR_CONTROL, &temp); |
| 627 | dev_printk(KERN_WARNING, dev, "scr_control, speed limited to %x\n", |
| 628 | temp); |
ashish kalra | e7eac96 | 2007-10-31 19:28:02 +0800 | [diff] [blame] | 629 | #endif |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 630 | |
| 631 | return 0; |
| 632 | } |
| 633 | |
| 634 | static void sata_fsl_port_stop(struct ata_port *ap) |
| 635 | { |
| 636 | struct device *dev = ap->host->dev; |
| 637 | struct sata_fsl_port_priv *pp = ap->private_data; |
| 638 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; |
| 639 | void __iomem *hcr_base = host_priv->hcr_base; |
| 640 | u32 temp; |
| 641 | |
| 642 | /* |
| 643 | * Force host controller to go off-line, aborting current operations |
| 644 | */ |
| 645 | temp = ioread32(hcr_base + HCONTROL); |
| 646 | temp &= ~HCONTROL_ONLINE_PHY_RST; |
| 647 | temp |= HCONTROL_FORCE_OFFLINE; |
| 648 | iowrite32(temp, hcr_base + HCONTROL); |
| 649 | |
| 650 | /* Poll for controller to go offline - should happen immediately */ |
| 651 | ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1); |
| 652 | |
| 653 | ap->private_data = NULL; |
| 654 | dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, |
| 655 | pp->cmdslot, pp->cmdslot_paddr); |
| 656 | |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 657 | kfree(pp); |
| 658 | } |
| 659 | |
| 660 | static unsigned int sata_fsl_dev_classify(struct ata_port *ap) |
| 661 | { |
| 662 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; |
| 663 | void __iomem *hcr_base = host_priv->hcr_base; |
| 664 | struct ata_taskfile tf; |
| 665 | u32 temp; |
| 666 | |
| 667 | temp = ioread32(hcr_base + SIGNATURE); |
| 668 | |
| 669 | VPRINTK("raw sig = 0x%x\n", temp); |
| 670 | VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); |
| 671 | VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); |
| 672 | |
| 673 | tf.lbah = (temp >> 24) & 0xff; |
| 674 | tf.lbam = (temp >> 16) & 0xff; |
| 675 | tf.lbal = (temp >> 8) & 0xff; |
| 676 | tf.nsect = temp & 0xff; |
| 677 | |
| 678 | return ata_dev_classify(&tf); |
| 679 | } |
| 680 | |
Li Yang | 1bf617b | 2007-10-31 19:27:53 +0800 | [diff] [blame] | 681 | static int sata_fsl_softreset(struct ata_link *link, unsigned int *class, |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 682 | unsigned long deadline) |
| 683 | { |
Li Yang | 1bf617b | 2007-10-31 19:27:53 +0800 | [diff] [blame] | 684 | struct ata_port *ap = link->ap; |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 685 | struct sata_fsl_port_priv *pp = ap->private_data; |
| 686 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; |
| 687 | void __iomem *hcr_base = host_priv->hcr_base; |
| 688 | u32 temp; |
| 689 | struct ata_taskfile tf; |
| 690 | u8 *cfis; |
| 691 | u32 Serror; |
| 692 | int i = 0; |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 693 | unsigned long start_jiffies; |
| 694 | |
| 695 | DPRINTK("in xx_softreset\n"); |
| 696 | |
| 697 | try_offline_again: |
| 698 | /* |
| 699 | * Force host controller to go off-line, aborting current operations |
| 700 | */ |
| 701 | temp = ioread32(hcr_base + HCONTROL); |
| 702 | temp &= ~HCONTROL_ONLINE_PHY_RST; |
| 703 | iowrite32(temp, hcr_base + HCONTROL); |
| 704 | |
| 705 | /* Poll for controller to go offline */ |
| 706 | temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 500); |
| 707 | |
| 708 | if (temp & ONLINE) { |
| 709 | ata_port_printk(ap, KERN_ERR, |
| 710 | "Softreset failed, not off-lined %d\n", i); |
| 711 | |
| 712 | /* |
| 713 | * Try to offline controller atleast twice |
| 714 | */ |
| 715 | i++; |
| 716 | if (i == 2) |
| 717 | goto err; |
| 718 | else |
| 719 | goto try_offline_again; |
| 720 | } |
| 721 | |
| 722 | DPRINTK("softreset, controller off-lined\n"); |
| 723 | VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); |
| 724 | VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); |
| 725 | |
| 726 | /* |
| 727 | * PHY reset should remain asserted for atleast 1ms |
| 728 | */ |
| 729 | msleep(1); |
| 730 | |
| 731 | /* |
| 732 | * Now, bring the host controller online again, this can take time |
| 733 | * as PHY reset and communication establishment, 1st D2H FIS and |
| 734 | * device signature update is done, on safe side assume 500ms |
| 735 | * NOTE : Host online status may be indicated immediately!! |
| 736 | */ |
| 737 | |
| 738 | temp = ioread32(hcr_base + HCONTROL); |
| 739 | temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE); |
| 740 | iowrite32(temp, hcr_base + HCONTROL); |
| 741 | |
| 742 | temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, 0, 1, 500); |
| 743 | |
| 744 | if (!(temp & ONLINE)) { |
| 745 | ata_port_printk(ap, KERN_ERR, |
| 746 | "Softreset failed, not on-lined\n"); |
| 747 | goto err; |
| 748 | } |
| 749 | |
| 750 | DPRINTK("softreset, controller off-lined & on-lined\n"); |
| 751 | VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); |
| 752 | VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); |
| 753 | |
| 754 | /* |
| 755 | * First, wait for the PHYRDY change to occur before waiting for |
| 756 | * the signature, and also verify if SStatus indicates device |
| 757 | * presence |
| 758 | */ |
| 759 | |
| 760 | temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0, 1, 500); |
Li Yang | 1bf617b | 2007-10-31 19:27:53 +0800 | [diff] [blame] | 761 | if ((!(temp & 0x10)) || ata_link_offline(link)) { |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 762 | ata_port_printk(ap, KERN_WARNING, |
| 763 | "No Device OR PHYRDY change,Hstatus = 0x%x\n", |
| 764 | ioread32(hcr_base + HSTATUS)); |
| 765 | goto err; |
| 766 | } |
| 767 | |
| 768 | /* |
| 769 | * Wait for the first D2H from device,i.e,signature update notification |
| 770 | */ |
| 771 | start_jiffies = jiffies; |
| 772 | temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0x10, |
| 773 | 500, jiffies_to_msecs(deadline - start_jiffies)); |
| 774 | |
| 775 | if ((temp & 0xFF) != 0x18) { |
| 776 | ata_port_printk(ap, KERN_WARNING, "No Signature Update\n"); |
| 777 | goto err; |
| 778 | } else { |
| 779 | ata_port_printk(ap, KERN_INFO, |
| 780 | "Signature Update detected @ %d msecs\n", |
| 781 | jiffies_to_msecs(jiffies - start_jiffies)); |
| 782 | } |
| 783 | |
| 784 | /* |
| 785 | * Send a device reset (SRST) explicitly on command slot #0 |
| 786 | * Check : will the command queue (reg) be cleared during offlining ?? |
| 787 | * Also we will be online only if Phy commn. has been established |
| 788 | * and device presence has been detected, therefore if we have |
| 789 | * reached here, we can send a command to the target device |
| 790 | */ |
| 791 | |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 792 | DPRINTK("Sending SRST/device reset\n"); |
| 793 | |
Li Yang | 1bf617b | 2007-10-31 19:27:53 +0800 | [diff] [blame] | 794 | ata_tf_init(link->device, &tf); |
Li Yang | 520d3a1 | 2007-10-31 19:28:01 +0800 | [diff] [blame] | 795 | cfis = (u8 *) &pp->cmdentry->cfis; |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 796 | |
| 797 | /* device reset/SRST is a control register update FIS, uses tag0 */ |
| 798 | sata_fsl_setup_cmd_hdr_entry(pp, 0, |
| 799 | SRST_CMD | CMD_DESC_SNOOP_ENABLE, 0, 0, 5); |
| 800 | |
| 801 | tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */ |
| 802 | ata_tf_to_fis(&tf, 0, 0, cfis); |
| 803 | |
| 804 | DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n", |
| 805 | cfis[0], cfis[1], cfis[2], cfis[3]); |
| 806 | |
| 807 | /* |
| 808 | * Queue SRST command to the controller/device, ensure that no |
| 809 | * other commands are active on the controller/device |
| 810 | */ |
| 811 | |
| 812 | DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n", |
| 813 | ioread32(CQ + hcr_base), |
| 814 | ioread32(CA + hcr_base), ioread32(CC + hcr_base)); |
| 815 | |
| 816 | iowrite32(0xFFFF, CC + hcr_base); |
| 817 | iowrite32(1, CQ + hcr_base); |
| 818 | |
| 819 | temp = ata_wait_register(CQ + hcr_base, 0x1, 0x1, 1, 5000); |
| 820 | if (temp & 0x1) { |
| 821 | ata_port_printk(ap, KERN_WARNING, "ATA_SRST issue failed\n"); |
| 822 | |
| 823 | DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n", |
| 824 | ioread32(CQ + hcr_base), |
| 825 | ioread32(CA + hcr_base), ioread32(CC + hcr_base)); |
| 826 | |
| 827 | sata_fsl_scr_read(ap, SCR_ERROR, &Serror); |
| 828 | |
| 829 | DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); |
| 830 | DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); |
| 831 | DPRINTK("Serror = 0x%x\n", Serror); |
| 832 | goto err; |
| 833 | } |
| 834 | |
| 835 | msleep(1); |
| 836 | |
| 837 | /* |
| 838 | * SATA device enters reset state after receving a Control register |
| 839 | * FIS with SRST bit asserted and it awaits another H2D Control reg. |
| 840 | * FIS with SRST bit cleared, then the device does internal diags & |
| 841 | * initialization, followed by indicating it's initialization status |
| 842 | * using ATA signature D2H register FIS to the host controller. |
| 843 | */ |
| 844 | |
| 845 | sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_SNOOP_ENABLE, 0, 0, 5); |
| 846 | |
| 847 | tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */ |
| 848 | ata_tf_to_fis(&tf, 0, 0, cfis); |
| 849 | |
| 850 | iowrite32(1, CQ + hcr_base); |
| 851 | msleep(150); /* ?? */ |
| 852 | |
| 853 | /* |
| 854 | * The above command would have signalled an interrupt on command |
| 855 | * complete, which needs special handling, by clearing the Nth |
| 856 | * command bit of the CCreg |
| 857 | */ |
| 858 | iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */ |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 859 | |
| 860 | DPRINTK("SATA FSL : Now checking device signature\n"); |
| 861 | |
| 862 | *class = ATA_DEV_NONE; |
| 863 | |
| 864 | /* Verify if SStatus indicates device presence */ |
Li Yang | 1bf617b | 2007-10-31 19:27:53 +0800 | [diff] [blame] | 865 | if (ata_link_online(link)) { |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 866 | /* |
| 867 | * if we are here, device presence has been detected, |
| 868 | * 1st D2H FIS would have been received, but sfis in |
| 869 | * command desc. is not updated, but signature register |
| 870 | * would have been updated |
| 871 | */ |
| 872 | |
| 873 | *class = sata_fsl_dev_classify(ap); |
| 874 | |
| 875 | DPRINTK("class = %d\n", *class); |
| 876 | VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC)); |
| 877 | VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE)); |
| 878 | } |
| 879 | |
| 880 | return 0; |
| 881 | |
| 882 | err: |
| 883 | return -EIO; |
| 884 | } |
| 885 | |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 886 | static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc) |
| 887 | { |
| 888 | if (qc->flags & ATA_QCFLAG_FAILED) |
| 889 | qc->err_mask |= AC_ERR_OTHER; |
| 890 | |
| 891 | if (qc->err_mask) { |
| 892 | /* make DMA engine forget about the failed command */ |
| 893 | |
| 894 | } |
| 895 | } |
| 896 | |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 897 | static void sata_fsl_error_intr(struct ata_port *ap) |
| 898 | { |
Li Yang | 1bf617b | 2007-10-31 19:27:53 +0800 | [diff] [blame] | 899 | struct ata_link *link = &ap->link; |
| 900 | struct ata_eh_info *ehi = &link->eh_info; |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 901 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; |
| 902 | void __iomem *hcr_base = host_priv->hcr_base; |
| 903 | u32 hstatus, dereg, cereg = 0, SError = 0; |
| 904 | unsigned int err_mask = 0, action = 0; |
| 905 | struct ata_queued_cmd *qc; |
| 906 | int freeze = 0; |
| 907 | |
| 908 | hstatus = ioread32(hcr_base + HSTATUS); |
| 909 | cereg = ioread32(hcr_base + CE); |
| 910 | |
| 911 | ata_ehi_clear_desc(ehi); |
| 912 | |
| 913 | /* |
| 914 | * Handle & Clear SError |
| 915 | */ |
| 916 | |
| 917 | sata_fsl_scr_read(ap, SCR_ERROR, &SError); |
| 918 | if (unlikely(SError & 0xFFFF0000)) { |
| 919 | sata_fsl_scr_write(ap, SCR_ERROR, SError); |
| 920 | err_mask |= AC_ERR_ATA_BUS; |
| 921 | } |
| 922 | |
| 923 | DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n", |
| 924 | hstatus, cereg, ioread32(hcr_base + DE), SError); |
| 925 | |
| 926 | /* handle single device errors */ |
| 927 | if (cereg) { |
| 928 | /* |
| 929 | * clear the command error, also clears queue to the device |
| 930 | * in error, and we can (re)issue commands to this device. |
| 931 | * When a device is in error all commands queued into the |
| 932 | * host controller and at the device are considered aborted |
| 933 | * and the queue for that device is stopped. Now, after |
| 934 | * clearing the device error, we can issue commands to the |
| 935 | * device to interrogate it to find the source of the error. |
| 936 | */ |
| 937 | dereg = ioread32(hcr_base + DE); |
| 938 | iowrite32(dereg, hcr_base + DE); |
| 939 | iowrite32(cereg, hcr_base + CE); |
| 940 | |
| 941 | DPRINTK("single device error, CE=0x%x, DE=0x%x\n", |
| 942 | ioread32(hcr_base + CE), ioread32(hcr_base + DE)); |
| 943 | /* |
| 944 | * We should consider this as non fatal error, and TF must |
| 945 | * be updated as done below. |
| 946 | */ |
| 947 | |
| 948 | err_mask |= AC_ERR_DEV; |
| 949 | } |
| 950 | |
| 951 | /* handle fatal errors */ |
| 952 | if (hstatus & FATAL_ERROR_DECODE) { |
| 953 | err_mask |= AC_ERR_ATA_BUS; |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 954 | action |= ATA_EH_RESET; |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 955 | /* how will fatal error interrupts be completed ?? */ |
| 956 | freeze = 1; |
| 957 | } |
| 958 | |
| 959 | /* Handle PHYRDY change notification */ |
| 960 | if (hstatus & INT_ON_PHYRDY_CHG) { |
| 961 | DPRINTK("SATA FSL: PHYRDY change indication\n"); |
| 962 | |
| 963 | /* Setup a soft-reset EH action */ |
| 964 | ata_ehi_hotplugged(ehi); |
| 965 | freeze = 1; |
| 966 | } |
| 967 | |
| 968 | /* record error info */ |
Li Yang | 1bf617b | 2007-10-31 19:27:53 +0800 | [diff] [blame] | 969 | qc = ata_qc_from_tag(ap, link->active_tag); |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 970 | |
Tejun Heo | 520d06f | 2008-04-07 22:47:21 +0900 | [diff] [blame^] | 971 | if (qc) |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 972 | qc->err_mask |= err_mask; |
Tejun Heo | 520d06f | 2008-04-07 22:47:21 +0900 | [diff] [blame^] | 973 | else |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 974 | ehi->err_mask |= err_mask; |
| 975 | |
| 976 | ehi->action |= action; |
| 977 | ehi->serror |= SError; |
| 978 | |
| 979 | /* freeze or abort */ |
| 980 | if (freeze) |
| 981 | ata_port_freeze(ap); |
| 982 | else |
| 983 | ata_port_abort(ap); |
| 984 | } |
| 985 | |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 986 | static void sata_fsl_host_intr(struct ata_port *ap) |
| 987 | { |
Li Yang | 1bf617b | 2007-10-31 19:27:53 +0800 | [diff] [blame] | 988 | struct ata_link *link = &ap->link; |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 989 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; |
| 990 | void __iomem *hcr_base = host_priv->hcr_base; |
| 991 | u32 hstatus, qc_active = 0; |
| 992 | struct ata_queued_cmd *qc; |
| 993 | u32 SError; |
| 994 | |
| 995 | hstatus = ioread32(hcr_base + HSTATUS); |
| 996 | |
| 997 | sata_fsl_scr_read(ap, SCR_ERROR, &SError); |
| 998 | |
| 999 | if (unlikely(SError & 0xFFFF0000)) { |
| 1000 | DPRINTK("serror @host_intr : 0x%x\n", SError); |
| 1001 | sata_fsl_error_intr(ap); |
| 1002 | |
| 1003 | } |
| 1004 | |
| 1005 | if (unlikely(hstatus & INT_ON_ERROR)) { |
| 1006 | DPRINTK("error interrupt!!\n"); |
| 1007 | sata_fsl_error_intr(ap); |
| 1008 | return; |
| 1009 | } |
| 1010 | |
Li Yang | 1bf617b | 2007-10-31 19:27:53 +0800 | [diff] [blame] | 1011 | if (link->sactive) { /* only true for NCQ commands */ |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 1012 | int i; |
| 1013 | /* Read command completed register */ |
| 1014 | qc_active = ioread32(hcr_base + CC); |
| 1015 | /* clear CC bit, this will also complete the interrupt */ |
| 1016 | iowrite32(qc_active, hcr_base + CC); |
| 1017 | |
| 1018 | DPRINTK("Status of all queues :\n"); |
| 1019 | DPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x\n", |
| 1020 | qc_active, ioread32(hcr_base + CA), |
| 1021 | ioread32(hcr_base + CE)); |
| 1022 | |
| 1023 | for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) { |
| 1024 | if (qc_active & (1 << i)) { |
| 1025 | qc = ata_qc_from_tag(ap, i); |
Tejun Heo | 520d06f | 2008-04-07 22:47:21 +0900 | [diff] [blame^] | 1026 | if (qc) |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 1027 | ata_qc_complete(qc); |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 1028 | DPRINTK |
| 1029 | ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n", |
| 1030 | i, ioread32(hcr_base + CC), |
| 1031 | ioread32(hcr_base + CA)); |
| 1032 | } |
| 1033 | } |
| 1034 | return; |
| 1035 | |
| 1036 | } else if (ap->qc_active) { |
| 1037 | iowrite32(1, hcr_base + CC); |
Li Yang | 1bf617b | 2007-10-31 19:27:53 +0800 | [diff] [blame] | 1038 | qc = ata_qc_from_tag(ap, link->active_tag); |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 1039 | |
| 1040 | DPRINTK("completing non-ncq cmd, tag=%d,CC=0x%x\n", |
Li Yang | 1bf617b | 2007-10-31 19:27:53 +0800 | [diff] [blame] | 1041 | link->active_tag, ioread32(hcr_base + CC)); |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 1042 | |
Tejun Heo | 520d06f | 2008-04-07 22:47:21 +0900 | [diff] [blame^] | 1043 | if (qc) |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 1044 | ata_qc_complete(qc); |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 1045 | } else { |
| 1046 | /* Spurious Interrupt!! */ |
| 1047 | DPRINTK("spurious interrupt!!, CC = 0x%x\n", |
| 1048 | ioread32(hcr_base + CC)); |
| 1049 | return; |
| 1050 | } |
| 1051 | } |
| 1052 | |
| 1053 | static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance) |
| 1054 | { |
| 1055 | struct ata_host *host = dev_instance; |
| 1056 | struct sata_fsl_host_priv *host_priv = host->private_data; |
| 1057 | void __iomem *hcr_base = host_priv->hcr_base; |
| 1058 | u32 interrupt_enables; |
| 1059 | unsigned handled = 0; |
| 1060 | struct ata_port *ap; |
| 1061 | |
| 1062 | /* ack. any pending IRQs for this controller/port */ |
| 1063 | interrupt_enables = ioread32(hcr_base + HSTATUS); |
| 1064 | interrupt_enables &= 0x3F; |
| 1065 | |
| 1066 | DPRINTK("interrupt status 0x%x\n", interrupt_enables); |
| 1067 | |
| 1068 | if (!interrupt_enables) |
| 1069 | return IRQ_NONE; |
| 1070 | |
| 1071 | spin_lock(&host->lock); |
| 1072 | |
| 1073 | /* Assuming one port per host controller */ |
| 1074 | |
| 1075 | ap = host->ports[0]; |
| 1076 | if (ap) { |
| 1077 | sata_fsl_host_intr(ap); |
| 1078 | } else { |
| 1079 | dev_printk(KERN_WARNING, host->dev, |
| 1080 | "interrupt on disabled port 0\n"); |
| 1081 | } |
| 1082 | |
| 1083 | iowrite32(interrupt_enables, hcr_base + HSTATUS); |
| 1084 | handled = 1; |
| 1085 | |
| 1086 | spin_unlock(&host->lock); |
| 1087 | |
| 1088 | return IRQ_RETVAL(handled); |
| 1089 | } |
| 1090 | |
| 1091 | /* |
| 1092 | * Multiple ports are represented by multiple SATA controllers with |
| 1093 | * one port per controller |
| 1094 | */ |
| 1095 | static int sata_fsl_init_controller(struct ata_host *host) |
| 1096 | { |
| 1097 | struct sata_fsl_host_priv *host_priv = host->private_data; |
| 1098 | void __iomem *hcr_base = host_priv->hcr_base; |
| 1099 | u32 temp; |
| 1100 | |
| 1101 | /* |
| 1102 | * NOTE : We cannot bring the controller online before setting |
| 1103 | * the CHBA, hence main controller initialization is done as |
| 1104 | * part of the port_start() callback |
| 1105 | */ |
| 1106 | |
| 1107 | /* ack. any pending IRQs for this controller/port */ |
| 1108 | temp = ioread32(hcr_base + HSTATUS); |
| 1109 | if (temp & 0x3F) |
| 1110 | iowrite32((temp & 0x3F), hcr_base + HSTATUS); |
| 1111 | |
| 1112 | /* Keep interrupts disabled on the controller */ |
| 1113 | temp = ioread32(hcr_base + HCONTROL); |
| 1114 | iowrite32((temp & ~0x3F), hcr_base + HCONTROL); |
| 1115 | |
| 1116 | /* Disable interrupt coalescing control(icc), for the moment */ |
| 1117 | DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC)); |
| 1118 | iowrite32(0x01000000, hcr_base + ICC); |
| 1119 | |
| 1120 | /* clear error registers, SError is cleared by libATA */ |
| 1121 | iowrite32(0x00000FFFF, hcr_base + CE); |
| 1122 | iowrite32(0x00000FFFF, hcr_base + DE); |
| 1123 | |
| 1124 | /* initially assuming no Port multiplier, set CQPMP to 0 */ |
| 1125 | iowrite32(0x0, hcr_base + CQPMP); |
| 1126 | |
| 1127 | /* |
| 1128 | * host controller will be brought on-line, during xx_port_start() |
| 1129 | * callback, that should also initiate the OOB, COMINIT sequence |
| 1130 | */ |
| 1131 | |
| 1132 | DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); |
| 1133 | DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); |
| 1134 | |
| 1135 | return 0; |
| 1136 | } |
| 1137 | |
| 1138 | /* |
| 1139 | * scsi mid-layer and libata interface structures |
| 1140 | */ |
| 1141 | static struct scsi_host_template sata_fsl_sht = { |
Tejun Heo | 68d1d07 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 1142 | ATA_NCQ_SHT("sata_fsl"), |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 1143 | .can_queue = SATA_FSL_QUEUE_DEPTH, |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 1144 | .sg_tablesize = SATA_FSL_MAX_PRD_USABLE, |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 1145 | .dma_boundary = ATA_DMA_BOUNDARY, |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 1146 | }; |
| 1147 | |
| 1148 | static const struct ata_port_operations sata_fsl_ops = { |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 1149 | .inherits = &sata_port_ops, |
| 1150 | |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 1151 | .qc_prep = sata_fsl_qc_prep, |
| 1152 | .qc_issue = sata_fsl_qc_issue, |
Tejun Heo | 4c9bf4e | 2008-04-07 22:47:20 +0900 | [diff] [blame] | 1153 | .qc_fill_rtf = sata_fsl_qc_fill_rtf, |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 1154 | |
| 1155 | .scr_read = sata_fsl_scr_read, |
| 1156 | .scr_write = sata_fsl_scr_write, |
| 1157 | |
| 1158 | .freeze = sata_fsl_freeze, |
| 1159 | .thaw = sata_fsl_thaw, |
Tejun Heo | a1efdab | 2008-03-25 12:22:50 +0900 | [diff] [blame] | 1160 | .softreset = sata_fsl_softreset, |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 1161 | .post_internal_cmd = sata_fsl_post_internal_cmd, |
| 1162 | |
| 1163 | .port_start = sata_fsl_port_start, |
| 1164 | .port_stop = sata_fsl_port_stop, |
| 1165 | }; |
| 1166 | |
| 1167 | static const struct ata_port_info sata_fsl_port_info[] = { |
| 1168 | { |
| 1169 | .flags = SATA_FSL_HOST_FLAGS, |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 1170 | .pio_mask = 0x1f, /* pio 0-4 */ |
| 1171 | .udma_mask = 0x7f, /* udma 0-6 */ |
| 1172 | .port_ops = &sata_fsl_ops, |
| 1173 | }, |
| 1174 | }; |
| 1175 | |
| 1176 | static int sata_fsl_probe(struct of_device *ofdev, |
| 1177 | const struct of_device_id *match) |
| 1178 | { |
| 1179 | int retval = 0; |
| 1180 | void __iomem *hcr_base = NULL; |
| 1181 | void __iomem *ssr_base = NULL; |
| 1182 | void __iomem *csr_base = NULL; |
| 1183 | struct sata_fsl_host_priv *host_priv = NULL; |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 1184 | int irq; |
| 1185 | struct ata_host *host; |
| 1186 | |
| 1187 | struct ata_port_info pi = sata_fsl_port_info[0]; |
| 1188 | const struct ata_port_info *ppi[] = { &pi, NULL }; |
| 1189 | |
| 1190 | dev_printk(KERN_INFO, &ofdev->dev, |
| 1191 | "Sata FSL Platform/CSB Driver init\n"); |
| 1192 | |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 1193 | hcr_base = of_iomap(ofdev->node, 0); |
| 1194 | if (!hcr_base) |
| 1195 | goto error_exit_with_cleanup; |
| 1196 | |
| 1197 | ssr_base = hcr_base + 0x100; |
| 1198 | csr_base = hcr_base + 0x140; |
| 1199 | |
| 1200 | DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG)); |
| 1201 | DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc)); |
| 1202 | DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE); |
| 1203 | |
| 1204 | host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL); |
| 1205 | if (!host_priv) |
| 1206 | goto error_exit_with_cleanup; |
| 1207 | |
| 1208 | host_priv->hcr_base = hcr_base; |
| 1209 | host_priv->ssr_base = ssr_base; |
| 1210 | host_priv->csr_base = csr_base; |
| 1211 | |
| 1212 | irq = irq_of_parse_and_map(ofdev->node, 0); |
| 1213 | if (irq < 0) { |
| 1214 | dev_printk(KERN_ERR, &ofdev->dev, "invalid irq from platform\n"); |
| 1215 | goto error_exit_with_cleanup; |
| 1216 | } |
Li Yang | 79b3edc | 2007-10-31 19:27:55 +0800 | [diff] [blame] | 1217 | host_priv->irq = irq; |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 1218 | |
| 1219 | /* allocate host structure */ |
| 1220 | host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS); |
| 1221 | |
| 1222 | /* host->iomap is not used currently */ |
| 1223 | host->private_data = host_priv; |
| 1224 | |
| 1225 | /* setup port(s) */ |
| 1226 | |
| 1227 | host->ports[0]->ioaddr.cmd_addr = host_priv->hcr_base; |
| 1228 | host->ports[0]->ioaddr.scr_addr = host_priv->ssr_base; |
| 1229 | |
| 1230 | /* initialize host controller */ |
| 1231 | sata_fsl_init_controller(host); |
| 1232 | |
| 1233 | /* |
| 1234 | * Now, register with libATA core, this will also initiate the |
| 1235 | * device discovery process, invoking our port_start() handler & |
| 1236 | * error_handler() to execute a dummy Softreset EH session |
| 1237 | */ |
| 1238 | ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG, |
| 1239 | &sata_fsl_sht); |
| 1240 | |
| 1241 | dev_set_drvdata(&ofdev->dev, host); |
| 1242 | |
| 1243 | return 0; |
| 1244 | |
| 1245 | error_exit_with_cleanup: |
| 1246 | |
| 1247 | if (hcr_base) |
| 1248 | iounmap(hcr_base); |
| 1249 | if (host_priv) |
| 1250 | kfree(host_priv); |
| 1251 | |
| 1252 | return retval; |
| 1253 | } |
| 1254 | |
| 1255 | static int sata_fsl_remove(struct of_device *ofdev) |
| 1256 | { |
| 1257 | struct ata_host *host = dev_get_drvdata(&ofdev->dev); |
| 1258 | struct sata_fsl_host_priv *host_priv = host->private_data; |
| 1259 | |
| 1260 | ata_host_detach(host); |
| 1261 | |
| 1262 | dev_set_drvdata(&ofdev->dev, NULL); |
| 1263 | |
Li Yang | 79b3edc | 2007-10-31 19:27:55 +0800 | [diff] [blame] | 1264 | irq_dispose_mapping(host_priv->irq); |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 1265 | iounmap(host_priv->hcr_base); |
| 1266 | kfree(host_priv); |
| 1267 | |
| 1268 | return 0; |
| 1269 | } |
| 1270 | |
| 1271 | static struct of_device_id fsl_sata_match[] = { |
| 1272 | { |
Kim Phillips | 96ce1b6 | 2008-03-28 10:51:33 -0500 | [diff] [blame] | 1273 | .compatible = "fsl,pq-sata", |
Li Yang | faf0b2e | 2007-10-16 20:58:38 +0800 | [diff] [blame] | 1274 | }, |
| 1275 | {}, |
| 1276 | }; |
| 1277 | |
| 1278 | MODULE_DEVICE_TABLE(of, fsl_sata_match); |
| 1279 | |
| 1280 | static struct of_platform_driver fsl_sata_driver = { |
| 1281 | .name = "fsl-sata", |
| 1282 | .match_table = fsl_sata_match, |
| 1283 | .probe = sata_fsl_probe, |
| 1284 | .remove = sata_fsl_remove, |
| 1285 | }; |
| 1286 | |
| 1287 | static int __init sata_fsl_init(void) |
| 1288 | { |
| 1289 | of_register_platform_driver(&fsl_sata_driver); |
| 1290 | return 0; |
| 1291 | } |
| 1292 | |
| 1293 | static void __exit sata_fsl_exit(void) |
| 1294 | { |
| 1295 | of_unregister_platform_driver(&fsl_sata_driver); |
| 1296 | } |
| 1297 | |
| 1298 | MODULE_LICENSE("GPL"); |
| 1299 | MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor"); |
| 1300 | MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver"); |
| 1301 | MODULE_VERSION("1.10"); |
| 1302 | |
| 1303 | module_init(sata_fsl_init); |
| 1304 | module_exit(sata_fsl_exit); |