| Philippe De Muyter | 5291fa9 | 2010-10-27 14:57:47 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * Bit definitions for the MCF54xx ACR and CACR registers. |
| 3 | */ |
| 4 | |
| 5 | #ifndef m54xxacr_h |
| 6 | #define m54xxacr_h |
| 7 | |
| 8 | /* |
| 9 | * Define the Cache register flags. |
| 10 | */ |
| 11 | #define CACR_DEC 0x80000000 /* Enable data cache */ |
| 12 | #define CACR_DWP 0x40000000 /* Data write protection */ |
| 13 | #define CACR_DESB 0x20000000 /* Enable data store buffer */ |
| 14 | #define CACR_DDPI 0x10000000 /* Disable invalidation by CPUSHL */ |
| 15 | #define CACR_DHCLK 0x08000000 /* Half data cache lock mode */ |
| 16 | #define CACR_DDCM_WT 0x00000000 /* Write through cache*/ |
| 17 | #define CACR_DDCM_CP 0x02000000 /* Copyback cache */ |
| 18 | #define CACR_DDCM_P 0x04000000 /* No cache, precise */ |
| 19 | #define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */ |
| 20 | #define CACR_DCINVA 0x01000000 /* Invalidate data cache */ |
| 21 | #define CACR_BEC 0x00080000 /* Enable branch cache */ |
| 22 | #define CACR_BCINVA 0x00040000 /* Invalidate branch cache */ |
| 23 | #define CACR_IEC 0x00008000 /* Enable instruction cache */ |
| 24 | #define CACR_DNFB 0x00002000 /* Inhibited fill buffer */ |
| 25 | #define CACR_IDPI 0x00001000 /* Disable CPUSHL */ |
| 26 | #define CACR_IHLCK 0x00000800 /* Intruction cache half lock */ |
| 27 | #define CACR_IDCM 0x00000400 /* Intruction cache inhibit */ |
| 28 | #define CACR_ICINVA 0x00000100 /* Invalidate instr cache */ |
| 29 | |
| 30 | #define ACR_BASE_POS 24 /* Address Base */ |
| 31 | #define ACR_MASK_POS 16 /* Address Mask */ |
| 32 | #define ACR_ENABLE 0x00008000 /* Enable address */ |
| 33 | #define ACR_USER 0x00000000 /* User mode access only */ |
| 34 | #define ACR_SUPER 0x00002000 /* Supervisor mode only */ |
| 35 | #define ACR_ANY 0x00004000 /* Match any access mode */ |
| 36 | #define ACR_CM_WT 0x00000000 /* Write through mode */ |
| 37 | #define ACR_CM_CP 0x00000020 /* Copyback mode */ |
| 38 | #define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */ |
| 39 | #define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */ |
| 40 | #define ACR_CM 0x00000060 /* Cache mode mask */ |
| 41 | #define ACR_WPROTECT 0x00000004 /* Write protect */ |
| 42 | |
| 43 | #endif /* m54xxacr_h */ |