| Tero Kristo | 52b1472 | 2013-07-18 17:15:51 +0300 | [diff] [blame^] | 1 | /* |
| 2 | * OMAP5 Clock init |
| 3 | * |
| 4 | * Copyright (C) 2013 Texas Instruments, Inc. |
| 5 | * |
| 6 | * Tero Kristo (t-kristo@ti.com) |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/list.h> |
| 15 | #include <linux/clk-private.h> |
| 16 | #include <linux/clkdev.h> |
| 17 | #include <linux/io.h> |
| 18 | #include <linux/clk/ti.h> |
| 19 | |
| 20 | #define OMAP5_DPLL_ABE_DEFFREQ 98304000 |
| 21 | |
| 22 | static struct ti_dt_clk omap54xx_clks[] = { |
| 23 | DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"), |
| 24 | DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"), |
| 25 | DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"), |
| 26 | DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"), |
| 27 | DT_CLK(NULL, "slimbus_clk", "slimbus_clk"), |
| 28 | DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"), |
| 29 | DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"), |
| 30 | DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"), |
| 31 | DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"), |
| 32 | DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), |
| 33 | DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), |
| 34 | DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"), |
| 35 | DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"), |
| 36 | DT_CLK(NULL, "sys_clkin", "sys_clkin"), |
| 37 | DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"), |
| 38 | DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"), |
| 39 | DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"), |
| 40 | DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"), |
| 41 | DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"), |
| 42 | DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"), |
| 43 | DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"), |
| 44 | DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"), |
| 45 | DT_CLK(NULL, "abe_clk", "abe_clk"), |
| 46 | DT_CLK(NULL, "abe_iclk", "abe_iclk"), |
| 47 | DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"), |
| 48 | DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"), |
| 49 | DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"), |
| 50 | DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"), |
| 51 | DT_CLK(NULL, "dpll_core_h21x2_ck", "dpll_core_h21x2_ck"), |
| 52 | DT_CLK(NULL, "c2c_fclk", "c2c_fclk"), |
| 53 | DT_CLK(NULL, "c2c_iclk", "c2c_iclk"), |
| 54 | DT_CLK(NULL, "custefuse_sys_gfclk_div", "custefuse_sys_gfclk_div"), |
| 55 | DT_CLK(NULL, "dpll_core_h11x2_ck", "dpll_core_h11x2_ck"), |
| 56 | DT_CLK(NULL, "dpll_core_h12x2_ck", "dpll_core_h12x2_ck"), |
| 57 | DT_CLK(NULL, "dpll_core_h13x2_ck", "dpll_core_h13x2_ck"), |
| 58 | DT_CLK(NULL, "dpll_core_h14x2_ck", "dpll_core_h14x2_ck"), |
| 59 | DT_CLK(NULL, "dpll_core_h22x2_ck", "dpll_core_h22x2_ck"), |
| 60 | DT_CLK(NULL, "dpll_core_h23x2_ck", "dpll_core_h23x2_ck"), |
| 61 | DT_CLK(NULL, "dpll_core_h24x2_ck", "dpll_core_h24x2_ck"), |
| 62 | DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"), |
| 63 | DT_CLK(NULL, "dpll_core_m3x2_ck", "dpll_core_m3x2_ck"), |
| 64 | DT_CLK(NULL, "iva_dpll_hs_clk_div", "iva_dpll_hs_clk_div"), |
| 65 | DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"), |
| 66 | DT_CLK(NULL, "dpll_iva_x2_ck", "dpll_iva_x2_ck"), |
| 67 | DT_CLK(NULL, "dpll_iva_h11x2_ck", "dpll_iva_h11x2_ck"), |
| 68 | DT_CLK(NULL, "dpll_iva_h12x2_ck", "dpll_iva_h12x2_ck"), |
| 69 | DT_CLK(NULL, "mpu_dpll_hs_clk_div", "mpu_dpll_hs_clk_div"), |
| 70 | DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"), |
| 71 | DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"), |
| 72 | DT_CLK(NULL, "per_dpll_hs_clk_div", "per_dpll_hs_clk_div"), |
| 73 | DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"), |
| 74 | DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"), |
| 75 | DT_CLK(NULL, "dpll_per_h11x2_ck", "dpll_per_h11x2_ck"), |
| 76 | DT_CLK(NULL, "dpll_per_h12x2_ck", "dpll_per_h12x2_ck"), |
| 77 | DT_CLK(NULL, "dpll_per_h14x2_ck", "dpll_per_h14x2_ck"), |
| 78 | DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"), |
| 79 | DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"), |
| 80 | DT_CLK(NULL, "dpll_per_m3x2_ck", "dpll_per_m3x2_ck"), |
| 81 | DT_CLK(NULL, "dpll_unipro1_ck", "dpll_unipro1_ck"), |
| 82 | DT_CLK(NULL, "dpll_unipro1_clkdcoldo", "dpll_unipro1_clkdcoldo"), |
| 83 | DT_CLK(NULL, "dpll_unipro1_m2_ck", "dpll_unipro1_m2_ck"), |
| 84 | DT_CLK(NULL, "dpll_unipro2_ck", "dpll_unipro2_ck"), |
| 85 | DT_CLK(NULL, "dpll_unipro2_clkdcoldo", "dpll_unipro2_clkdcoldo"), |
| 86 | DT_CLK(NULL, "dpll_unipro2_m2_ck", "dpll_unipro2_m2_ck"), |
| 87 | DT_CLK(NULL, "usb_dpll_hs_clk_div", "usb_dpll_hs_clk_div"), |
| 88 | DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"), |
| 89 | DT_CLK(NULL, "dpll_usb_clkdcoldo", "dpll_usb_clkdcoldo"), |
| 90 | DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"), |
| 91 | DT_CLK(NULL, "dss_syc_gfclk_div", "dss_syc_gfclk_div"), |
| 92 | DT_CLK(NULL, "func_128m_clk", "func_128m_clk"), |
| 93 | DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"), |
| 94 | DT_CLK(NULL, "func_24m_clk", "func_24m_clk"), |
| 95 | DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"), |
| 96 | DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"), |
| 97 | DT_CLK(NULL, "l3_iclk_div", "l3_iclk_div"), |
| 98 | DT_CLK(NULL, "gpu_l3_iclk", "gpu_l3_iclk"), |
| 99 | DT_CLK(NULL, "l3init_60m_fclk", "l3init_60m_fclk"), |
| 100 | DT_CLK(NULL, "wkupaon_iclk_mux", "wkupaon_iclk_mux"), |
| 101 | DT_CLK(NULL, "l3instr_ts_gclk_div", "l3instr_ts_gclk_div"), |
| 102 | DT_CLK(NULL, "l4_root_clk_div", "l4_root_clk_div"), |
| 103 | DT_CLK(NULL, "dss_32khz_clk", "dss_32khz_clk"), |
| 104 | DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"), |
| 105 | DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"), |
| 106 | DT_CLK(NULL, "dss_sys_clk", "dss_sys_clk"), |
| 107 | DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), |
| 108 | DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"), |
| 109 | DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"), |
| 110 | DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"), |
| 111 | DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"), |
| 112 | DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"), |
| 113 | DT_CLK(NULL, "gpio7_dbclk", "gpio7_dbclk"), |
| 114 | DT_CLK(NULL, "gpio8_dbclk", "gpio8_dbclk"), |
| 115 | DT_CLK(NULL, "iss_ctrlclk", "iss_ctrlclk"), |
| 116 | DT_CLK(NULL, "lli_txphy_clk", "lli_txphy_clk"), |
| 117 | DT_CLK(NULL, "lli_txphy_ls_clk", "lli_txphy_ls_clk"), |
| 118 | DT_CLK(NULL, "mmc1_32khz_clk", "mmc1_32khz_clk"), |
| 119 | DT_CLK(NULL, "sata_ref_clk", "sata_ref_clk"), |
| 120 | DT_CLK(NULL, "slimbus1_slimbus_clk", "slimbus1_slimbus_clk"), |
| 121 | DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "usb_host_hs_hsic480m_p1_clk"), |
| 122 | DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "usb_host_hs_hsic480m_p2_clk"), |
| 123 | DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "usb_host_hs_hsic480m_p3_clk"), |
| 124 | DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "usb_host_hs_hsic60m_p1_clk"), |
| 125 | DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "usb_host_hs_hsic60m_p2_clk"), |
| 126 | DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "usb_host_hs_hsic60m_p3_clk"), |
| 127 | DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "usb_host_hs_utmi_p1_clk"), |
| 128 | DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "usb_host_hs_utmi_p2_clk"), |
| 129 | DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "usb_host_hs_utmi_p3_clk"), |
| 130 | DT_CLK(NULL, "usb_otg_ss_refclk960m", "usb_otg_ss_refclk960m"), |
| 131 | DT_CLK(NULL, "usb_phy_cm_clk32k", "usb_phy_cm_clk32k"), |
| 132 | DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "usb_tll_hs_usb_ch0_clk"), |
| 133 | DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "usb_tll_hs_usb_ch1_clk"), |
| 134 | DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "usb_tll_hs_usb_ch2_clk"), |
| 135 | DT_CLK(NULL, "aess_fclk", "aess_fclk"), |
| 136 | DT_CLK(NULL, "dmic_sync_mux_ck", "dmic_sync_mux_ck"), |
| 137 | DT_CLK(NULL, "dmic_gfclk", "dmic_gfclk"), |
| 138 | DT_CLK(NULL, "fdif_fclk", "fdif_fclk"), |
| 139 | DT_CLK(NULL, "gpu_core_gclk_mux", "gpu_core_gclk_mux"), |
| 140 | DT_CLK(NULL, "gpu_hyd_gclk_mux", "gpu_hyd_gclk_mux"), |
| 141 | DT_CLK(NULL, "hsi_fclk", "hsi_fclk"), |
| 142 | DT_CLK(NULL, "mcasp_sync_mux_ck", "mcasp_sync_mux_ck"), |
| 143 | DT_CLK(NULL, "mcasp_gfclk", "mcasp_gfclk"), |
| 144 | DT_CLK(NULL, "mcbsp1_sync_mux_ck", "mcbsp1_sync_mux_ck"), |
| 145 | DT_CLK(NULL, "mcbsp1_gfclk", "mcbsp1_gfclk"), |
| 146 | DT_CLK(NULL, "mcbsp2_sync_mux_ck", "mcbsp2_sync_mux_ck"), |
| 147 | DT_CLK(NULL, "mcbsp2_gfclk", "mcbsp2_gfclk"), |
| 148 | DT_CLK(NULL, "mcbsp3_sync_mux_ck", "mcbsp3_sync_mux_ck"), |
| 149 | DT_CLK(NULL, "mcbsp3_gfclk", "mcbsp3_gfclk"), |
| 150 | DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"), |
| 151 | DT_CLK(NULL, "mmc1_fclk", "mmc1_fclk"), |
| 152 | DT_CLK(NULL, "mmc2_fclk_mux", "mmc2_fclk_mux"), |
| 153 | DT_CLK(NULL, "mmc2_fclk", "mmc2_fclk"), |
| 154 | DT_CLK(NULL, "timer10_gfclk_mux", "timer10_gfclk_mux"), |
| 155 | DT_CLK(NULL, "timer11_gfclk_mux", "timer11_gfclk_mux"), |
| 156 | DT_CLK(NULL, "timer1_gfclk_mux", "timer1_gfclk_mux"), |
| 157 | DT_CLK(NULL, "timer2_gfclk_mux", "timer2_gfclk_mux"), |
| 158 | DT_CLK(NULL, "timer3_gfclk_mux", "timer3_gfclk_mux"), |
| 159 | DT_CLK(NULL, "timer4_gfclk_mux", "timer4_gfclk_mux"), |
| 160 | DT_CLK(NULL, "timer5_gfclk_mux", "timer5_gfclk_mux"), |
| 161 | DT_CLK(NULL, "timer6_gfclk_mux", "timer6_gfclk_mux"), |
| 162 | DT_CLK(NULL, "timer7_gfclk_mux", "timer7_gfclk_mux"), |
| 163 | DT_CLK(NULL, "timer8_gfclk_mux", "timer8_gfclk_mux"), |
| 164 | DT_CLK(NULL, "timer9_gfclk_mux", "timer9_gfclk_mux"), |
| 165 | DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"), |
| 166 | DT_CLK(NULL, "utmi_p2_gfclk", "utmi_p2_gfclk"), |
| 167 | DT_CLK(NULL, "auxclk0_src_ck", "auxclk0_src_ck"), |
| 168 | DT_CLK(NULL, "auxclk0_ck", "auxclk0_ck"), |
| 169 | DT_CLK(NULL, "auxclkreq0_ck", "auxclkreq0_ck"), |
| 170 | DT_CLK(NULL, "auxclk1_src_ck", "auxclk1_src_ck"), |
| 171 | DT_CLK(NULL, "auxclk1_ck", "auxclk1_ck"), |
| 172 | DT_CLK(NULL, "auxclkreq1_ck", "auxclkreq1_ck"), |
| 173 | DT_CLK(NULL, "auxclk2_src_ck", "auxclk2_src_ck"), |
| 174 | DT_CLK(NULL, "auxclk2_ck", "auxclk2_ck"), |
| 175 | DT_CLK(NULL, "auxclkreq2_ck", "auxclkreq2_ck"), |
| 176 | DT_CLK(NULL, "auxclk3_src_ck", "auxclk3_src_ck"), |
| 177 | DT_CLK(NULL, "auxclk3_ck", "auxclk3_ck"), |
| 178 | DT_CLK(NULL, "auxclkreq3_ck", "auxclkreq3_ck"), |
| 179 | DT_CLK(NULL, "gpmc_ck", "dummy_ck"), |
| 180 | DT_CLK("omap_i2c.1", "ick", "dummy_ck"), |
| 181 | DT_CLK("omap_i2c.2", "ick", "dummy_ck"), |
| 182 | DT_CLK("omap_i2c.3", "ick", "dummy_ck"), |
| 183 | DT_CLK("omap_i2c.4", "ick", "dummy_ck"), |
| 184 | DT_CLK(NULL, "mailboxes_ick", "dummy_ck"), |
| 185 | DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"), |
| 186 | DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"), |
| 187 | DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"), |
| 188 | DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"), |
| 189 | DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"), |
| 190 | DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"), |
| 191 | DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"), |
| 192 | DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"), |
| 193 | DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"), |
| 194 | DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"), |
| 195 | DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"), |
| 196 | DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"), |
| 197 | DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"), |
| 198 | DT_CLK(NULL, "uart1_ick", "dummy_ck"), |
| 199 | DT_CLK(NULL, "uart2_ick", "dummy_ck"), |
| 200 | DT_CLK(NULL, "uart3_ick", "dummy_ck"), |
| 201 | DT_CLK(NULL, "uart4_ick", "dummy_ck"), |
| 202 | DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"), |
| 203 | DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"), |
| 204 | DT_CLK("omap_wdt", "ick", "dummy_ck"), |
| 205 | DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), |
| 206 | DT_CLK("omap_timer.1", "sys_ck", "sys_clkin"), |
| 207 | DT_CLK("omap_timer.2", "sys_ck", "sys_clkin"), |
| 208 | DT_CLK("omap_timer.3", "sys_ck", "sys_clkin"), |
| 209 | DT_CLK("omap_timer.4", "sys_ck", "sys_clkin"), |
| 210 | DT_CLK("omap_timer.9", "sys_ck", "sys_clkin"), |
| 211 | DT_CLK("omap_timer.10", "sys_ck", "sys_clkin"), |
| 212 | DT_CLK("omap_timer.11", "sys_ck", "sys_clkin"), |
| 213 | DT_CLK("omap_timer.5", "sys_ck", "dss_syc_gfclk_div"), |
| 214 | DT_CLK("omap_timer.6", "sys_ck", "dss_syc_gfclk_div"), |
| 215 | DT_CLK("omap_timer.7", "sys_ck", "dss_syc_gfclk_div"), |
| 216 | DT_CLK("omap_timer.8", "sys_ck", "dss_syc_gfclk_div"), |
| 217 | { .node_name = NULL }, |
| 218 | }; |
| 219 | |
| 220 | int __init omap5xxx_dt_clk_init(void) |
| 221 | { |
| 222 | int rc; |
| 223 | struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck; |
| 224 | |
| 225 | ti_dt_clocks_register(omap54xx_clks); |
| 226 | |
| 227 | omap2_clk_disable_autoidle_all(); |
| 228 | |
| 229 | abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux"); |
| 230 | sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck"); |
| 231 | rc = clk_set_parent(abe_dpll_ref, sys_32k_ck); |
| 232 | abe_dpll = clk_get_sys(NULL, "dpll_abe_ck"); |
| 233 | if (!rc) |
| 234 | rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ); |
| 235 | if (rc) |
| 236 | pr_err("%s: failed to configure ABE DPLL!\n", __func__); |
| 237 | |
| 238 | return 0; |
| 239 | } |