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Graf Yang5be36d22008-04-25 03:09:15 +08001/*
Robin Getz96f10502009-09-24 14:11:24 +00002 * Copyright 2007-2009 Analog Devices Inc.
Graf Yang5be36d22008-04-25 03:09:15 +08003 *
Robin Getz96f10502009-09-24 14:11:24 +00004 * Licensed under the GPL-2 or later.
Graf Yang5be36d22008-04-25 03:09:15 +08005 */
6
Roy Huang088eec12007-06-21 11:34:16 +08007#include <asm/dma.h>
Michael Hennerichb99ab542007-10-11 10:57:54 +08008#include <asm/portmux.h>
Roy Huang088eec12007-06-21 11:34:16 +08009
Sonic Zhangd307d362009-04-07 16:52:26 +010010#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) || \
11 defined(CONFIG_BFIN_UART2_CTSRTS) || defined(CONFIG_BFIN_UART3_CTSRTS)
12# define CONFIG_SERIAL_BFIN_HARD_CTSRTS
Roy Huang088eec12007-06-21 11:34:16 +080013#endif
Graf Yangb3ef5ab2008-10-13 10:33:42 +010014
Roy Huang088eec12007-06-21 11:34:16 +080015struct bfin_serial_res {
16 unsigned long uart_base_addr;
17 int uart_irq;
Sonic Zhangd307d362009-04-07 16:52:26 +010018 int uart_status_irq;
Roy Huang088eec12007-06-21 11:34:16 +080019#ifdef CONFIG_SERIAL_BFIN_DMA
20 unsigned int uart_tx_dma_channel;
21 unsigned int uart_rx_dma_channel;
22#endif
Sonic Zhangd307d362009-04-07 16:52:26 +010023#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
24 int uart_cts_pin;
25 int uart_rts_pin;
Roy Huang088eec12007-06-21 11:34:16 +080026#endif
27};
28
29struct bfin_serial_res bfin_serial_resource[] = {
30#ifdef CONFIG_SERIAL_BFIN_UART0
31 {
32 0xFFC00400,
33 IRQ_UART0_RX,
Sonic Zhangd307d362009-04-07 16:52:26 +010034 IRQ_UART0_ERROR,
Roy Huang088eec12007-06-21 11:34:16 +080035#ifdef CONFIG_SERIAL_BFIN_DMA
36 CH_UART0_TX,
37 CH_UART0_RX,
38#endif
Sonic Zhangd307d362009-04-07 16:52:26 +010039#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
40 0,
41 0,
Roy Huang088eec12007-06-21 11:34:16 +080042#endif
43 },
44#endif
45#ifdef CONFIG_SERIAL_BFIN_UART1
46 {
47 0xFFC02000,
48 IRQ_UART1_RX,
Sonic Zhangd307d362009-04-07 16:52:26 +010049 IRQ_UART1_ERROR,
Roy Huang088eec12007-06-21 11:34:16 +080050#ifdef CONFIG_SERIAL_BFIN_DMA
51 CH_UART1_TX,
52 CH_UART1_RX,
53#endif
Sonic Zhangd307d362009-04-07 16:52:26 +010054#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
55 GPIO_PE10,
56 GPIO_PE9,
Tom Parker97d4b352009-03-03 17:59:39 +080057#endif
Roy Huang24a07a12007-07-12 22:41:45 +080058 },
59#endif
60#ifdef CONFIG_SERIAL_BFIN_UART2
61 {
62 0xFFC02100,
63 IRQ_UART2_RX,
Sonic Zhangd307d362009-04-07 16:52:26 +010064 IRQ_UART2_ERROR,
Roy Huang24a07a12007-07-12 22:41:45 +080065#ifdef CONFIG_SERIAL_BFIN_DMA
66 CH_UART2_TX,
67 CH_UART2_RX,
68#endif
Sonic Zhangd307d362009-04-07 16:52:26 +010069#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
70 0,
71 0,
Roy Huang24a07a12007-07-12 22:41:45 +080072#endif
73 },
74#endif
75#ifdef CONFIG_SERIAL_BFIN_UART3
76 {
77 0xFFC03100,
78 IRQ_UART3_RX,
Sonic Zhangd307d362009-04-07 16:52:26 +010079 IRQ_UART3_ERROR,
Roy Huang24a07a12007-07-12 22:41:45 +080080#ifdef CONFIG_SERIAL_BFIN_DMA
81 CH_UART3_TX,
82 CH_UART3_RX,
Roy Huang088eec12007-06-21 11:34:16 +080083#endif
Sonic Zhangd307d362009-04-07 16:52:26 +010084#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
85 GPIO_PB3,
86 GPIO_PB2,
Tom Parker97d4b352009-03-03 17:59:39 +080087#endif
Roy Huang088eec12007-06-21 11:34:16 +080088 },
89#endif
90};
91
Michael Hennerichb99ab542007-10-11 10:57:54 +080092#define DRIVER_NAME "bfin-uart"
Mike Frysingerb1524e22009-09-28 03:16:01 +000093
94#include <asm/bfin_serial.h>