Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 1 | /* |
Robin Getz | 96f1050 | 2009-09-24 14:11:24 +0000 | [diff] [blame] | 2 | * Copyright 2007-2009 Analog Devices Inc. |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 3 | * |
Robin Getz | 96f1050 | 2009-09-24 14:11:24 +0000 | [diff] [blame] | 4 | * Licensed under the GPL-2 or later. |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _BF548_IRQ_H_ |
| 8 | #define _BF548_IRQ_H_ |
| 9 | |
| 10 | /* |
| 11 | * Interrupt source definitions |
| 12 | Event Source Core Event Name |
| 13 | Core Emulation ** |
| 14 | Events (highest priority) EMU 0 |
| 15 | Reset RST 1 |
| 16 | NMI NMI 2 |
| 17 | Exception EVX 3 |
| 18 | Reserved -- 4 |
| 19 | Hardware Error IVHW 5 |
| 20 | Core Timer IVTMR 6 * |
| 21 | |
| 22 | ..... |
| 23 | |
| 24 | Software Interrupt 1 IVG14 31 |
| 25 | Software Interrupt 2 -- |
| 26 | (lowest priority) IVG15 32 * |
| 27 | */ |
| 28 | |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 29 | #define NR_PERI_INTS (32 * 3) |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 30 | |
| 31 | /* The ABSTRACT IRQ definitions */ |
| 32 | /** the first seven of the following are fixed, the rest you change if you need to **/ |
Michael Hennerich | 55249e9 | 2007-10-11 00:06:31 +0800 | [diff] [blame] | 33 | #define IRQ_EMU 0 /* Emulation */ |
| 34 | #define IRQ_RST 1 /* reset */ |
| 35 | #define IRQ_NMI 2 /* Non Maskable */ |
| 36 | #define IRQ_EVX 3 /* Exception */ |
| 37 | #define IRQ_UNUSED 4 /* - unused interrupt*/ |
| 38 | #define IRQ_HWERR 5 /* Hardware Error */ |
| 39 | #define IRQ_CORETMR 6 /* Core timer */ |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 40 | |
Michael Hennerich | 55249e9 | 2007-10-11 00:06:31 +0800 | [diff] [blame] | 41 | #define BFIN_IRQ(x) ((x) + 7) |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 42 | |
Michael Hennerich | 55249e9 | 2007-10-11 00:06:31 +0800 | [diff] [blame] | 43 | #define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ |
| 44 | #define IRQ_DMAC0_ERROR BFIN_IRQ(1) /* DMAC0 Status Interrupt */ |
| 45 | #define IRQ_EPPI0_ERROR BFIN_IRQ(2) /* EPPI0 Error Interrupt */ |
| 46 | #define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Error Interrupt */ |
| 47 | #define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Error Interrupt */ |
| 48 | #define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status(Error) Interrupt */ |
| 49 | #define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status(Error) Interrupt */ |
| 50 | #define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */ |
| 51 | #define IRQ_EPPI0 BFIN_IRQ(8) /* EPPI0 Interrupt (DMA12) */ |
| 52 | #define IRQ_SPORT0_RX BFIN_IRQ(9) /* SPORT0 RX Interrupt (DMA0) */ |
| 53 | #define IRQ_SPORT0_TX BFIN_IRQ(10) /* SPORT0 TX Interrupt (DMA1) */ |
| 54 | #define IRQ_SPORT1_RX BFIN_IRQ(11) /* SPORT1 RX Interrupt (DMA2) */ |
| 55 | #define IRQ_SPORT1_TX BFIN_IRQ(12) /* SPORT1 TX Interrupt (DMA3) */ |
| 56 | #define IRQ_SPI0 BFIN_IRQ(13) /* SPI0 Interrupt (DMA4) */ |
| 57 | #define IRQ_UART0_RX BFIN_IRQ(14) /* UART0 RX Interrupt (DMA6) */ |
| 58 | #define IRQ_UART0_TX BFIN_IRQ(15) /* UART0 TX Interrupt (DMA7) */ |
| 59 | #define IRQ_TIMER8 BFIN_IRQ(16) /* TIMER 8 Interrupt */ |
| 60 | #define IRQ_TIMER9 BFIN_IRQ(17) /* TIMER 9 Interrupt */ |
| 61 | #define IRQ_TIMER10 BFIN_IRQ(18) /* TIMER 10 Interrupt */ |
| 62 | #define IRQ_PINT0 BFIN_IRQ(19) /* PINT0 Interrupt */ |
| 63 | #define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */ |
| 64 | #define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */ |
| 65 | #define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */ |
Sonic Zhang | fb5f004 | 2007-12-23 23:02:13 +0800 | [diff] [blame] | 66 | #define IRQ_WATCH BFIN_IRQ(23) /* Watchdog Interrupt */ |
Michael Hennerich | 55249e9 | 2007-10-11 00:06:31 +0800 | [diff] [blame] | 67 | #define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */ |
| 68 | #define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */ |
| 69 | #define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */ |
| 70 | #define IRQ_MXVR_DATA BFIN_IRQ(27) /* MXVR Data Interrupt */ |
| 71 | #define IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */ |
| 72 | #define IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */ |
| 73 | #define IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */ |
| 74 | #define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */ |
| 75 | #define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */ |
| 76 | #define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */ |
| 77 | #define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */ |
| 78 | #define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */ |
| 79 | #define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */ |
| 80 | #define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */ |
| 81 | #define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */ |
| 82 | #define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */ |
| 83 | #define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */ |
| 84 | #define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */ |
| 85 | #define IRQ_UART1_TX BFIN_IRQ(42) /* UART1 TX (DMA9) Interrupt */ |
| 86 | #define IRQ_ATAPI_RX BFIN_IRQ(43) /* ATAPI RX (DMA10) Interrupt */ |
| 87 | #define IRQ_ATAPI_TX BFIN_IRQ(44) /* ATAPI TX (DMA11) Interrupt */ |
| 88 | #define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 Interrupt */ |
| 89 | #define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 Interrupt */ |
| 90 | #define IRQ_CAN0_RX BFIN_IRQ(47) /* CAN0 Receive Interrupt */ |
| 91 | #define IRQ_CAN0_TX BFIN_IRQ(48) /* CAN0 Transmit Interrupt */ |
| 92 | #define IRQ_MDMAS2 BFIN_IRQ(49) /* MDMA Stream 2 Interrupt */ |
| 93 | #define IRQ_MDMAS3 BFIN_IRQ(50) /* MDMA Stream 3 Interrupt */ |
| 94 | #define IRQ_MXVR_ERROR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */ |
| 95 | #define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */ |
| 96 | #define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */ |
Michael Hennerich | 0f29456 | 2009-03-02 18:06:13 +0800 | [diff] [blame] | 97 | #define IRQ_EPPI1_ERROR BFIN_IRQ(54) /* EPPI1 Error Interrupt */ |
| 98 | #define IRQ_EPPI2_ERROR BFIN_IRQ(55) /* EPPI2 Error Interrupt */ |
Michael Hennerich | 55249e9 | 2007-10-11 00:06:31 +0800 | [diff] [blame] | 99 | #define IRQ_UART3_ERROR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */ |
| 100 | #define IRQ_HOST_ERROR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */ |
| 101 | #define IRQ_PIXC_ERROR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */ |
| 102 | #define IRQ_NFC_ERROR BFIN_IRQ(60) /* NFC Error Interrupt */ |
| 103 | #define IRQ_ATAPI_ERROR BFIN_IRQ(61) /* ATAPI Error Interrupt */ |
| 104 | #define IRQ_CAN1_ERROR BFIN_IRQ(62) /* CAN1 Status (Error) Interrupt */ |
| 105 | #define IRQ_HS_DMA_ERROR BFIN_IRQ(63) /* Handshake DMA Status Interrupt */ |
| 106 | #define IRQ_PIXC_IN0 BFIN_IRQ(64) /* PIXC IN0 (DMA15) Interrupt */ |
| 107 | #define IRQ_PIXC_IN1 BFIN_IRQ(65) /* PIXC IN1 (DMA16) Interrupt */ |
| 108 | #define IRQ_PIXC_OUT BFIN_IRQ(66) /* PIXC OUT (DMA17) Interrupt */ |
| 109 | #define IRQ_SDH BFIN_IRQ(67) /* SDH/NFC (DMA22) Interrupt */ |
| 110 | #define IRQ_CNT BFIN_IRQ(68) /* CNT Interrupt */ |
| 111 | #define IRQ_KEY BFIN_IRQ(69) /* KEY Interrupt */ |
| 112 | #define IRQ_CAN1_RX BFIN_IRQ(70) /* CAN1 RX Interrupt */ |
| 113 | #define IRQ_CAN1_TX BFIN_IRQ(71) /* CAN1 TX Interrupt */ |
| 114 | #define IRQ_SDH_MASK0 BFIN_IRQ(72) /* SDH Mask 0 Interrupt */ |
| 115 | #define IRQ_SDH_MASK1 BFIN_IRQ(73) /* SDH Mask 1 Interrupt */ |
| 116 | #define IRQ_USB_INT0 BFIN_IRQ(75) /* USB INT0 Interrupt */ |
| 117 | #define IRQ_USB_INT1 BFIN_IRQ(76) /* USB INT1 Interrupt */ |
| 118 | #define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */ |
| 119 | #define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */ |
| 120 | #define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */ |
| 121 | #define IRQ_TIMER0 BFIN_IRQ(86) /* Timer 0 Interrupt */ |
| 122 | #define IRQ_TIMER1 BFIN_IRQ(87) /* Timer 1 Interrupt */ |
| 123 | #define IRQ_TIMER2 BFIN_IRQ(88) /* Timer 2 Interrupt */ |
| 124 | #define IRQ_TIMER3 BFIN_IRQ(89) /* Timer 3 Interrupt */ |
| 125 | #define IRQ_TIMER4 BFIN_IRQ(90) /* Timer 4 Interrupt */ |
| 126 | #define IRQ_TIMER5 BFIN_IRQ(91) /* Timer 5 Interrupt */ |
| 127 | #define IRQ_TIMER6 BFIN_IRQ(92) /* Timer 6 Interrupt */ |
| 128 | #define IRQ_TIMER7 BFIN_IRQ(93) /* Timer 7 Interrupt */ |
| 129 | #define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */ |
| 130 | #define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */ |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 131 | |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 132 | #define SYS_IRQS IRQ_PINT3 |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 133 | |
Michael Hennerich | 55249e9 | 2007-10-11 00:06:31 +0800 | [diff] [blame] | 134 | #define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1) |
| 135 | #define IRQ_PA0 BFIN_PA_IRQ(0) |
| 136 | #define IRQ_PA1 BFIN_PA_IRQ(1) |
| 137 | #define IRQ_PA2 BFIN_PA_IRQ(2) |
| 138 | #define IRQ_PA3 BFIN_PA_IRQ(3) |
| 139 | #define IRQ_PA4 BFIN_PA_IRQ(4) |
| 140 | #define IRQ_PA5 BFIN_PA_IRQ(5) |
| 141 | #define IRQ_PA6 BFIN_PA_IRQ(6) |
| 142 | #define IRQ_PA7 BFIN_PA_IRQ(7) |
| 143 | #define IRQ_PA8 BFIN_PA_IRQ(8) |
| 144 | #define IRQ_PA9 BFIN_PA_IRQ(9) |
| 145 | #define IRQ_PA10 BFIN_PA_IRQ(10) |
| 146 | #define IRQ_PA11 BFIN_PA_IRQ(11) |
| 147 | #define IRQ_PA12 BFIN_PA_IRQ(12) |
| 148 | #define IRQ_PA13 BFIN_PA_IRQ(13) |
| 149 | #define IRQ_PA14 BFIN_PA_IRQ(14) |
| 150 | #define IRQ_PA15 BFIN_PA_IRQ(15) |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 151 | |
Michael Hennerich | 55249e9 | 2007-10-11 00:06:31 +0800 | [diff] [blame] | 152 | #define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1) |
| 153 | #define IRQ_PB0 BFIN_PB_IRQ(0) |
| 154 | #define IRQ_PB1 BFIN_PB_IRQ(1) |
| 155 | #define IRQ_PB2 BFIN_PB_IRQ(2) |
| 156 | #define IRQ_PB3 BFIN_PB_IRQ(3) |
| 157 | #define IRQ_PB4 BFIN_PB_IRQ(4) |
| 158 | #define IRQ_PB5 BFIN_PB_IRQ(5) |
| 159 | #define IRQ_PB6 BFIN_PB_IRQ(6) |
| 160 | #define IRQ_PB7 BFIN_PB_IRQ(7) |
| 161 | #define IRQ_PB8 BFIN_PB_IRQ(8) |
| 162 | #define IRQ_PB9 BFIN_PB_IRQ(9) |
| 163 | #define IRQ_PB10 BFIN_PB_IRQ(10) |
| 164 | #define IRQ_PB11 BFIN_PB_IRQ(11) |
| 165 | #define IRQ_PB12 BFIN_PB_IRQ(12) |
| 166 | #define IRQ_PB13 BFIN_PB_IRQ(13) |
| 167 | #define IRQ_PB14 BFIN_PB_IRQ(14) |
| 168 | #define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */ |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 169 | |
Michael Hennerich | 55249e9 | 2007-10-11 00:06:31 +0800 | [diff] [blame] | 170 | #define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1) |
| 171 | #define IRQ_PC0 BFIN_PC_IRQ(0) |
| 172 | #define IRQ_PC1 BFIN_PC_IRQ(1) |
| 173 | #define IRQ_PC2 BFIN_PC_IRQ(2) |
| 174 | #define IRQ_PC3 BFIN_PC_IRQ(3) |
| 175 | #define IRQ_PC4 BFIN_PC_IRQ(4) |
| 176 | #define IRQ_PC5 BFIN_PC_IRQ(5) |
| 177 | #define IRQ_PC6 BFIN_PC_IRQ(6) |
| 178 | #define IRQ_PC7 BFIN_PC_IRQ(7) |
| 179 | #define IRQ_PC8 BFIN_PC_IRQ(8) |
| 180 | #define IRQ_PC9 BFIN_PC_IRQ(9) |
| 181 | #define IRQ_PC10 BFIN_PC_IRQ(10) |
| 182 | #define IRQ_PC11 BFIN_PC_IRQ(11) |
| 183 | #define IRQ_PC12 BFIN_PC_IRQ(12) |
| 184 | #define IRQ_PC13 BFIN_PC_IRQ(13) |
| 185 | #define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */ |
| 186 | #define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */ |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 187 | |
Michael Hennerich | 55249e9 | 2007-10-11 00:06:31 +0800 | [diff] [blame] | 188 | #define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1) |
| 189 | #define IRQ_PD0 BFIN_PD_IRQ(0) |
| 190 | #define IRQ_PD1 BFIN_PD_IRQ(1) |
| 191 | #define IRQ_PD2 BFIN_PD_IRQ(2) |
| 192 | #define IRQ_PD3 BFIN_PD_IRQ(3) |
| 193 | #define IRQ_PD4 BFIN_PD_IRQ(4) |
| 194 | #define IRQ_PD5 BFIN_PD_IRQ(5) |
| 195 | #define IRQ_PD6 BFIN_PD_IRQ(6) |
| 196 | #define IRQ_PD7 BFIN_PD_IRQ(7) |
| 197 | #define IRQ_PD8 BFIN_PD_IRQ(8) |
| 198 | #define IRQ_PD9 BFIN_PD_IRQ(9) |
| 199 | #define IRQ_PD10 BFIN_PD_IRQ(10) |
| 200 | #define IRQ_PD11 BFIN_PD_IRQ(11) |
| 201 | #define IRQ_PD12 BFIN_PD_IRQ(12) |
| 202 | #define IRQ_PD13 BFIN_PD_IRQ(13) |
| 203 | #define IRQ_PD14 BFIN_PD_IRQ(14) |
| 204 | #define IRQ_PD15 BFIN_PD_IRQ(15) |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 205 | |
Michael Hennerich | 55249e9 | 2007-10-11 00:06:31 +0800 | [diff] [blame] | 206 | #define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1) |
| 207 | #define IRQ_PE0 BFIN_PE_IRQ(0) |
| 208 | #define IRQ_PE1 BFIN_PE_IRQ(1) |
| 209 | #define IRQ_PE2 BFIN_PE_IRQ(2) |
| 210 | #define IRQ_PE3 BFIN_PE_IRQ(3) |
| 211 | #define IRQ_PE4 BFIN_PE_IRQ(4) |
| 212 | #define IRQ_PE5 BFIN_PE_IRQ(5) |
| 213 | #define IRQ_PE6 BFIN_PE_IRQ(6) |
| 214 | #define IRQ_PE7 BFIN_PE_IRQ(7) |
| 215 | #define IRQ_PE8 BFIN_PE_IRQ(8) |
| 216 | #define IRQ_PE9 BFIN_PE_IRQ(9) |
| 217 | #define IRQ_PE10 BFIN_PE_IRQ(10) |
| 218 | #define IRQ_PE11 BFIN_PE_IRQ(11) |
| 219 | #define IRQ_PE12 BFIN_PE_IRQ(12) |
| 220 | #define IRQ_PE13 BFIN_PE_IRQ(13) |
| 221 | #define IRQ_PE14 BFIN_PE_IRQ(14) |
| 222 | #define IRQ_PE15 BFIN_PE_IRQ(15) |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 223 | |
Michael Hennerich | 55249e9 | 2007-10-11 00:06:31 +0800 | [diff] [blame] | 224 | #define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1) |
| 225 | #define IRQ_PF0 BFIN_PF_IRQ(0) |
| 226 | #define IRQ_PF1 BFIN_PF_IRQ(1) |
| 227 | #define IRQ_PF2 BFIN_PF_IRQ(2) |
| 228 | #define IRQ_PF3 BFIN_PF_IRQ(3) |
| 229 | #define IRQ_PF4 BFIN_PF_IRQ(4) |
| 230 | #define IRQ_PF5 BFIN_PF_IRQ(5) |
| 231 | #define IRQ_PF6 BFIN_PF_IRQ(6) |
| 232 | #define IRQ_PF7 BFIN_PF_IRQ(7) |
| 233 | #define IRQ_PF8 BFIN_PF_IRQ(8) |
| 234 | #define IRQ_PF9 BFIN_PF_IRQ(9) |
| 235 | #define IRQ_PF10 BFIN_PF_IRQ(10) |
| 236 | #define IRQ_PF11 BFIN_PF_IRQ(11) |
| 237 | #define IRQ_PF12 BFIN_PF_IRQ(12) |
| 238 | #define IRQ_PF13 BFIN_PF_IRQ(13) |
| 239 | #define IRQ_PF14 BFIN_PF_IRQ(14) |
| 240 | #define IRQ_PF15 BFIN_PF_IRQ(15) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 241 | |
Michael Hennerich | 55249e9 | 2007-10-11 00:06:31 +0800 | [diff] [blame] | 242 | #define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1) |
| 243 | #define IRQ_PG0 BFIN_PG_IRQ(0) |
| 244 | #define IRQ_PG1 BFIN_PG_IRQ(1) |
| 245 | #define IRQ_PG2 BFIN_PG_IRQ(2) |
| 246 | #define IRQ_PG3 BFIN_PG_IRQ(3) |
| 247 | #define IRQ_PG4 BFIN_PG_IRQ(4) |
| 248 | #define IRQ_PG5 BFIN_PG_IRQ(5) |
| 249 | #define IRQ_PG6 BFIN_PG_IRQ(6) |
| 250 | #define IRQ_PG7 BFIN_PG_IRQ(7) |
| 251 | #define IRQ_PG8 BFIN_PG_IRQ(8) |
| 252 | #define IRQ_PG9 BFIN_PG_IRQ(9) |
| 253 | #define IRQ_PG10 BFIN_PG_IRQ(10) |
| 254 | #define IRQ_PG11 BFIN_PG_IRQ(11) |
| 255 | #define IRQ_PG12 BFIN_PG_IRQ(12) |
| 256 | #define IRQ_PG13 BFIN_PG_IRQ(13) |
| 257 | #define IRQ_PG14 BFIN_PG_IRQ(14) |
| 258 | #define IRQ_PG15 BFIN_PG_IRQ(15) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 259 | |
Michael Hennerich | 55249e9 | 2007-10-11 00:06:31 +0800 | [diff] [blame] | 260 | #define BFIN_PH_IRQ(x) ((x) + IRQ_PG15 + 1) |
| 261 | #define IRQ_PH0 BFIN_PH_IRQ(0) |
| 262 | #define IRQ_PH1 BFIN_PH_IRQ(1) |
| 263 | #define IRQ_PH2 BFIN_PH_IRQ(2) |
| 264 | #define IRQ_PH3 BFIN_PH_IRQ(3) |
| 265 | #define IRQ_PH4 BFIN_PH_IRQ(4) |
| 266 | #define IRQ_PH5 BFIN_PH_IRQ(5) |
| 267 | #define IRQ_PH6 BFIN_PH_IRQ(6) |
| 268 | #define IRQ_PH7 BFIN_PH_IRQ(7) |
| 269 | #define IRQ_PH8 BFIN_PH_IRQ(8) |
| 270 | #define IRQ_PH9 BFIN_PH_IRQ(9) |
| 271 | #define IRQ_PH10 BFIN_PH_IRQ(10) |
| 272 | #define IRQ_PH11 BFIN_PH_IRQ(11) |
| 273 | #define IRQ_PH12 BFIN_PH_IRQ(12) |
| 274 | #define IRQ_PH13 BFIN_PH_IRQ(13) |
| 275 | #define IRQ_PH14 BFIN_PH_IRQ(14) /* N/A */ |
| 276 | #define IRQ_PH15 BFIN_PH_IRQ(15) /* N/A */ |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 277 | |
Michael Hennerich | 55249e9 | 2007-10-11 00:06:31 +0800 | [diff] [blame] | 278 | #define BFIN_PI_IRQ(x) ((x) + IRQ_PH15 + 1) |
| 279 | #define IRQ_PI0 BFIN_PI_IRQ(0) |
| 280 | #define IRQ_PI1 BFIN_PI_IRQ(1) |
| 281 | #define IRQ_PI2 BFIN_PI_IRQ(2) |
| 282 | #define IRQ_PI3 BFIN_PI_IRQ(3) |
| 283 | #define IRQ_PI4 BFIN_PI_IRQ(4) |
| 284 | #define IRQ_PI5 BFIN_PI_IRQ(5) |
| 285 | #define IRQ_PI6 BFIN_PI_IRQ(6) |
| 286 | #define IRQ_PI7 BFIN_PI_IRQ(7) |
| 287 | #define IRQ_PI8 BFIN_PI_IRQ(8) |
| 288 | #define IRQ_PI9 BFIN_PI_IRQ(9) |
| 289 | #define IRQ_PI10 BFIN_PI_IRQ(10) |
| 290 | #define IRQ_PI11 BFIN_PI_IRQ(11) |
| 291 | #define IRQ_PI12 BFIN_PI_IRQ(12) |
| 292 | #define IRQ_PI13 BFIN_PI_IRQ(13) |
| 293 | #define IRQ_PI14 BFIN_PI_IRQ(14) |
| 294 | #define IRQ_PI15 BFIN_PI_IRQ(15) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 295 | |
Michael Hennerich | 55249e9 | 2007-10-11 00:06:31 +0800 | [diff] [blame] | 296 | #define BFIN_PJ_IRQ(x) ((x) + IRQ_PI15 + 1) |
| 297 | #define IRQ_PJ0 BFIN_PJ_IRQ(0) |
| 298 | #define IRQ_PJ1 BFIN_PJ_IRQ(1) |
| 299 | #define IRQ_PJ2 BFIN_PJ_IRQ(2) |
| 300 | #define IRQ_PJ3 BFIN_PJ_IRQ(3) |
| 301 | #define IRQ_PJ4 BFIN_PJ_IRQ(4) |
| 302 | #define IRQ_PJ5 BFIN_PJ_IRQ(5) |
| 303 | #define IRQ_PJ6 BFIN_PJ_IRQ(6) |
| 304 | #define IRQ_PJ7 BFIN_PJ_IRQ(7) |
| 305 | #define IRQ_PJ8 BFIN_PJ_IRQ(8) |
| 306 | #define IRQ_PJ9 BFIN_PJ_IRQ(9) |
| 307 | #define IRQ_PJ10 BFIN_PJ_IRQ(10) |
| 308 | #define IRQ_PJ11 BFIN_PJ_IRQ(11) |
| 309 | #define IRQ_PJ12 BFIN_PJ_IRQ(12) |
| 310 | #define IRQ_PJ13 BFIN_PJ_IRQ(13) |
| 311 | #define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */ |
| 312 | #define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */ |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 313 | |
Michael Hennerich | 301af29 | 2007-07-24 15:35:53 +0800 | [diff] [blame] | 314 | #define GPIO_IRQ_BASE IRQ_PA0 |
| 315 | |
Michael Hennerich | f3dec78 | 2010-01-19 14:45:38 +0000 | [diff] [blame] | 316 | #define NR_MACH_IRQS (IRQ_PJ15 + 1) |
| 317 | #define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS) |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 318 | |
Michael Hennerich | 55249e9 | 2007-10-11 00:06:31 +0800 | [diff] [blame] | 319 | /* For compatibility reasons with existing code */ |
| 320 | |
| 321 | #define IRQ_DMAC0_ERR IRQ_DMAC0_ERROR |
| 322 | #define IRQ_EPPI0_ERR IRQ_EPPI0_ERROR |
| 323 | #define IRQ_SPORT0_ERR IRQ_SPORT0_ERROR |
| 324 | #define IRQ_SPORT1_ERR IRQ_SPORT1_ERROR |
| 325 | #define IRQ_SPI0_ERR IRQ_SPI0_ERROR |
| 326 | #define IRQ_UART0_ERR IRQ_UART0_ERROR |
| 327 | #define IRQ_DMAC1_ERR IRQ_DMAC1_ERROR |
| 328 | #define IRQ_SPORT2_ERR IRQ_SPORT2_ERROR |
| 329 | #define IRQ_SPORT3_ERR IRQ_SPORT3_ERROR |
| 330 | #define IRQ_SPI1_ERR IRQ_SPI1_ERROR |
| 331 | #define IRQ_SPI2_ERR IRQ_SPI2_ERROR |
| 332 | #define IRQ_UART1_ERR IRQ_UART1_ERROR |
| 333 | #define IRQ_UART2_ERR IRQ_UART2_ERROR |
| 334 | #define IRQ_CAN0_ERR IRQ_CAN0_ERROR |
| 335 | #define IRQ_MXVR_ERR IRQ_MXVR_ERROR |
Michael Hennerich | 0f29456 | 2009-03-02 18:06:13 +0800 | [diff] [blame] | 336 | #define IRQ_EPPI1_ERR IRQ_EPPI1_ERROR |
| 337 | #define IRQ_EPPI2_ERR IRQ_EPPI2_ERROR |
Michael Hennerich | 55249e9 | 2007-10-11 00:06:31 +0800 | [diff] [blame] | 338 | #define IRQ_UART3_ERR IRQ_UART3_ERROR |
| 339 | #define IRQ_HOST_ERR IRQ_HOST_ERROR |
| 340 | #define IRQ_PIXC_ERR IRQ_PIXC_ERROR |
| 341 | #define IRQ_NFC_ERR IRQ_NFC_ERROR |
| 342 | #define IRQ_ATAPI_ERR IRQ_ATAPI_ERROR |
| 343 | #define IRQ_CAN1_ERR IRQ_CAN1_ERROR |
| 344 | #define IRQ_HS_DMA_ERR IRQ_HS_DMA_ERROR |
| 345 | |
| 346 | |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 347 | #define IVG7 7 |
| 348 | #define IVG8 8 |
| 349 | #define IVG9 9 |
| 350 | #define IVG10 10 |
| 351 | #define IVG11 11 |
| 352 | #define IVG12 12 |
| 353 | #define IVG13 13 |
| 354 | #define IVG14 14 |
| 355 | #define IVG15 15 |
| 356 | |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 357 | /* IAR0 BIT FIELDS */ |
| 358 | #define IRQ_PLL_WAKEUP_POS 0 |
| 359 | #define IRQ_DMAC0_ERR_POS 4 |
| 360 | #define IRQ_EPPI0_ERR_POS 8 |
| 361 | #define IRQ_SPORT0_ERR_POS 12 |
| 362 | #define IRQ_SPORT1_ERR_POS 16 |
| 363 | #define IRQ_SPI0_ERR_POS 20 |
| 364 | #define IRQ_UART0_ERR_POS 24 |
| 365 | #define IRQ_RTC_POS 28 |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 366 | |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 367 | /* IAR1 BIT FIELDS */ |
| 368 | #define IRQ_EPPI0_POS 0 |
| 369 | #define IRQ_SPORT0_RX_POS 4 |
| 370 | #define IRQ_SPORT0_TX_POS 8 |
| 371 | #define IRQ_SPORT1_RX_POS 12 |
| 372 | #define IRQ_SPORT1_TX_POS 16 |
| 373 | #define IRQ_SPI0_POS 20 |
| 374 | #define IRQ_UART0_RX_POS 24 |
| 375 | #define IRQ_UART0_TX_POS 28 |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 376 | |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 377 | /* IAR2 BIT FIELDS */ |
| 378 | #define IRQ_TIMER8_POS 0 |
| 379 | #define IRQ_TIMER9_POS 4 |
| 380 | #define IRQ_TIMER10_POS 8 |
| 381 | #define IRQ_PINT0_POS 12 |
| 382 | #define IRQ_PINT1_POS 16 |
| 383 | #define IRQ_MDMAS0_POS 20 |
| 384 | #define IRQ_MDMAS1_POS 24 |
Sonic Zhang | fb5f004 | 2007-12-23 23:02:13 +0800 | [diff] [blame] | 385 | #define IRQ_WATCH_POS 28 |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 386 | |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 387 | /* IAR3 BIT FIELDS */ |
| 388 | #define IRQ_DMAC1_ERR_POS 0 |
| 389 | #define IRQ_SPORT2_ERR_POS 4 |
| 390 | #define IRQ_SPORT3_ERR_POS 8 |
| 391 | #define IRQ_MXVR_DATA_POS 12 |
| 392 | #define IRQ_SPI1_ERR_POS 16 |
| 393 | #define IRQ_SPI2_ERR_POS 20 |
| 394 | #define IRQ_UART1_ERR_POS 24 |
| 395 | #define IRQ_UART2_ERR_POS 28 |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 396 | |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 397 | /* IAR4 BIT FILEDS */ |
| 398 | #define IRQ_CAN0_ERR_POS 0 |
| 399 | #define IRQ_SPORT2_RX_POS 4 |
Sonic Zhang | 8b01eaf | 2008-02-02 16:31:00 +0800 | [diff] [blame] | 400 | #define IRQ_UART2_RX_POS 4 |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 401 | #define IRQ_SPORT2_TX_POS 8 |
Sonic Zhang | 8b01eaf | 2008-02-02 16:31:00 +0800 | [diff] [blame] | 402 | #define IRQ_UART2_TX_POS 8 |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 403 | #define IRQ_SPORT3_RX_POS 12 |
Sonic Zhang | 8b01eaf | 2008-02-02 16:31:00 +0800 | [diff] [blame] | 404 | #define IRQ_UART3_RX_POS 12 |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 405 | #define IRQ_SPORT3_TX_POS 16 |
Sonic Zhang | 8b01eaf | 2008-02-02 16:31:00 +0800 | [diff] [blame] | 406 | #define IRQ_UART3_TX_POS 16 |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 407 | #define IRQ_EPPI1_POS 20 |
| 408 | #define IRQ_EPPI2_POS 24 |
| 409 | #define IRQ_SPI1_POS 28 |
| 410 | |
| 411 | /* IAR5 BIT FIELDS */ |
| 412 | #define IRQ_SPI2_POS 0 |
| 413 | #define IRQ_UART1_RX_POS 4 |
| 414 | #define IRQ_UART1_TX_POS 8 |
| 415 | #define IRQ_ATAPI_RX_POS 12 |
| 416 | #define IRQ_ATAPI_TX_POS 16 |
| 417 | #define IRQ_TWI0_POS 20 |
| 418 | #define IRQ_TWI1_POS 24 |
| 419 | #define IRQ_CAN0_RX_POS 28 |
| 420 | |
| 421 | /* IAR6 BIT FIELDS */ |
| 422 | #define IRQ_CAN0_TX_POS 0 |
| 423 | #define IRQ_MDMAS2_POS 4 |
| 424 | #define IRQ_MDMAS3_POS 8 |
| 425 | #define IRQ_MXVR_ERR_POS 12 |
| 426 | #define IRQ_MXVR_MSG_POS 16 |
| 427 | #define IRQ_MXVR_PKT_POS 20 |
| 428 | #define IRQ_EPPI1_ERR_POS 24 |
| 429 | #define IRQ_EPPI2_ERR_POS 28 |
| 430 | |
| 431 | /* IAR7 BIT FIELDS */ |
| 432 | #define IRQ_UART3_ERR_POS 0 |
| 433 | #define IRQ_HOST_ERR_POS 4 |
| 434 | #define IRQ_PIXC_ERR_POS 12 |
| 435 | #define IRQ_NFC_ERR_POS 16 |
| 436 | #define IRQ_ATAPI_ERR_POS 20 |
| 437 | #define IRQ_CAN1_ERR_POS 24 |
| 438 | #define IRQ_HS_DMA_ERR_POS 28 |
| 439 | |
| 440 | /* IAR8 BIT FIELDS */ |
| 441 | #define IRQ_PIXC_IN0_POS 0 |
| 442 | #define IRQ_PIXC_IN1_POS 4 |
| 443 | #define IRQ_PIXC_OUT_POS 8 |
| 444 | #define IRQ_SDH_POS 12 |
| 445 | #define IRQ_CNT_POS 16 |
| 446 | #define IRQ_KEY_POS 20 |
| 447 | #define IRQ_CAN1_RX_POS 24 |
| 448 | #define IRQ_CAN1_TX_POS 28 |
| 449 | |
| 450 | /* IAR9 BIT FIELDS */ |
| 451 | #define IRQ_SDH_MASK0_POS 0 |
| 452 | #define IRQ_SDH_MASK1_POS 4 |
| 453 | #define IRQ_USB_INT0_POS 12 |
| 454 | #define IRQ_USB_INT1_POS 16 |
| 455 | #define IRQ_USB_INT2_POS 20 |
| 456 | #define IRQ_USB_DMA_POS 24 |
| 457 | #define IRQ_OTPSEC_POS 28 |
| 458 | |
| 459 | /* IAR10 BIT FIELDS */ |
| 460 | #define IRQ_TIMER0_POS 24 |
| 461 | #define IRQ_TIMER1_POS 28 |
| 462 | |
| 463 | /* IAR11 BIT FIELDS */ |
| 464 | #define IRQ_TIMER2_POS 0 |
| 465 | #define IRQ_TIMER3_POS 4 |
| 466 | #define IRQ_TIMER4_POS 8 |
| 467 | #define IRQ_TIMER5_POS 12 |
| 468 | #define IRQ_TIMER6_POS 16 |
| 469 | #define IRQ_TIMER7_POS 20 |
| 470 | #define IRQ_PINT2_POS 24 |
| 471 | #define IRQ_PINT3_POS 28 |
| 472 | |
Mike Frysinger | 77c90e3 | 2010-10-27 20:21:51 +0000 | [diff] [blame] | 473 | #ifndef __ASSEMBLY__ |
| 474 | #include <linux/types.h> |
| 475 | |
| 476 | /* |
| 477 | * bfin pint registers layout |
| 478 | */ |
| 479 | struct bfin_pint_regs { |
| 480 | u32 mask_set; |
| 481 | u32 mask_clear; |
| 482 | u32 irq; |
| 483 | u32 assign; |
| 484 | u32 edge_set; |
| 485 | u32 edge_clear; |
| 486 | u32 invert_set; |
| 487 | u32 invert_clear; |
| 488 | u32 pinstate; |
| 489 | u32 latch; |
| 490 | u32 __pad0[2]; |
| 491 | }; |
| 492 | |
| 493 | #endif |
| 494 | |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 495 | #endif /* _BF548_IRQ_H_ */ |