Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013-2014 Allwinner Tech Co., Ltd |
| 3 | * Author: Sugar <shuge@allwinnertech.com> |
| 4 | * |
| 5 | * Copyright (C) 2014 Maxime Ripard |
| 6 | * Maxime Ripard <maxime.ripard@free-electrons.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/clk.h> |
| 15 | #include <linux/delay.h> |
| 16 | #include <linux/dmaengine.h> |
| 17 | #include <linux/dmapool.h> |
| 18 | #include <linux/interrupt.h> |
| 19 | #include <linux/module.h> |
| 20 | #include <linux/of_dma.h> |
Chen-Yu Tsai | 25a37c2 | 2014-11-07 12:15:46 +0800 | [diff] [blame] | 21 | #include <linux/of_device.h> |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 22 | #include <linux/platform_device.h> |
| 23 | #include <linux/reset.h> |
| 24 | #include <linux/slab.h> |
| 25 | #include <linux/types.h> |
| 26 | |
| 27 | #include "virt-dma.h" |
| 28 | |
| 29 | /* |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 30 | * Common registers |
| 31 | */ |
| 32 | #define DMA_IRQ_EN(x) ((x) * 0x04) |
| 33 | #define DMA_IRQ_HALF BIT(0) |
| 34 | #define DMA_IRQ_PKG BIT(1) |
| 35 | #define DMA_IRQ_QUEUE BIT(2) |
| 36 | |
| 37 | #define DMA_IRQ_CHAN_NR 8 |
| 38 | #define DMA_IRQ_CHAN_WIDTH 4 |
| 39 | |
| 40 | |
| 41 | #define DMA_IRQ_STAT(x) ((x) * 0x04 + 0x10) |
| 42 | |
| 43 | #define DMA_STAT 0x30 |
| 44 | |
| 45 | /* |
Chen-Yu Tsai | 0b04ddf | 2014-11-07 12:15:47 +0800 | [diff] [blame] | 46 | * sun8i specific registers |
| 47 | */ |
| 48 | #define SUN8I_DMA_GATE 0x20 |
| 49 | #define SUN8I_DMA_GATE_ENABLE 0x4 |
| 50 | |
| 51 | /* |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 52 | * Channels specific registers |
| 53 | */ |
| 54 | #define DMA_CHAN_ENABLE 0x00 |
| 55 | #define DMA_CHAN_ENABLE_START BIT(0) |
| 56 | #define DMA_CHAN_ENABLE_STOP 0 |
| 57 | |
| 58 | #define DMA_CHAN_PAUSE 0x04 |
| 59 | #define DMA_CHAN_PAUSE_PAUSE BIT(1) |
| 60 | #define DMA_CHAN_PAUSE_RESUME 0 |
| 61 | |
| 62 | #define DMA_CHAN_LLI_ADDR 0x08 |
| 63 | |
| 64 | #define DMA_CHAN_CUR_CFG 0x0c |
| 65 | #define DMA_CHAN_CFG_SRC_DRQ(x) ((x) & 0x1f) |
| 66 | #define DMA_CHAN_CFG_SRC_IO_MODE BIT(5) |
| 67 | #define DMA_CHAN_CFG_SRC_LINEAR_MODE (0 << 5) |
| 68 | #define DMA_CHAN_CFG_SRC_BURST(x) (((x) & 0x3) << 7) |
| 69 | #define DMA_CHAN_CFG_SRC_WIDTH(x) (((x) & 0x3) << 9) |
| 70 | |
| 71 | #define DMA_CHAN_CFG_DST_DRQ(x) (DMA_CHAN_CFG_SRC_DRQ(x) << 16) |
| 72 | #define DMA_CHAN_CFG_DST_IO_MODE (DMA_CHAN_CFG_SRC_IO_MODE << 16) |
| 73 | #define DMA_CHAN_CFG_DST_LINEAR_MODE (DMA_CHAN_CFG_SRC_LINEAR_MODE << 16) |
| 74 | #define DMA_CHAN_CFG_DST_BURST(x) (DMA_CHAN_CFG_SRC_BURST(x) << 16) |
| 75 | #define DMA_CHAN_CFG_DST_WIDTH(x) (DMA_CHAN_CFG_SRC_WIDTH(x) << 16) |
| 76 | |
| 77 | #define DMA_CHAN_CUR_SRC 0x10 |
| 78 | |
| 79 | #define DMA_CHAN_CUR_DST 0x14 |
| 80 | |
| 81 | #define DMA_CHAN_CUR_CNT 0x18 |
| 82 | |
| 83 | #define DMA_CHAN_CUR_PARA 0x1c |
| 84 | |
| 85 | |
| 86 | /* |
| 87 | * Various hardware related defines |
| 88 | */ |
| 89 | #define LLI_LAST_ITEM 0xfffff800 |
| 90 | #define NORMAL_WAIT 8 |
| 91 | #define DRQ_SDRAM 1 |
| 92 | |
| 93 | /* |
Chen-Yu Tsai | 25a37c2 | 2014-11-07 12:15:46 +0800 | [diff] [blame] | 94 | * Hardware channels / ports representation |
| 95 | * |
| 96 | * The hardware is used in several SoCs, with differing numbers |
| 97 | * of channels and endpoints. This structure ties those numbers |
| 98 | * to a certain compatible string. |
| 99 | */ |
| 100 | struct sun6i_dma_config { |
| 101 | u32 nr_max_channels; |
| 102 | u32 nr_max_requests; |
| 103 | u32 nr_max_vchans; |
| 104 | }; |
| 105 | |
| 106 | /* |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 107 | * Hardware representation of the LLI |
| 108 | * |
| 109 | * The hardware will be fed the physical address of this structure, |
| 110 | * and read its content in order to start the transfer. |
| 111 | */ |
| 112 | struct sun6i_dma_lli { |
| 113 | u32 cfg; |
| 114 | u32 src; |
| 115 | u32 dst; |
| 116 | u32 len; |
| 117 | u32 para; |
| 118 | u32 p_lli_next; |
| 119 | |
| 120 | /* |
| 121 | * This field is not used by the DMA controller, but will be |
| 122 | * used by the CPU to go through the list (mostly for dumping |
| 123 | * or freeing it). |
| 124 | */ |
| 125 | struct sun6i_dma_lli *v_lli_next; |
| 126 | }; |
| 127 | |
| 128 | |
| 129 | struct sun6i_desc { |
| 130 | struct virt_dma_desc vd; |
| 131 | dma_addr_t p_lli; |
| 132 | struct sun6i_dma_lli *v_lli; |
| 133 | }; |
| 134 | |
| 135 | struct sun6i_pchan { |
| 136 | u32 idx; |
| 137 | void __iomem *base; |
| 138 | struct sun6i_vchan *vchan; |
| 139 | struct sun6i_desc *desc; |
| 140 | struct sun6i_desc *done; |
| 141 | }; |
| 142 | |
| 143 | struct sun6i_vchan { |
| 144 | struct virt_dma_chan vc; |
| 145 | struct list_head node; |
| 146 | struct dma_slave_config cfg; |
| 147 | struct sun6i_pchan *phy; |
| 148 | u8 port; |
| 149 | }; |
| 150 | |
| 151 | struct sun6i_dma_dev { |
| 152 | struct dma_device slave; |
| 153 | void __iomem *base; |
| 154 | struct clk *clk; |
| 155 | int irq; |
| 156 | spinlock_t lock; |
| 157 | struct reset_control *rstc; |
| 158 | struct tasklet_struct task; |
| 159 | atomic_t tasklet_shutdown; |
| 160 | struct list_head pending; |
| 161 | struct dma_pool *pool; |
| 162 | struct sun6i_pchan *pchans; |
| 163 | struct sun6i_vchan *vchans; |
Chen-Yu Tsai | 25a37c2 | 2014-11-07 12:15:46 +0800 | [diff] [blame] | 164 | const struct sun6i_dma_config *cfg; |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 165 | }; |
| 166 | |
| 167 | static struct device *chan2dev(struct dma_chan *chan) |
| 168 | { |
| 169 | return &chan->dev->device; |
| 170 | } |
| 171 | |
| 172 | static inline struct sun6i_dma_dev *to_sun6i_dma_dev(struct dma_device *d) |
| 173 | { |
| 174 | return container_of(d, struct sun6i_dma_dev, slave); |
| 175 | } |
| 176 | |
| 177 | static inline struct sun6i_vchan *to_sun6i_vchan(struct dma_chan *chan) |
| 178 | { |
| 179 | return container_of(chan, struct sun6i_vchan, vc.chan); |
| 180 | } |
| 181 | |
| 182 | static inline struct sun6i_desc * |
| 183 | to_sun6i_desc(struct dma_async_tx_descriptor *tx) |
| 184 | { |
| 185 | return container_of(tx, struct sun6i_desc, vd.tx); |
| 186 | } |
| 187 | |
| 188 | static inline void sun6i_dma_dump_com_regs(struct sun6i_dma_dev *sdev) |
| 189 | { |
| 190 | dev_dbg(sdev->slave.dev, "Common register:\n" |
| 191 | "\tmask0(%04x): 0x%08x\n" |
| 192 | "\tmask1(%04x): 0x%08x\n" |
| 193 | "\tpend0(%04x): 0x%08x\n" |
| 194 | "\tpend1(%04x): 0x%08x\n" |
| 195 | "\tstats(%04x): 0x%08x\n", |
| 196 | DMA_IRQ_EN(0), readl(sdev->base + DMA_IRQ_EN(0)), |
| 197 | DMA_IRQ_EN(1), readl(sdev->base + DMA_IRQ_EN(1)), |
| 198 | DMA_IRQ_STAT(0), readl(sdev->base + DMA_IRQ_STAT(0)), |
| 199 | DMA_IRQ_STAT(1), readl(sdev->base + DMA_IRQ_STAT(1)), |
| 200 | DMA_STAT, readl(sdev->base + DMA_STAT)); |
| 201 | } |
| 202 | |
| 203 | static inline void sun6i_dma_dump_chan_regs(struct sun6i_dma_dev *sdev, |
| 204 | struct sun6i_pchan *pchan) |
| 205 | { |
Vinod Koul | 42c0d54 | 2014-07-28 11:57:25 +0530 | [diff] [blame] | 206 | phys_addr_t reg = virt_to_phys(pchan->base); |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 207 | |
| 208 | dev_dbg(sdev->slave.dev, "Chan %d reg: %pa\n" |
| 209 | "\t___en(%04x): \t0x%08x\n" |
| 210 | "\tpause(%04x): \t0x%08x\n" |
| 211 | "\tstart(%04x): \t0x%08x\n" |
| 212 | "\t__cfg(%04x): \t0x%08x\n" |
| 213 | "\t__src(%04x): \t0x%08x\n" |
| 214 | "\t__dst(%04x): \t0x%08x\n" |
| 215 | "\tcount(%04x): \t0x%08x\n" |
| 216 | "\t_para(%04x): \t0x%08x\n\n", |
| 217 | pchan->idx, ®, |
| 218 | DMA_CHAN_ENABLE, |
| 219 | readl(pchan->base + DMA_CHAN_ENABLE), |
| 220 | DMA_CHAN_PAUSE, |
| 221 | readl(pchan->base + DMA_CHAN_PAUSE), |
| 222 | DMA_CHAN_LLI_ADDR, |
| 223 | readl(pchan->base + DMA_CHAN_LLI_ADDR), |
| 224 | DMA_CHAN_CUR_CFG, |
| 225 | readl(pchan->base + DMA_CHAN_CUR_CFG), |
| 226 | DMA_CHAN_CUR_SRC, |
| 227 | readl(pchan->base + DMA_CHAN_CUR_SRC), |
| 228 | DMA_CHAN_CUR_DST, |
| 229 | readl(pchan->base + DMA_CHAN_CUR_DST), |
| 230 | DMA_CHAN_CUR_CNT, |
| 231 | readl(pchan->base + DMA_CHAN_CUR_CNT), |
| 232 | DMA_CHAN_CUR_PARA, |
| 233 | readl(pchan->base + DMA_CHAN_CUR_PARA)); |
| 234 | } |
| 235 | |
Maxime Ripard | 1f9cd91 | 2014-11-11 19:35:52 +0100 | [diff] [blame] | 236 | static inline s8 convert_burst(u32 maxburst) |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 237 | { |
| 238 | switch (maxburst) { |
| 239 | case 1: |
Maxime Ripard | 1f9cd91 | 2014-11-11 19:35:52 +0100 | [diff] [blame] | 240 | return 0; |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 241 | case 8: |
Maxime Ripard | 1f9cd91 | 2014-11-11 19:35:52 +0100 | [diff] [blame] | 242 | return 2; |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 243 | default: |
| 244 | return -EINVAL; |
| 245 | } |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 246 | } |
| 247 | |
Maxime Ripard | 1f9cd91 | 2014-11-11 19:35:52 +0100 | [diff] [blame] | 248 | static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width) |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 249 | { |
Maxime Ripard | 92e4a3b | 2014-07-30 10:30:21 +0200 | [diff] [blame] | 250 | if ((addr_width < DMA_SLAVE_BUSWIDTH_1_BYTE) || |
| 251 | (addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES)) |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 252 | return -EINVAL; |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 253 | |
Maxime Ripard | 1f9cd91 | 2014-11-11 19:35:52 +0100 | [diff] [blame] | 254 | return addr_width >> 1; |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 255 | } |
| 256 | |
| 257 | static void *sun6i_dma_lli_add(struct sun6i_dma_lli *prev, |
| 258 | struct sun6i_dma_lli *next, |
| 259 | dma_addr_t next_phy, |
| 260 | struct sun6i_desc *txd) |
| 261 | { |
| 262 | if ((!prev && !txd) || !next) |
| 263 | return NULL; |
| 264 | |
| 265 | if (!prev) { |
| 266 | txd->p_lli = next_phy; |
| 267 | txd->v_lli = next; |
| 268 | } else { |
| 269 | prev->p_lli_next = next_phy; |
| 270 | prev->v_lli_next = next; |
| 271 | } |
| 272 | |
| 273 | next->p_lli_next = LLI_LAST_ITEM; |
| 274 | next->v_lli_next = NULL; |
| 275 | |
| 276 | return next; |
| 277 | } |
| 278 | |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 279 | static inline void sun6i_dma_dump_lli(struct sun6i_vchan *vchan, |
| 280 | struct sun6i_dma_lli *lli) |
| 281 | { |
Vinod Koul | 42c0d54 | 2014-07-28 11:57:25 +0530 | [diff] [blame] | 282 | phys_addr_t p_lli = virt_to_phys(lli); |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 283 | |
| 284 | dev_dbg(chan2dev(&vchan->vc.chan), |
| 285 | "\n\tdesc: p - %pa v - 0x%p\n" |
| 286 | "\t\tc - 0x%08x s - 0x%08x d - 0x%08x\n" |
| 287 | "\t\tl - 0x%08x p - 0x%08x n - 0x%08x\n", |
| 288 | &p_lli, lli, |
| 289 | lli->cfg, lli->src, lli->dst, |
| 290 | lli->len, lli->para, lli->p_lli_next); |
| 291 | } |
| 292 | |
| 293 | static void sun6i_dma_free_desc(struct virt_dma_desc *vd) |
| 294 | { |
| 295 | struct sun6i_desc *txd = to_sun6i_desc(&vd->tx); |
| 296 | struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vd->tx.chan->device); |
| 297 | struct sun6i_dma_lli *v_lli, *v_next; |
| 298 | dma_addr_t p_lli, p_next; |
| 299 | |
| 300 | if (unlikely(!txd)) |
| 301 | return; |
| 302 | |
| 303 | p_lli = txd->p_lli; |
| 304 | v_lli = txd->v_lli; |
| 305 | |
| 306 | while (v_lli) { |
| 307 | v_next = v_lli->v_lli_next; |
| 308 | p_next = v_lli->p_lli_next; |
| 309 | |
| 310 | dma_pool_free(sdev->pool, v_lli, p_lli); |
| 311 | |
| 312 | v_lli = v_next; |
| 313 | p_lli = p_next; |
| 314 | } |
| 315 | |
| 316 | kfree(txd); |
| 317 | } |
| 318 | |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 319 | static int sun6i_dma_start_desc(struct sun6i_vchan *vchan) |
| 320 | { |
| 321 | struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vchan->vc.chan.device); |
| 322 | struct virt_dma_desc *desc = vchan_next_desc(&vchan->vc); |
| 323 | struct sun6i_pchan *pchan = vchan->phy; |
| 324 | u32 irq_val, irq_reg, irq_offset; |
| 325 | |
| 326 | if (!pchan) |
| 327 | return -EAGAIN; |
| 328 | |
| 329 | if (!desc) { |
| 330 | pchan->desc = NULL; |
| 331 | pchan->done = NULL; |
| 332 | return -EAGAIN; |
| 333 | } |
| 334 | |
| 335 | list_del(&desc->node); |
| 336 | |
| 337 | pchan->desc = to_sun6i_desc(&desc->tx); |
| 338 | pchan->done = NULL; |
| 339 | |
| 340 | sun6i_dma_dump_lli(vchan, pchan->desc->v_lli); |
| 341 | |
| 342 | irq_reg = pchan->idx / DMA_IRQ_CHAN_NR; |
| 343 | irq_offset = pchan->idx % DMA_IRQ_CHAN_NR; |
| 344 | |
Jean-Francois Moine | 128fe7e | 2016-04-22 08:14:33 +0200 | [diff] [blame] | 345 | irq_val = readl(sdev->base + DMA_IRQ_EN(irq_reg)); |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 346 | irq_val |= DMA_IRQ_QUEUE << (irq_offset * DMA_IRQ_CHAN_WIDTH); |
Jean-Francois Moine | 128fe7e | 2016-04-22 08:14:33 +0200 | [diff] [blame] | 347 | writel(irq_val, sdev->base + DMA_IRQ_EN(irq_reg)); |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 348 | |
| 349 | writel(pchan->desc->p_lli, pchan->base + DMA_CHAN_LLI_ADDR); |
| 350 | writel(DMA_CHAN_ENABLE_START, pchan->base + DMA_CHAN_ENABLE); |
| 351 | |
| 352 | sun6i_dma_dump_com_regs(sdev); |
| 353 | sun6i_dma_dump_chan_regs(sdev, pchan); |
| 354 | |
| 355 | return 0; |
| 356 | } |
| 357 | |
| 358 | static void sun6i_dma_tasklet(unsigned long data) |
| 359 | { |
| 360 | struct sun6i_dma_dev *sdev = (struct sun6i_dma_dev *)data; |
Chen-Yu Tsai | 25a37c2 | 2014-11-07 12:15:46 +0800 | [diff] [blame] | 361 | const struct sun6i_dma_config *cfg = sdev->cfg; |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 362 | struct sun6i_vchan *vchan; |
| 363 | struct sun6i_pchan *pchan; |
| 364 | unsigned int pchan_alloc = 0; |
| 365 | unsigned int pchan_idx; |
| 366 | |
| 367 | list_for_each_entry(vchan, &sdev->slave.channels, vc.chan.device_node) { |
| 368 | spin_lock_irq(&vchan->vc.lock); |
| 369 | |
| 370 | pchan = vchan->phy; |
| 371 | |
| 372 | if (pchan && pchan->done) { |
| 373 | if (sun6i_dma_start_desc(vchan)) { |
| 374 | /* |
| 375 | * No current txd associated with this channel |
| 376 | */ |
| 377 | dev_dbg(sdev->slave.dev, "pchan %u: free\n", |
| 378 | pchan->idx); |
| 379 | |
| 380 | /* Mark this channel free */ |
| 381 | vchan->phy = NULL; |
| 382 | pchan->vchan = NULL; |
| 383 | } |
| 384 | } |
| 385 | spin_unlock_irq(&vchan->vc.lock); |
| 386 | } |
| 387 | |
| 388 | spin_lock_irq(&sdev->lock); |
Chen-Yu Tsai | 25a37c2 | 2014-11-07 12:15:46 +0800 | [diff] [blame] | 389 | for (pchan_idx = 0; pchan_idx < cfg->nr_max_channels; pchan_idx++) { |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 390 | pchan = &sdev->pchans[pchan_idx]; |
| 391 | |
| 392 | if (pchan->vchan || list_empty(&sdev->pending)) |
| 393 | continue; |
| 394 | |
| 395 | vchan = list_first_entry(&sdev->pending, |
| 396 | struct sun6i_vchan, node); |
| 397 | |
| 398 | /* Remove from pending channels */ |
| 399 | list_del_init(&vchan->node); |
| 400 | pchan_alloc |= BIT(pchan_idx); |
| 401 | |
| 402 | /* Mark this channel allocated */ |
| 403 | pchan->vchan = vchan; |
| 404 | vchan->phy = pchan; |
| 405 | dev_dbg(sdev->slave.dev, "pchan %u: alloc vchan %p\n", |
| 406 | pchan->idx, &vchan->vc); |
| 407 | } |
| 408 | spin_unlock_irq(&sdev->lock); |
| 409 | |
Chen-Yu Tsai | 25a37c2 | 2014-11-07 12:15:46 +0800 | [diff] [blame] | 410 | for (pchan_idx = 0; pchan_idx < cfg->nr_max_channels; pchan_idx++) { |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 411 | if (!(pchan_alloc & BIT(pchan_idx))) |
| 412 | continue; |
| 413 | |
| 414 | pchan = sdev->pchans + pchan_idx; |
| 415 | vchan = pchan->vchan; |
| 416 | if (vchan) { |
| 417 | spin_lock_irq(&vchan->vc.lock); |
| 418 | sun6i_dma_start_desc(vchan); |
| 419 | spin_unlock_irq(&vchan->vc.lock); |
| 420 | } |
| 421 | } |
| 422 | } |
| 423 | |
| 424 | static irqreturn_t sun6i_dma_interrupt(int irq, void *dev_id) |
| 425 | { |
| 426 | struct sun6i_dma_dev *sdev = dev_id; |
| 427 | struct sun6i_vchan *vchan; |
| 428 | struct sun6i_pchan *pchan; |
| 429 | int i, j, ret = IRQ_NONE; |
| 430 | u32 status; |
| 431 | |
Chen-Yu Tsai | 25a37c2 | 2014-11-07 12:15:46 +0800 | [diff] [blame] | 432 | for (i = 0; i < sdev->cfg->nr_max_channels / DMA_IRQ_CHAN_NR; i++) { |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 433 | status = readl(sdev->base + DMA_IRQ_STAT(i)); |
| 434 | if (!status) |
| 435 | continue; |
| 436 | |
| 437 | dev_dbg(sdev->slave.dev, "DMA irq status %s: 0x%x\n", |
| 438 | i ? "high" : "low", status); |
| 439 | |
| 440 | writel(status, sdev->base + DMA_IRQ_STAT(i)); |
| 441 | |
Chen-Yu Tsai | 25a37c2 | 2014-11-07 12:15:46 +0800 | [diff] [blame] | 442 | for (j = 0; (j < DMA_IRQ_CHAN_NR) && status; j++) { |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 443 | if (status & DMA_IRQ_QUEUE) { |
| 444 | pchan = sdev->pchans + j; |
| 445 | vchan = pchan->vchan; |
| 446 | |
| 447 | if (vchan) { |
| 448 | spin_lock(&vchan->vc.lock); |
| 449 | vchan_cookie_complete(&pchan->desc->vd); |
| 450 | pchan->done = pchan->desc; |
| 451 | spin_unlock(&vchan->vc.lock); |
| 452 | } |
| 453 | } |
| 454 | |
Chen-Yu Tsai | 25a37c2 | 2014-11-07 12:15:46 +0800 | [diff] [blame] | 455 | status = status >> DMA_IRQ_CHAN_WIDTH; |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 456 | } |
| 457 | |
| 458 | if (!atomic_read(&sdev->tasklet_shutdown)) |
| 459 | tasklet_schedule(&sdev->task); |
| 460 | ret = IRQ_HANDLED; |
| 461 | } |
| 462 | |
| 463 | return ret; |
| 464 | } |
| 465 | |
Jean-Francois Moine | 52c8717 | 2016-04-22 08:47:29 +0200 | [diff] [blame^] | 466 | static int set_config(struct sun6i_dma_dev *sdev, |
| 467 | struct dma_slave_config *sconfig, |
| 468 | enum dma_transfer_direction direction, |
| 469 | u32 *p_cfg) |
| 470 | { |
| 471 | s8 src_width, dst_width, src_burst, dst_burst; |
| 472 | |
| 473 | src_burst = convert_burst(sconfig->src_maxburst); |
| 474 | src_width = convert_buswidth(sconfig->src_addr_width); |
| 475 | dst_burst = convert_burst(sconfig->dst_maxburst); |
| 476 | dst_width = convert_buswidth(sconfig->dst_addr_width); |
| 477 | |
| 478 | if (src_burst < 0) |
| 479 | return src_burst; |
| 480 | if (src_width < 0) |
| 481 | return src_width; |
| 482 | if (dst_burst < 0) |
| 483 | return dst_burst; |
| 484 | if (dst_width < 0) |
| 485 | return dst_width; |
| 486 | |
| 487 | *p_cfg = DMA_CHAN_CFG_SRC_BURST(src_burst) | |
| 488 | DMA_CHAN_CFG_SRC_WIDTH(src_width) | |
| 489 | DMA_CHAN_CFG_DST_BURST(dst_burst) | |
| 490 | DMA_CHAN_CFG_DST_WIDTH(dst_width); |
| 491 | |
| 492 | return 0; |
| 493 | } |
| 494 | |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 495 | static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy( |
| 496 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
| 497 | size_t len, unsigned long flags) |
| 498 | { |
| 499 | struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); |
| 500 | struct sun6i_vchan *vchan = to_sun6i_vchan(chan); |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 501 | struct sun6i_dma_lli *v_lli; |
| 502 | struct sun6i_desc *txd; |
| 503 | dma_addr_t p_lli; |
Maxime Ripard | 1f9cd91 | 2014-11-11 19:35:52 +0100 | [diff] [blame] | 504 | s8 burst, width; |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 505 | |
| 506 | dev_dbg(chan2dev(chan), |
| 507 | "%s; chan: %d, dest: %pad, src: %pad, len: %zu. flags: 0x%08lx\n", |
| 508 | __func__, vchan->vc.chan.chan_id, &dest, &src, len, flags); |
| 509 | |
| 510 | if (!len) |
| 511 | return NULL; |
| 512 | |
| 513 | txd = kzalloc(sizeof(*txd), GFP_NOWAIT); |
| 514 | if (!txd) |
| 515 | return NULL; |
| 516 | |
| 517 | v_lli = dma_pool_alloc(sdev->pool, GFP_NOWAIT, &p_lli); |
| 518 | if (!v_lli) { |
| 519 | dev_err(sdev->slave.dev, "Failed to alloc lli memory\n"); |
Maxime Ripard | 4fbd804 | 2014-07-30 10:30:23 +0200 | [diff] [blame] | 520 | goto err_txd_free; |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 521 | } |
| 522 | |
Maxime Ripard | 1f9cd91 | 2014-11-11 19:35:52 +0100 | [diff] [blame] | 523 | v_lli->src = src; |
| 524 | v_lli->dst = dest; |
| 525 | v_lli->len = len; |
| 526 | v_lli->para = NORMAL_WAIT; |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 527 | |
Maxime Ripard | 1f9cd91 | 2014-11-11 19:35:52 +0100 | [diff] [blame] | 528 | burst = convert_burst(8); |
| 529 | width = convert_buswidth(DMA_SLAVE_BUSWIDTH_4_BYTES); |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 530 | v_lli->cfg |= DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) | |
| 531 | DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) | |
| 532 | DMA_CHAN_CFG_DST_LINEAR_MODE | |
Maxime Ripard | 1f9cd91 | 2014-11-11 19:35:52 +0100 | [diff] [blame] | 533 | DMA_CHAN_CFG_SRC_LINEAR_MODE | |
| 534 | DMA_CHAN_CFG_SRC_BURST(burst) | |
| 535 | DMA_CHAN_CFG_SRC_WIDTH(width) | |
| 536 | DMA_CHAN_CFG_DST_BURST(burst) | |
| 537 | DMA_CHAN_CFG_DST_WIDTH(width); |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 538 | |
| 539 | sun6i_dma_lli_add(NULL, v_lli, p_lli, txd); |
| 540 | |
| 541 | sun6i_dma_dump_lli(vchan, v_lli); |
| 542 | |
| 543 | return vchan_tx_prep(&vchan->vc, &txd->vd, flags); |
| 544 | |
Maxime Ripard | 4fbd804 | 2014-07-30 10:30:23 +0200 | [diff] [blame] | 545 | err_txd_free: |
| 546 | kfree(txd); |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 547 | return NULL; |
| 548 | } |
| 549 | |
| 550 | static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg( |
| 551 | struct dma_chan *chan, struct scatterlist *sgl, |
| 552 | unsigned int sg_len, enum dma_transfer_direction dir, |
| 553 | unsigned long flags, void *context) |
| 554 | { |
| 555 | struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); |
| 556 | struct sun6i_vchan *vchan = to_sun6i_vchan(chan); |
| 557 | struct dma_slave_config *sconfig = &vchan->cfg; |
| 558 | struct sun6i_dma_lli *v_lli, *prev = NULL; |
| 559 | struct sun6i_desc *txd; |
| 560 | struct scatterlist *sg; |
| 561 | dma_addr_t p_lli; |
Jean-Francois Moine | 52c8717 | 2016-04-22 08:47:29 +0200 | [diff] [blame^] | 562 | u32 lli_cfg; |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 563 | int i, ret; |
| 564 | |
| 565 | if (!sgl) |
| 566 | return NULL; |
| 567 | |
| 568 | if (!is_slave_direction(dir)) { |
| 569 | dev_err(chan2dev(chan), "Invalid DMA direction\n"); |
| 570 | return NULL; |
| 571 | } |
| 572 | |
Jean-Francois Moine | 52c8717 | 2016-04-22 08:47:29 +0200 | [diff] [blame^] | 573 | ret = set_config(sdev, sconfig, dir, &lli_cfg); |
| 574 | if (ret) { |
| 575 | dev_err(chan2dev(chan), "Invalid DMA configuration\n"); |
| 576 | return NULL; |
| 577 | } |
| 578 | |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 579 | txd = kzalloc(sizeof(*txd), GFP_NOWAIT); |
| 580 | if (!txd) |
| 581 | return NULL; |
| 582 | |
| 583 | for_each_sg(sgl, sg, sg_len, i) { |
| 584 | v_lli = dma_pool_alloc(sdev->pool, GFP_NOWAIT, &p_lli); |
Maxime Ripard | 4fbd804 | 2014-07-30 10:30:23 +0200 | [diff] [blame] | 585 | if (!v_lli) |
| 586 | goto err_lli_free; |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 587 | |
Jean-Francois Moine | 52c8717 | 2016-04-22 08:47:29 +0200 | [diff] [blame^] | 588 | v_lli->len = sg_dma_len(sg); |
| 589 | v_lli->para = NORMAL_WAIT; |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 590 | |
Jean-Francois Moine | 52c8717 | 2016-04-22 08:47:29 +0200 | [diff] [blame^] | 591 | if (dir == DMA_MEM_TO_DEV) { |
| 592 | v_lli->src = sg_dma_address(sg); |
| 593 | v_lli->dst = sconfig->dst_addr; |
| 594 | v_lli->cfg = lli_cfg | |
| 595 | DMA_CHAN_CFG_DST_IO_MODE | |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 596 | DMA_CHAN_CFG_SRC_LINEAR_MODE | |
| 597 | DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) | |
| 598 | DMA_CHAN_CFG_DST_DRQ(vchan->port); |
| 599 | |
| 600 | dev_dbg(chan2dev(chan), |
Vinod Koul | 7f5e03e | 2014-07-28 12:32:51 +0530 | [diff] [blame] | 601 | "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n", |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 602 | __func__, vchan->vc.chan.chan_id, |
| 603 | &sconfig->dst_addr, &sg_dma_address(sg), |
| 604 | sg_dma_len(sg), flags); |
| 605 | |
| 606 | } else { |
Jean-Francois Moine | 52c8717 | 2016-04-22 08:47:29 +0200 | [diff] [blame^] | 607 | v_lli->src = sconfig->src_addr; |
| 608 | v_lli->dst = sg_dma_address(sg); |
| 609 | v_lli->cfg = lli_cfg | |
| 610 | DMA_CHAN_CFG_DST_LINEAR_MODE | |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 611 | DMA_CHAN_CFG_SRC_IO_MODE | |
| 612 | DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) | |
| 613 | DMA_CHAN_CFG_SRC_DRQ(vchan->port); |
| 614 | |
| 615 | dev_dbg(chan2dev(chan), |
Vinod Koul | 7f5e03e | 2014-07-28 12:32:51 +0530 | [diff] [blame] | 616 | "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n", |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 617 | __func__, vchan->vc.chan.chan_id, |
| 618 | &sg_dma_address(sg), &sconfig->src_addr, |
| 619 | sg_dma_len(sg), flags); |
| 620 | } |
| 621 | |
| 622 | prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd); |
| 623 | } |
| 624 | |
| 625 | dev_dbg(chan2dev(chan), "First: %pad\n", &txd->p_lli); |
| 626 | for (prev = txd->v_lli; prev; prev = prev->v_lli_next) |
| 627 | sun6i_dma_dump_lli(vchan, prev); |
| 628 | |
| 629 | return vchan_tx_prep(&vchan->vc, &txd->vd, flags); |
| 630 | |
Maxime Ripard | 4fbd804 | 2014-07-30 10:30:23 +0200 | [diff] [blame] | 631 | err_lli_free: |
| 632 | for (prev = txd->v_lli; prev; prev = prev->v_lli_next) |
| 633 | dma_pool_free(sdev->pool, prev, virt_to_phys(prev)); |
| 634 | kfree(txd); |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 635 | return NULL; |
| 636 | } |
| 637 | |
Maxime Ripard | 826b15a | 2014-11-17 14:42:35 +0100 | [diff] [blame] | 638 | static int sun6i_dma_config(struct dma_chan *chan, |
| 639 | struct dma_slave_config *config) |
| 640 | { |
| 641 | struct sun6i_vchan *vchan = to_sun6i_vchan(chan); |
| 642 | |
| 643 | memcpy(&vchan->cfg, config, sizeof(*config)); |
| 644 | |
| 645 | return 0; |
| 646 | } |
| 647 | |
| 648 | static int sun6i_dma_pause(struct dma_chan *chan) |
| 649 | { |
| 650 | struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); |
| 651 | struct sun6i_vchan *vchan = to_sun6i_vchan(chan); |
| 652 | struct sun6i_pchan *pchan = vchan->phy; |
| 653 | |
| 654 | dev_dbg(chan2dev(chan), "vchan %p: pause\n", &vchan->vc); |
| 655 | |
| 656 | if (pchan) { |
| 657 | writel(DMA_CHAN_PAUSE_PAUSE, |
| 658 | pchan->base + DMA_CHAN_PAUSE); |
| 659 | } else { |
| 660 | spin_lock(&sdev->lock); |
| 661 | list_del_init(&vchan->node); |
| 662 | spin_unlock(&sdev->lock); |
| 663 | } |
| 664 | |
| 665 | return 0; |
| 666 | } |
| 667 | |
| 668 | static int sun6i_dma_resume(struct dma_chan *chan) |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 669 | { |
| 670 | struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); |
| 671 | struct sun6i_vchan *vchan = to_sun6i_vchan(chan); |
| 672 | struct sun6i_pchan *pchan = vchan->phy; |
| 673 | unsigned long flags; |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 674 | |
Maxime Ripard | 826b15a | 2014-11-17 14:42:35 +0100 | [diff] [blame] | 675 | dev_dbg(chan2dev(chan), "vchan %p: resume\n", &vchan->vc); |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 676 | |
Maxime Ripard | 826b15a | 2014-11-17 14:42:35 +0100 | [diff] [blame] | 677 | spin_lock_irqsave(&vchan->vc.lock, flags); |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 678 | |
Maxime Ripard | 826b15a | 2014-11-17 14:42:35 +0100 | [diff] [blame] | 679 | if (pchan) { |
| 680 | writel(DMA_CHAN_PAUSE_RESUME, |
| 681 | pchan->base + DMA_CHAN_PAUSE); |
| 682 | } else if (!list_empty(&vchan->vc.desc_issued)) { |
| 683 | spin_lock(&sdev->lock); |
| 684 | list_add_tail(&vchan->node, &sdev->pending); |
| 685 | spin_unlock(&sdev->lock); |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 686 | } |
Maxime Ripard | 826b15a | 2014-11-17 14:42:35 +0100 | [diff] [blame] | 687 | |
| 688 | spin_unlock_irqrestore(&vchan->vc.lock, flags); |
| 689 | |
| 690 | return 0; |
| 691 | } |
| 692 | |
| 693 | static int sun6i_dma_terminate_all(struct dma_chan *chan) |
| 694 | { |
| 695 | struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); |
| 696 | struct sun6i_vchan *vchan = to_sun6i_vchan(chan); |
| 697 | struct sun6i_pchan *pchan = vchan->phy; |
| 698 | unsigned long flags; |
| 699 | LIST_HEAD(head); |
| 700 | |
| 701 | spin_lock(&sdev->lock); |
| 702 | list_del_init(&vchan->node); |
| 703 | spin_unlock(&sdev->lock); |
| 704 | |
| 705 | spin_lock_irqsave(&vchan->vc.lock, flags); |
| 706 | |
| 707 | vchan_get_all_descriptors(&vchan->vc, &head); |
| 708 | |
| 709 | if (pchan) { |
| 710 | writel(DMA_CHAN_ENABLE_STOP, pchan->base + DMA_CHAN_ENABLE); |
| 711 | writel(DMA_CHAN_PAUSE_RESUME, pchan->base + DMA_CHAN_PAUSE); |
| 712 | |
| 713 | vchan->phy = NULL; |
| 714 | pchan->vchan = NULL; |
| 715 | pchan->desc = NULL; |
| 716 | pchan->done = NULL; |
| 717 | } |
| 718 | |
| 719 | spin_unlock_irqrestore(&vchan->vc.lock, flags); |
| 720 | |
| 721 | vchan_dma_desc_free_list(&vchan->vc, &head); |
| 722 | |
| 723 | return 0; |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 724 | } |
| 725 | |
| 726 | static enum dma_status sun6i_dma_tx_status(struct dma_chan *chan, |
| 727 | dma_cookie_t cookie, |
| 728 | struct dma_tx_state *state) |
| 729 | { |
| 730 | struct sun6i_vchan *vchan = to_sun6i_vchan(chan); |
| 731 | struct sun6i_pchan *pchan = vchan->phy; |
| 732 | struct sun6i_dma_lli *lli; |
| 733 | struct virt_dma_desc *vd; |
| 734 | struct sun6i_desc *txd; |
| 735 | enum dma_status ret; |
| 736 | unsigned long flags; |
| 737 | size_t bytes = 0; |
| 738 | |
| 739 | ret = dma_cookie_status(chan, cookie, state); |
| 740 | if (ret == DMA_COMPLETE) |
| 741 | return ret; |
| 742 | |
| 743 | spin_lock_irqsave(&vchan->vc.lock, flags); |
| 744 | |
| 745 | vd = vchan_find_desc(&vchan->vc, cookie); |
| 746 | txd = to_sun6i_desc(&vd->tx); |
| 747 | |
| 748 | if (vd) { |
| 749 | for (lli = txd->v_lli; lli != NULL; lli = lli->v_lli_next) |
| 750 | bytes += lli->len; |
| 751 | } else if (!pchan || !pchan->desc) { |
| 752 | bytes = 0; |
| 753 | } else { |
| 754 | bytes = readl(pchan->base + DMA_CHAN_CUR_CNT); |
| 755 | } |
| 756 | |
| 757 | spin_unlock_irqrestore(&vchan->vc.lock, flags); |
| 758 | |
| 759 | dma_set_residue(state, bytes); |
| 760 | |
| 761 | return ret; |
| 762 | } |
| 763 | |
| 764 | static void sun6i_dma_issue_pending(struct dma_chan *chan) |
| 765 | { |
| 766 | struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); |
| 767 | struct sun6i_vchan *vchan = to_sun6i_vchan(chan); |
| 768 | unsigned long flags; |
| 769 | |
| 770 | spin_lock_irqsave(&vchan->vc.lock, flags); |
| 771 | |
| 772 | if (vchan_issue_pending(&vchan->vc)) { |
| 773 | spin_lock(&sdev->lock); |
| 774 | |
| 775 | if (!vchan->phy && list_empty(&vchan->node)) { |
| 776 | list_add_tail(&vchan->node, &sdev->pending); |
| 777 | tasklet_schedule(&sdev->task); |
| 778 | dev_dbg(chan2dev(chan), "vchan %p: issued\n", |
| 779 | &vchan->vc); |
| 780 | } |
| 781 | |
| 782 | spin_unlock(&sdev->lock); |
| 783 | } else { |
| 784 | dev_dbg(chan2dev(chan), "vchan %p: nothing to issue\n", |
| 785 | &vchan->vc); |
| 786 | } |
| 787 | |
| 788 | spin_unlock_irqrestore(&vchan->vc.lock, flags); |
| 789 | } |
| 790 | |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 791 | static void sun6i_dma_free_chan_resources(struct dma_chan *chan) |
| 792 | { |
| 793 | struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); |
| 794 | struct sun6i_vchan *vchan = to_sun6i_vchan(chan); |
| 795 | unsigned long flags; |
| 796 | |
| 797 | spin_lock_irqsave(&sdev->lock, flags); |
| 798 | list_del_init(&vchan->node); |
| 799 | spin_unlock_irqrestore(&sdev->lock, flags); |
| 800 | |
| 801 | vchan_free_chan_resources(&vchan->vc); |
| 802 | } |
| 803 | |
| 804 | static struct dma_chan *sun6i_dma_of_xlate(struct of_phandle_args *dma_spec, |
| 805 | struct of_dma *ofdma) |
| 806 | { |
| 807 | struct sun6i_dma_dev *sdev = ofdma->of_dma_data; |
| 808 | struct sun6i_vchan *vchan; |
| 809 | struct dma_chan *chan; |
| 810 | u8 port = dma_spec->args[0]; |
| 811 | |
Chen-Yu Tsai | 25a37c2 | 2014-11-07 12:15:46 +0800 | [diff] [blame] | 812 | if (port > sdev->cfg->nr_max_requests) |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 813 | return NULL; |
| 814 | |
| 815 | chan = dma_get_any_slave_channel(&sdev->slave); |
| 816 | if (!chan) |
| 817 | return NULL; |
| 818 | |
| 819 | vchan = to_sun6i_vchan(chan); |
| 820 | vchan->port = port; |
| 821 | |
| 822 | return chan; |
| 823 | } |
| 824 | |
| 825 | static inline void sun6i_kill_tasklet(struct sun6i_dma_dev *sdev) |
| 826 | { |
| 827 | /* Disable all interrupts from DMA */ |
| 828 | writel(0, sdev->base + DMA_IRQ_EN(0)); |
| 829 | writel(0, sdev->base + DMA_IRQ_EN(1)); |
| 830 | |
| 831 | /* Prevent spurious interrupts from scheduling the tasklet */ |
| 832 | atomic_inc(&sdev->tasklet_shutdown); |
| 833 | |
Maxime Ripard | 174427c | 2014-07-30 10:30:22 +0200 | [diff] [blame] | 834 | /* Make sure we won't have any further interrupts */ |
| 835 | devm_free_irq(sdev->slave.dev, sdev->irq, sdev); |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 836 | |
| 837 | /* Actually prevent the tasklet from being scheduled */ |
| 838 | tasklet_kill(&sdev->task); |
| 839 | } |
| 840 | |
| 841 | static inline void sun6i_dma_free(struct sun6i_dma_dev *sdev) |
| 842 | { |
| 843 | int i; |
| 844 | |
Chen-Yu Tsai | 25a37c2 | 2014-11-07 12:15:46 +0800 | [diff] [blame] | 845 | for (i = 0; i < sdev->cfg->nr_max_vchans; i++) { |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 846 | struct sun6i_vchan *vchan = &sdev->vchans[i]; |
| 847 | |
| 848 | list_del(&vchan->vc.chan.device_node); |
| 849 | tasklet_kill(&vchan->vc.task); |
| 850 | } |
| 851 | } |
| 852 | |
Chen-Yu Tsai | 25a37c2 | 2014-11-07 12:15:46 +0800 | [diff] [blame] | 853 | /* |
| 854 | * For A31: |
| 855 | * |
| 856 | * There's 16 physical channels that can work in parallel. |
| 857 | * |
| 858 | * However we have 30 different endpoints for our requests. |
| 859 | * |
| 860 | * Since the channels are able to handle only an unidirectional |
| 861 | * transfer, we need to allocate more virtual channels so that |
| 862 | * everyone can grab one channel. |
| 863 | * |
| 864 | * Some devices can't work in both direction (mostly because it |
| 865 | * wouldn't make sense), so we have a bit fewer virtual channels than |
| 866 | * 2 channels per endpoints. |
| 867 | */ |
| 868 | |
| 869 | static struct sun6i_dma_config sun6i_a31_dma_cfg = { |
| 870 | .nr_max_channels = 16, |
| 871 | .nr_max_requests = 30, |
| 872 | .nr_max_vchans = 53, |
| 873 | }; |
| 874 | |
Chen-Yu Tsai | 0b04ddf | 2014-11-07 12:15:47 +0800 | [diff] [blame] | 875 | /* |
| 876 | * The A23 only has 8 physical channels, a maximum DRQ port id of 24, |
| 877 | * and a total of 37 usable source and destination endpoints. |
| 878 | */ |
| 879 | |
| 880 | static struct sun6i_dma_config sun8i_a23_dma_cfg = { |
| 881 | .nr_max_channels = 8, |
| 882 | .nr_max_requests = 24, |
| 883 | .nr_max_vchans = 37, |
| 884 | }; |
| 885 | |
Jens Kuske | f008db8 | 2015-05-06 11:31:31 +0200 | [diff] [blame] | 886 | /* |
| 887 | * The H3 has 12 physical channels, a maximum DRQ port id of 27, |
| 888 | * and a total of 34 usable source and destination endpoints. |
| 889 | */ |
| 890 | |
| 891 | static struct sun6i_dma_config sun8i_h3_dma_cfg = { |
| 892 | .nr_max_channels = 12, |
| 893 | .nr_max_requests = 27, |
| 894 | .nr_max_vchans = 34, |
| 895 | }; |
| 896 | |
Fabian Frederick | 57c0342 | 2015-03-16 20:17:14 +0100 | [diff] [blame] | 897 | static const struct of_device_id sun6i_dma_match[] = { |
Chen-Yu Tsai | 25a37c2 | 2014-11-07 12:15:46 +0800 | [diff] [blame] | 898 | { .compatible = "allwinner,sun6i-a31-dma", .data = &sun6i_a31_dma_cfg }, |
Chen-Yu Tsai | 0b04ddf | 2014-11-07 12:15:47 +0800 | [diff] [blame] | 899 | { .compatible = "allwinner,sun8i-a23-dma", .data = &sun8i_a23_dma_cfg }, |
Jens Kuske | f008db8 | 2015-05-06 11:31:31 +0200 | [diff] [blame] | 900 | { .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg }, |
Chen-Yu Tsai | 25a37c2 | 2014-11-07 12:15:46 +0800 | [diff] [blame] | 901 | { /* sentinel */ } |
| 902 | }; |
Luis de Bethencourt | c719d7f | 2015-09-16 22:59:31 +0200 | [diff] [blame] | 903 | MODULE_DEVICE_TABLE(of, sun6i_dma_match); |
Chen-Yu Tsai | 25a37c2 | 2014-11-07 12:15:46 +0800 | [diff] [blame] | 904 | |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 905 | static int sun6i_dma_probe(struct platform_device *pdev) |
| 906 | { |
Chen-Yu Tsai | 25a37c2 | 2014-11-07 12:15:46 +0800 | [diff] [blame] | 907 | const struct of_device_id *device; |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 908 | struct sun6i_dma_dev *sdc; |
| 909 | struct resource *res; |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 910 | int ret, i; |
| 911 | |
| 912 | sdc = devm_kzalloc(&pdev->dev, sizeof(*sdc), GFP_KERNEL); |
| 913 | if (!sdc) |
| 914 | return -ENOMEM; |
| 915 | |
Chen-Yu Tsai | 25a37c2 | 2014-11-07 12:15:46 +0800 | [diff] [blame] | 916 | device = of_match_device(sun6i_dma_match, &pdev->dev); |
| 917 | if (!device) |
| 918 | return -ENODEV; |
| 919 | sdc->cfg = device->data; |
| 920 | |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 921 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 922 | sdc->base = devm_ioremap_resource(&pdev->dev, res); |
| 923 | if (IS_ERR(sdc->base)) |
| 924 | return PTR_ERR(sdc->base); |
| 925 | |
| 926 | sdc->irq = platform_get_irq(pdev, 0); |
| 927 | if (sdc->irq < 0) { |
| 928 | dev_err(&pdev->dev, "Cannot claim IRQ\n"); |
| 929 | return sdc->irq; |
| 930 | } |
| 931 | |
| 932 | sdc->clk = devm_clk_get(&pdev->dev, NULL); |
| 933 | if (IS_ERR(sdc->clk)) { |
| 934 | dev_err(&pdev->dev, "No clock specified\n"); |
| 935 | return PTR_ERR(sdc->clk); |
| 936 | } |
| 937 | |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 938 | sdc->rstc = devm_reset_control_get(&pdev->dev, NULL); |
| 939 | if (IS_ERR(sdc->rstc)) { |
| 940 | dev_err(&pdev->dev, "No reset controller specified\n"); |
| 941 | return PTR_ERR(sdc->rstc); |
| 942 | } |
| 943 | |
| 944 | sdc->pool = dmam_pool_create(dev_name(&pdev->dev), &pdev->dev, |
| 945 | sizeof(struct sun6i_dma_lli), 4, 0); |
| 946 | if (!sdc->pool) { |
| 947 | dev_err(&pdev->dev, "No memory for descriptors dma pool\n"); |
| 948 | return -ENOMEM; |
| 949 | } |
| 950 | |
| 951 | platform_set_drvdata(pdev, sdc); |
| 952 | INIT_LIST_HEAD(&sdc->pending); |
| 953 | spin_lock_init(&sdc->lock); |
| 954 | |
| 955 | dma_cap_set(DMA_PRIVATE, sdc->slave.cap_mask); |
| 956 | dma_cap_set(DMA_MEMCPY, sdc->slave.cap_mask); |
| 957 | dma_cap_set(DMA_SLAVE, sdc->slave.cap_mask); |
| 958 | |
| 959 | INIT_LIST_HEAD(&sdc->slave.channels); |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 960 | sdc->slave.device_free_chan_resources = sun6i_dma_free_chan_resources; |
| 961 | sdc->slave.device_tx_status = sun6i_dma_tx_status; |
| 962 | sdc->slave.device_issue_pending = sun6i_dma_issue_pending; |
| 963 | sdc->slave.device_prep_slave_sg = sun6i_dma_prep_slave_sg; |
| 964 | sdc->slave.device_prep_dma_memcpy = sun6i_dma_prep_dma_memcpy; |
Maxime Ripard | 77a68e5 | 2015-07-20 10:41:32 +0200 | [diff] [blame] | 965 | sdc->slave.copy_align = DMAENGINE_ALIGN_4_BYTES; |
Maxime Ripard | 826b15a | 2014-11-17 14:42:35 +0100 | [diff] [blame] | 966 | sdc->slave.device_config = sun6i_dma_config; |
| 967 | sdc->slave.device_pause = sun6i_dma_pause; |
| 968 | sdc->slave.device_resume = sun6i_dma_resume; |
| 969 | sdc->slave.device_terminate_all = sun6i_dma_terminate_all; |
Maxime Ripard | 1cac81b | 2014-11-17 14:42:52 +0100 | [diff] [blame] | 970 | sdc->slave.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | |
| 971 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | |
| 972 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); |
| 973 | sdc->slave.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | |
| 974 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | |
| 975 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); |
| 976 | sdc->slave.directions = BIT(DMA_DEV_TO_MEM) | |
| 977 | BIT(DMA_MEM_TO_DEV); |
| 978 | sdc->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 979 | sdc->slave.dev = &pdev->dev; |
| 980 | |
Chen-Yu Tsai | 25a37c2 | 2014-11-07 12:15:46 +0800 | [diff] [blame] | 981 | sdc->pchans = devm_kcalloc(&pdev->dev, sdc->cfg->nr_max_channels, |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 982 | sizeof(struct sun6i_pchan), GFP_KERNEL); |
| 983 | if (!sdc->pchans) |
| 984 | return -ENOMEM; |
| 985 | |
Chen-Yu Tsai | 25a37c2 | 2014-11-07 12:15:46 +0800 | [diff] [blame] | 986 | sdc->vchans = devm_kcalloc(&pdev->dev, sdc->cfg->nr_max_vchans, |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 987 | sizeof(struct sun6i_vchan), GFP_KERNEL); |
| 988 | if (!sdc->vchans) |
| 989 | return -ENOMEM; |
| 990 | |
| 991 | tasklet_init(&sdc->task, sun6i_dma_tasklet, (unsigned long)sdc); |
| 992 | |
Chen-Yu Tsai | 25a37c2 | 2014-11-07 12:15:46 +0800 | [diff] [blame] | 993 | for (i = 0; i < sdc->cfg->nr_max_channels; i++) { |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 994 | struct sun6i_pchan *pchan = &sdc->pchans[i]; |
| 995 | |
| 996 | pchan->idx = i; |
| 997 | pchan->base = sdc->base + 0x100 + i * 0x40; |
| 998 | } |
| 999 | |
Chen-Yu Tsai | 25a37c2 | 2014-11-07 12:15:46 +0800 | [diff] [blame] | 1000 | for (i = 0; i < sdc->cfg->nr_max_vchans; i++) { |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 1001 | struct sun6i_vchan *vchan = &sdc->vchans[i]; |
| 1002 | |
| 1003 | INIT_LIST_HEAD(&vchan->node); |
| 1004 | vchan->vc.desc_free = sun6i_dma_free_desc; |
| 1005 | vchan_init(&vchan->vc, &sdc->slave); |
| 1006 | } |
| 1007 | |
| 1008 | ret = reset_control_deassert(sdc->rstc); |
| 1009 | if (ret) { |
| 1010 | dev_err(&pdev->dev, "Couldn't deassert the device from reset\n"); |
| 1011 | goto err_chan_free; |
| 1012 | } |
| 1013 | |
| 1014 | ret = clk_prepare_enable(sdc->clk); |
| 1015 | if (ret) { |
| 1016 | dev_err(&pdev->dev, "Couldn't enable the clock\n"); |
| 1017 | goto err_reset_assert; |
| 1018 | } |
| 1019 | |
| 1020 | ret = devm_request_irq(&pdev->dev, sdc->irq, sun6i_dma_interrupt, 0, |
| 1021 | dev_name(&pdev->dev), sdc); |
| 1022 | if (ret) { |
| 1023 | dev_err(&pdev->dev, "Cannot request IRQ\n"); |
| 1024 | goto err_clk_disable; |
| 1025 | } |
| 1026 | |
| 1027 | ret = dma_async_device_register(&sdc->slave); |
| 1028 | if (ret) { |
| 1029 | dev_warn(&pdev->dev, "Failed to register DMA engine device\n"); |
| 1030 | goto err_irq_disable; |
| 1031 | } |
| 1032 | |
| 1033 | ret = of_dma_controller_register(pdev->dev.of_node, sun6i_dma_of_xlate, |
| 1034 | sdc); |
| 1035 | if (ret) { |
| 1036 | dev_err(&pdev->dev, "of_dma_controller_register failed\n"); |
| 1037 | goto err_dma_unregister; |
| 1038 | } |
| 1039 | |
Chen-Yu Tsai | 0b04ddf | 2014-11-07 12:15:47 +0800 | [diff] [blame] | 1040 | /* |
| 1041 | * sun8i variant requires us to toggle a dma gating register, |
| 1042 | * as seen in Allwinner's SDK. This register is not documented |
| 1043 | * in the A23 user manual. |
| 1044 | */ |
| 1045 | if (of_device_is_compatible(pdev->dev.of_node, |
| 1046 | "allwinner,sun8i-a23-dma")) |
| 1047 | writel(SUN8I_DMA_GATE_ENABLE, sdc->base + SUN8I_DMA_GATE); |
| 1048 | |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 1049 | return 0; |
| 1050 | |
| 1051 | err_dma_unregister: |
| 1052 | dma_async_device_unregister(&sdc->slave); |
| 1053 | err_irq_disable: |
| 1054 | sun6i_kill_tasklet(sdc); |
| 1055 | err_clk_disable: |
| 1056 | clk_disable_unprepare(sdc->clk); |
| 1057 | err_reset_assert: |
| 1058 | reset_control_assert(sdc->rstc); |
| 1059 | err_chan_free: |
| 1060 | sun6i_dma_free(sdc); |
| 1061 | return ret; |
| 1062 | } |
| 1063 | |
| 1064 | static int sun6i_dma_remove(struct platform_device *pdev) |
| 1065 | { |
| 1066 | struct sun6i_dma_dev *sdc = platform_get_drvdata(pdev); |
| 1067 | |
| 1068 | of_dma_controller_free(pdev->dev.of_node); |
| 1069 | dma_async_device_unregister(&sdc->slave); |
| 1070 | |
| 1071 | sun6i_kill_tasklet(sdc); |
| 1072 | |
| 1073 | clk_disable_unprepare(sdc->clk); |
| 1074 | reset_control_assert(sdc->rstc); |
| 1075 | |
| 1076 | sun6i_dma_free(sdc); |
| 1077 | |
| 1078 | return 0; |
| 1079 | } |
| 1080 | |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 1081 | static struct platform_driver sun6i_dma_driver = { |
| 1082 | .probe = sun6i_dma_probe, |
| 1083 | .remove = sun6i_dma_remove, |
| 1084 | .driver = { |
| 1085 | .name = "sun6i-dma", |
| 1086 | .of_match_table = sun6i_dma_match, |
| 1087 | }, |
| 1088 | }; |
| 1089 | module_platform_driver(sun6i_dma_driver); |
| 1090 | |
| 1091 | MODULE_DESCRIPTION("Allwinner A31 DMA Controller Driver"); |
| 1092 | MODULE_AUTHOR("Sugar <shuge@allwinnertech.com>"); |
| 1093 | MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); |
| 1094 | MODULE_LICENSE("GPL"); |