Catalin Marinas | 08e875c | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 ARM Ltd. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License |
| 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 15 | */ |
| 16 | #ifndef __ASM_SPINLOCK_H |
| 17 | #define __ASM_SPINLOCK_H |
| 18 | |
| 19 | #include <asm/spinlock_types.h> |
| 20 | #include <asm/processor.h> |
| 21 | |
| 22 | /* |
| 23 | * Spinlock implementation. |
| 24 | * |
Catalin Marinas | 08e875c | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 25 | * The memory barriers are implicit with the load-acquire and store-release |
| 26 | * instructions. |
Catalin Marinas | 08e875c | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 27 | */ |
| 28 | |
Catalin Marinas | 08e875c | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 29 | #define arch_spin_unlock_wait(lock) \ |
| 30 | do { while (arch_spin_is_locked(lock)) cpu_relax(); } while (0) |
| 31 | |
| 32 | #define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock) |
| 33 | |
| 34 | static inline void arch_spin_lock(arch_spinlock_t *lock) |
| 35 | { |
| 36 | unsigned int tmp; |
Will Deacon | 52ea2a5 | 2013-10-09 15:54:26 +0100 | [diff] [blame^] | 37 | arch_spinlock_t lockval, newval; |
Catalin Marinas | 08e875c | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 38 | |
| 39 | asm volatile( |
Will Deacon | 52ea2a5 | 2013-10-09 15:54:26 +0100 | [diff] [blame^] | 40 | /* Atomically increment the next ticket. */ |
| 41 | " prfm pstl1strm, %3\n" |
| 42 | "1: ldaxr %w0, %3\n" |
| 43 | " add %w1, %w0, %w5\n" |
| 44 | " stxr %w2, %w1, %3\n" |
| 45 | " cbnz %w2, 1b\n" |
| 46 | /* Did we get the lock? */ |
| 47 | " eor %w1, %w0, %w0, ror #16\n" |
| 48 | " cbz %w1, 3f\n" |
| 49 | /* |
| 50 | * No: spin on the owner. Send a local event to avoid missing an |
| 51 | * unlock before the exclusive load. |
| 52 | */ |
| 53 | " sevl\n" |
| 54 | "2: wfe\n" |
| 55 | " ldaxrh %w2, %4\n" |
| 56 | " eor %w1, %w2, %w0, lsr #16\n" |
| 57 | " cbnz %w1, 2b\n" |
| 58 | /* We got the lock. Critical section starts here. */ |
| 59 | "3:" |
| 60 | : "=&r" (lockval), "=&r" (newval), "=&r" (tmp), "+Q" (*lock) |
| 61 | : "Q" (lock->owner), "I" (1 << TICKET_SHIFT) |
| 62 | : "memory"); |
Catalin Marinas | 08e875c | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 63 | } |
| 64 | |
| 65 | static inline int arch_spin_trylock(arch_spinlock_t *lock) |
| 66 | { |
| 67 | unsigned int tmp; |
Will Deacon | 52ea2a5 | 2013-10-09 15:54:26 +0100 | [diff] [blame^] | 68 | arch_spinlock_t lockval; |
Catalin Marinas | 08e875c | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 69 | |
| 70 | asm volatile( |
Will Deacon | 52ea2a5 | 2013-10-09 15:54:26 +0100 | [diff] [blame^] | 71 | " prfm pstl1strm, %2\n" |
| 72 | "1: ldaxr %w0, %2\n" |
| 73 | " eor %w1, %w0, %w0, ror #16\n" |
| 74 | " cbnz %w1, 2f\n" |
| 75 | " add %w0, %w0, %3\n" |
| 76 | " stxr %w1, %w0, %2\n" |
| 77 | " cbnz %w1, 1b\n" |
| 78 | "2:" |
| 79 | : "=&r" (lockval), "=&r" (tmp), "+Q" (*lock) |
| 80 | : "I" (1 << TICKET_SHIFT) |
| 81 | : "memory"); |
Catalin Marinas | 08e875c | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 82 | |
| 83 | return !tmp; |
| 84 | } |
| 85 | |
| 86 | static inline void arch_spin_unlock(arch_spinlock_t *lock) |
| 87 | { |
| 88 | asm volatile( |
Will Deacon | 52ea2a5 | 2013-10-09 15:54:26 +0100 | [diff] [blame^] | 89 | " stlrh %w1, %0\n" |
| 90 | : "=Q" (lock->owner) |
| 91 | : "r" (lock->owner + 1) |
| 92 | : "memory"); |
Catalin Marinas | 08e875c | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 93 | } |
| 94 | |
Will Deacon | 52ea2a5 | 2013-10-09 15:54:26 +0100 | [diff] [blame^] | 95 | static inline int arch_spin_is_locked(arch_spinlock_t *lock) |
| 96 | { |
| 97 | arch_spinlock_t lockval = ACCESS_ONCE(*lock); |
| 98 | return lockval.owner != lockval.next; |
| 99 | } |
| 100 | |
| 101 | static inline int arch_spin_is_contended(arch_spinlock_t *lock) |
| 102 | { |
| 103 | arch_spinlock_t lockval = ACCESS_ONCE(*lock); |
| 104 | return (lockval.next - lockval.owner) > 1; |
| 105 | } |
| 106 | #define arch_spin_is_contended arch_spin_is_contended |
| 107 | |
Catalin Marinas | 08e875c | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 108 | /* |
| 109 | * Write lock implementation. |
| 110 | * |
| 111 | * Write locks set bit 31. Unlocking, is done by writing 0 since the lock is |
| 112 | * exclusively held. |
| 113 | * |
| 114 | * The memory barriers are implicit with the load-acquire and store-release |
| 115 | * instructions. |
| 116 | */ |
| 117 | |
| 118 | static inline void arch_write_lock(arch_rwlock_t *rw) |
| 119 | { |
| 120 | unsigned int tmp; |
| 121 | |
| 122 | asm volatile( |
| 123 | " sevl\n" |
| 124 | "1: wfe\n" |
Will Deacon | 3a0310e | 2013-02-04 12:12:33 +0000 | [diff] [blame] | 125 | "2: ldaxr %w0, %1\n" |
Catalin Marinas | 08e875c | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 126 | " cbnz %w0, 1b\n" |
Will Deacon | 3a0310e | 2013-02-04 12:12:33 +0000 | [diff] [blame] | 127 | " stxr %w0, %w2, %1\n" |
Catalin Marinas | 08e875c | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 128 | " cbnz %w0, 2b\n" |
Will Deacon | 3a0310e | 2013-02-04 12:12:33 +0000 | [diff] [blame] | 129 | : "=&r" (tmp), "+Q" (rw->lock) |
| 130 | : "r" (0x80000000) |
| 131 | : "cc", "memory"); |
Catalin Marinas | 08e875c | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 132 | } |
| 133 | |
| 134 | static inline int arch_write_trylock(arch_rwlock_t *rw) |
| 135 | { |
| 136 | unsigned int tmp; |
| 137 | |
| 138 | asm volatile( |
Will Deacon | 3a0310e | 2013-02-04 12:12:33 +0000 | [diff] [blame] | 139 | " ldaxr %w0, %1\n" |
Catalin Marinas | 08e875c | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 140 | " cbnz %w0, 1f\n" |
Will Deacon | 3a0310e | 2013-02-04 12:12:33 +0000 | [diff] [blame] | 141 | " stxr %w0, %w2, %1\n" |
Catalin Marinas | 08e875c | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 142 | "1:\n" |
Will Deacon | 3a0310e | 2013-02-04 12:12:33 +0000 | [diff] [blame] | 143 | : "=&r" (tmp), "+Q" (rw->lock) |
| 144 | : "r" (0x80000000) |
| 145 | : "cc", "memory"); |
Catalin Marinas | 08e875c | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 146 | |
| 147 | return !tmp; |
| 148 | } |
| 149 | |
| 150 | static inline void arch_write_unlock(arch_rwlock_t *rw) |
| 151 | { |
| 152 | asm volatile( |
Will Deacon | 3a0310e | 2013-02-04 12:12:33 +0000 | [diff] [blame] | 153 | " stlr %w1, %0\n" |
| 154 | : "=Q" (rw->lock) : "r" (0) : "memory"); |
Catalin Marinas | 08e875c | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 155 | } |
| 156 | |
| 157 | /* write_can_lock - would write_trylock() succeed? */ |
| 158 | #define arch_write_can_lock(x) ((x)->lock == 0) |
| 159 | |
| 160 | /* |
| 161 | * Read lock implementation. |
| 162 | * |
| 163 | * It exclusively loads the lock value, increments it and stores the new value |
| 164 | * back if positive and the CPU still exclusively owns the location. If the |
| 165 | * value is negative, the lock is already held. |
| 166 | * |
| 167 | * During unlocking there may be multiple active read locks but no write lock. |
| 168 | * |
| 169 | * The memory barriers are implicit with the load-acquire and store-release |
| 170 | * instructions. |
| 171 | */ |
| 172 | static inline void arch_read_lock(arch_rwlock_t *rw) |
| 173 | { |
| 174 | unsigned int tmp, tmp2; |
| 175 | |
| 176 | asm volatile( |
| 177 | " sevl\n" |
| 178 | "1: wfe\n" |
Will Deacon | 3a0310e | 2013-02-04 12:12:33 +0000 | [diff] [blame] | 179 | "2: ldaxr %w0, %2\n" |
Catalin Marinas | 08e875c | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 180 | " add %w0, %w0, #1\n" |
| 181 | " tbnz %w0, #31, 1b\n" |
Will Deacon | 3a0310e | 2013-02-04 12:12:33 +0000 | [diff] [blame] | 182 | " stxr %w1, %w0, %2\n" |
Catalin Marinas | 08e875c | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 183 | " cbnz %w1, 2b\n" |
Will Deacon | 3a0310e | 2013-02-04 12:12:33 +0000 | [diff] [blame] | 184 | : "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock) |
| 185 | : |
| 186 | : "cc", "memory"); |
Catalin Marinas | 08e875c | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 187 | } |
| 188 | |
| 189 | static inline void arch_read_unlock(arch_rwlock_t *rw) |
| 190 | { |
| 191 | unsigned int tmp, tmp2; |
| 192 | |
| 193 | asm volatile( |
Will Deacon | 3a0310e | 2013-02-04 12:12:33 +0000 | [diff] [blame] | 194 | "1: ldxr %w0, %2\n" |
Catalin Marinas | 08e875c | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 195 | " sub %w0, %w0, #1\n" |
Will Deacon | 3a0310e | 2013-02-04 12:12:33 +0000 | [diff] [blame] | 196 | " stlxr %w1, %w0, %2\n" |
Catalin Marinas | 08e875c | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 197 | " cbnz %w1, 1b\n" |
Will Deacon | 3a0310e | 2013-02-04 12:12:33 +0000 | [diff] [blame] | 198 | : "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock) |
| 199 | : |
| 200 | : "cc", "memory"); |
Catalin Marinas | 08e875c | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 201 | } |
| 202 | |
| 203 | static inline int arch_read_trylock(arch_rwlock_t *rw) |
| 204 | { |
| 205 | unsigned int tmp, tmp2 = 1; |
| 206 | |
| 207 | asm volatile( |
Will Deacon | 3a0310e | 2013-02-04 12:12:33 +0000 | [diff] [blame] | 208 | " ldaxr %w0, %2\n" |
Catalin Marinas | 08e875c | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 209 | " add %w0, %w0, #1\n" |
| 210 | " tbnz %w0, #31, 1f\n" |
Will Deacon | 3a0310e | 2013-02-04 12:12:33 +0000 | [diff] [blame] | 211 | " stxr %w1, %w0, %2\n" |
Catalin Marinas | 08e875c | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 212 | "1:\n" |
Will Deacon | 3a0310e | 2013-02-04 12:12:33 +0000 | [diff] [blame] | 213 | : "=&r" (tmp), "+r" (tmp2), "+Q" (rw->lock) |
| 214 | : |
| 215 | : "cc", "memory"); |
Catalin Marinas | 08e875c | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 216 | |
| 217 | return !tmp2; |
| 218 | } |
| 219 | |
| 220 | /* read_can_lock - would read_trylock() succeed? */ |
| 221 | #define arch_read_can_lock(x) ((x)->lock < 0x80000000) |
| 222 | |
| 223 | #define arch_read_lock_flags(lock, flags) arch_read_lock(lock) |
| 224 | #define arch_write_lock_flags(lock, flags) arch_write_lock(lock) |
| 225 | |
| 226 | #define arch_spin_relax(lock) cpu_relax() |
| 227 | #define arch_read_relax(lock) cpu_relax() |
| 228 | #define arch_write_relax(lock) cpu_relax() |
| 229 | |
| 230 | #endif /* __ASM_SPINLOCK_H */ |