Blame - drivers/net/sunhme.h - kernel/msm-4.9

Linus Torvalds

1da177e

2005-04-16 15:20:36 -0700

[diff] [blame]

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/* $Id: sunhme.h,v 1.33 2001/08/03 06:23:04 davem Exp $

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* sunhme.h: Definitions for Sparc HME/BigMac 10/100baseT ethernet driver.

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* Also known as the "Happy Meal".

*

*/

#ifndef _SUNHME_H

#define _SUNHME_H

#include <linux/config.h>

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#include <linux/pci.h>

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/* Happy Meal global registers. */

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#define GREG_SWRESET 0x000UL /* Software Reset */

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#define GREG_CFG 0x004UL /* Config Register */

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#define GREG_STAT 0x108UL /* Status */

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#define GREG_IMASK 0x10cUL /* Interrupt Mask */

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#define GREG_REG_SIZE 0x110UL

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/* Global reset register. */

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#define GREG_RESET_ETX 0x01

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#define GREG_RESET_ERX 0x02

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#define GREG_RESET_ALL 0x03

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/* Global config register. */

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#define GREG_CFG_BURSTMSK 0x03

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#define GREG_CFG_BURST16 0x00

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#define GREG_CFG_BURST32 0x01

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#define GREG_CFG_BURST64 0x02

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#define GREG_CFG_64BIT 0x04

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#define GREG_CFG_PARITY 0x08

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#define GREG_CFG_RESV 0x10

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/* Global status register. */

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#define GREG_STAT_GOTFRAME 0x00000001 /* Received a frame */

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#define GREG_STAT_RCNTEXP 0x00000002 /* Receive frame counter expired */

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#define GREG_STAT_ACNTEXP 0x00000004 /* Align-error counter expired */

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#define GREG_STAT_CCNTEXP 0x00000008 /* CRC-error counter expired */

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#define GREG_STAT_LCNTEXP 0x00000010 /* Length-error counter expired */

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#define GREG_STAT_RFIFOVF 0x00000020 /* Receive FIFO overflow */

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#define GREG_STAT_CVCNTEXP 0x00000040 /* Code-violation counter expired */

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#define GREG_STAT_STSTERR 0x00000080 /* Test error in XIF for SQE */

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#define GREG_STAT_SENTFRAME 0x00000100 /* Transmitted a frame */

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#define GREG_STAT_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */

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#define GREG_STAT_MAXPKTERR 0x00000400 /* Max-packet size error */

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#define GREG_STAT_NCNTEXP 0x00000800 /* Normal-collision counter expired */

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#define GREG_STAT_ECNTEXP 0x00001000 /* Excess-collision counter expired */

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#define GREG_STAT_LCCNTEXP 0x00002000 /* Late-collision counter expired */

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#define GREG_STAT_FCNTEXP 0x00004000 /* First-collision counter expired */

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#define GREG_STAT_DTIMEXP 0x00008000 /* Defer-timer expired */

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#define GREG_STAT_RXTOHOST 0x00010000 /* Moved from receive-FIFO to host memory */

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#define GREG_STAT_NORXD 0x00020000 /* No more receive descriptors */

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#define GREG_STAT_RXERR 0x00040000 /* Error during receive dma */

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#define GREG_STAT_RXLATERR 0x00080000 /* Late error during receive dma */

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#define GREG_STAT_RXPERR 0x00100000 /* Parity error during receive dma */

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#define GREG_STAT_RXTERR 0x00200000 /* Tag error during receive dma */

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#define GREG_STAT_EOPERR 0x00400000 /* Transmit descriptor did not have EOP set */

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#define GREG_STAT_MIFIRQ 0x00800000 /* MIF is signaling an interrupt condition */

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#define GREG_STAT_HOSTTOTX 0x01000000 /* Moved from host memory to transmit-FIFO */

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#define GREG_STAT_TXALL 0x02000000 /* Transmitted all packets in the tx-fifo */

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#define GREG_STAT_TXEACK 0x04000000 /* Error during transmit dma */

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#define GREG_STAT_TXLERR 0x08000000 /* Late error during transmit dma */

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#define GREG_STAT_TXPERR 0x10000000 /* Parity error during transmit dma */

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#define GREG_STAT_TXTERR 0x20000000 /* Tag error during transmit dma */

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#define GREG_STAT_SLVERR 0x40000000 /* PIO access got an error */

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#define GREG_STAT_SLVPERR 0x80000000 /* PIO access got a parity error */

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/* All interesting error conditions. */

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#define GREG_STAT_ERRORS 0xfc7efefc

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/* Global interrupt mask register. */

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#define GREG_IMASK_GOTFRAME 0x00000001 /* Received a frame */

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#define GREG_IMASK_RCNTEXP 0x00000002 /* Receive frame counter expired */

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#define GREG_IMASK_ACNTEXP 0x00000004 /* Align-error counter expired */

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#define GREG_IMASK_CCNTEXP 0x00000008 /* CRC-error counter expired */

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#define GREG_IMASK_LCNTEXP 0x00000010 /* Length-error counter expired */

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#define GREG_IMASK_RFIFOVF 0x00000020 /* Receive FIFO overflow */

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#define GREG_IMASK_CVCNTEXP 0x00000040 /* Code-violation counter expired */

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#define GREG_IMASK_STSTERR 0x00000080 /* Test error in XIF for SQE */

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#define GREG_IMASK_SENTFRAME 0x00000100 /* Transmitted a frame */

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#define GREG_IMASK_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */

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#define GREG_IMASK_MAXPKTERR 0x00000400 /* Max-packet size error */

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#define GREG_IMASK_NCNTEXP 0x00000800 /* Normal-collision counter expired */

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#define GREG_IMASK_ECNTEXP 0x00001000 /* Excess-collision counter expired */

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#define GREG_IMASK_LCCNTEXP 0x00002000 /* Late-collision counter expired */

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#define GREG_IMASK_FCNTEXP 0x00004000 /* First-collision counter expired */

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#define GREG_IMASK_DTIMEXP 0x00008000 /* Defer-timer expired */

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#define GREG_IMASK_RXTOHOST 0x00010000 /* Moved from receive-FIFO to host memory */

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#define GREG_IMASK_NORXD 0x00020000 /* No more receive descriptors */

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#define GREG_IMASK_RXERR 0x00040000 /* Error during receive dma */

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#define GREG_IMASK_RXLATERR 0x00080000 /* Late error during receive dma */

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#define GREG_IMASK_RXPERR 0x00100000 /* Parity error during receive dma */

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#define GREG_IMASK_RXTERR 0x00200000 /* Tag error during receive dma */

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#define GREG_IMASK_EOPERR 0x00400000 /* Transmit descriptor did not have EOP set */

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#define GREG_IMASK_MIFIRQ 0x00800000 /* MIF is signaling an interrupt condition */

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#define GREG_IMASK_HOSTTOTX 0x01000000 /* Moved from host memory to transmit-FIFO */

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#define GREG_IMASK_TXALL 0x02000000 /* Transmitted all packets in the tx-fifo */

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#define GREG_IMASK_TXEACK 0x04000000 /* Error during transmit dma */

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#define GREG_IMASK_TXLERR 0x08000000 /* Late error during transmit dma */

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#define GREG_IMASK_TXPERR 0x10000000 /* Parity error during transmit dma */

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#define GREG_IMASK_TXTERR 0x20000000 /* Tag error during transmit dma */

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#define GREG_IMASK_SLVERR 0x40000000 /* PIO access got an error */

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#define GREG_IMASK_SLVPERR 0x80000000 /* PIO access got a parity error */

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/* Happy Meal external transmitter registers. */

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#define ETX_PENDING 0x00UL /* Transmit pending/wakeup register */

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#define ETX_CFG 0x04UL /* Transmit config register */

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#define ETX_RING 0x08UL /* Transmit ring pointer */

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#define ETX_BBASE 0x0cUL /* Transmit buffer base */

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#define ETX_BDISP 0x10UL /* Transmit buffer displacement */

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#define ETX_FIFOWPTR 0x14UL /* FIFO write ptr */

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#define ETX_FIFOSWPTR 0x18UL /* FIFO write ptr (shadow register) */

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#define ETX_FIFORPTR 0x1cUL /* FIFO read ptr */

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#define ETX_FIFOSRPTR 0x20UL /* FIFO read ptr (shadow register) */

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#define ETX_FIFOPCNT 0x24UL /* FIFO packet counter */

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#define ETX_SMACHINE 0x28UL /* Transmitter state machine */

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#define ETX_RSIZE 0x2cUL /* Ring descriptor size */

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#define ETX_BPTR 0x30UL /* Transmit data buffer ptr */

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#define ETX_REG_SIZE 0x34UL

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/* ETX transmit pending register. */

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#define ETX_TP_DMAWAKEUP 0x00000001 /* Restart transmit dma */

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/* ETX config register. */

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#define ETX_CFG_DMAENABLE 0x00000001 /* Enable transmit dma */

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#define ETX_CFG_FIFOTHRESH 0x000003fe /* Transmit FIFO threshold */

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#define ETX_CFG_IRQDAFTER 0x00000400 /* Interrupt after TX-FIFO drained */

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#define ETX_CFG_IRQDBEFORE 0x00000000 /* Interrupt before TX-FIFO drained */

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#define ETX_RSIZE_SHIFT 4

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/* Happy Meal external receiver registers. */

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#define ERX_CFG 0x00UL /* Receiver config register */

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#define ERX_RING 0x04UL /* Receiver ring ptr */

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#define ERX_BPTR 0x08UL /* Receiver buffer ptr */

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#define ERX_FIFOWPTR 0x0cUL /* FIFO write ptr */

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#define ERX_FIFOSWPTR 0x10UL /* FIFO write ptr (shadow register) */

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#define ERX_FIFORPTR 0x14UL /* FIFO read ptr */

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#define ERX_FIFOSRPTR 0x18UL /* FIFO read ptr (shadow register) */

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#define ERX_SMACHINE 0x1cUL /* Receiver state machine */

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#define ERX_REG_SIZE 0x20UL

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/* ERX config register. */

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#define ERX_CFG_DMAENABLE 0x00000001 /* Enable receive DMA */

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#define ERX_CFG_RESV1 0x00000006 /* Unused... */

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#define ERX_CFG_BYTEOFFSET 0x00000038 /* Receive first byte offset */

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#define ERX_CFG_RESV2 0x000001c0 /* Unused... */

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#define ERX_CFG_SIZE32 0x00000000 /* Receive ring size == 32 */

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#define ERX_CFG_SIZE64 0x00000200 /* Receive ring size == 64 */

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#define ERX_CFG_SIZE128 0x00000400 /* Receive ring size == 128 */

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#define ERX_CFG_SIZE256 0x00000600 /* Receive ring size == 256 */

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#define ERX_CFG_RESV3 0x0000f800 /* Unused... */

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#define ERX_CFG_CSUMSTART 0x007f0000 /* Offset of checksum start,

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* in halfwords. */

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/* I'd like a Big Mac, small fries, small coke, and SparcLinux please. */

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#define BMAC_XIFCFG 0x0000UL /* XIF config register */

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/* 0x4-->0x204, reserved */

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#define BMAC_TXSWRESET 0x208UL /* Transmitter software reset */

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#define BMAC_TXCFG 0x20cUL /* Transmitter config register */

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#define BMAC_IGAP1 0x210UL /* Inter-packet gap 1 */

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#define BMAC_IGAP2 0x214UL /* Inter-packet gap 2 */

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#define BMAC_ALIMIT 0x218UL /* Transmit attempt limit */

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#define BMAC_STIME 0x21cUL /* Transmit slot time */

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#define BMAC_PLEN 0x220UL /* Size of transmit preamble */

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#define BMAC_PPAT 0x224UL /* Pattern for transmit preamble */

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#define BMAC_TXSDELIM 0x228UL /* Transmit delimiter */

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#define BMAC_JSIZE 0x22cUL /* Jam size */

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#define BMAC_TXMAX 0x230UL /* Transmit max pkt size */

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#define BMAC_TXMIN 0x234UL /* Transmit min pkt size */

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#define BMAC_PATTEMPT 0x238UL /* Count of transmit peak attempts */

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#define BMAC_DTCTR 0x23cUL /* Transmit defer timer */

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#define BMAC_NCCTR 0x240UL /* Transmit normal-collision counter */

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#define BMAC_FCCTR 0x244UL /* Transmit first-collision counter */

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#define BMAC_EXCTR 0x248UL /* Transmit excess-collision counter */

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#define BMAC_LTCTR 0x24cUL /* Transmit late-collision counter */

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#define BMAC_RSEED 0x250UL /* Transmit random number seed */

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#define BMAC_TXSMACHINE 0x254UL /* Transmit state machine */

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/* 0x258-->0x304, reserved */

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#define BMAC_RXSWRESET 0x308UL /* Receiver software reset */

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#define BMAC_RXCFG 0x30cUL /* Receiver config register */

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#define BMAC_RXMAX 0x310UL /* Receive max pkt size */

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#define BMAC_RXMIN 0x314UL /* Receive min pkt size */

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#define BMAC_MACADDR2 0x318UL /* Ether address register 2 */

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#define BMAC_MACADDR1 0x31cUL /* Ether address register 1 */

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#define BMAC_MACADDR0 0x320UL /* Ether address register 0 */

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#define BMAC_FRCTR 0x324UL /* Receive frame receive counter */

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#define BMAC_GLECTR 0x328UL /* Receive giant-length error counter */

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#define BMAC_UNALECTR 0x32cUL /* Receive unaligned error counter */

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#define BMAC_RCRCECTR 0x330UL /* Receive CRC error counter */

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#define BMAC_RXSMACHINE 0x334UL /* Receiver state machine */

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#define BMAC_RXCVALID 0x338UL /* Receiver code violation */

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/* 0x33c, reserved */

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#define BMAC_HTABLE3 0x340UL /* Hash table 3 */

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#define BMAC_HTABLE2 0x344UL /* Hash table 2 */

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#define BMAC_HTABLE1 0x348UL /* Hash table 1 */

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#define BMAC_HTABLE0 0x34cUL /* Hash table 0 */

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#define BMAC_AFILTER2 0x350UL /* Address filter 2 */

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#define BMAC_AFILTER1 0x354UL /* Address filter 1 */

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#define BMAC_AFILTER0 0x358UL /* Address filter 0 */

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#define BMAC_AFMASK 0x35cUL /* Address filter mask */

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#define BMAC_REG_SIZE 0x360UL

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/* BigMac XIF config register. */

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#define BIGMAC_XCFG_ODENABLE 0x00000001 /* Output driver enable */

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#define BIGMAC_XCFG_XLBACK 0x00000002 /* Loopback-mode XIF enable */

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#define BIGMAC_XCFG_MLBACK 0x00000004 /* Loopback-mode MII enable */

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#define BIGMAC_XCFG_MIIDISAB 0x00000008 /* MII receive buffer disable */

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#define BIGMAC_XCFG_SQENABLE 0x00000010 /* SQE test enable */

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#define BIGMAC_XCFG_SQETWIN 0x000003e0 /* SQE time window */

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#define BIGMAC_XCFG_LANCE 0x00000010 /* Lance mode enable */

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#define BIGMAC_XCFG_LIPG0 0x000003e0 /* Lance mode IPG0 */

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/* BigMac transmit config register. */

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#define BIGMAC_TXCFG_ENABLE 0x00000001 /* Enable the transmitter */

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#define BIGMAC_TXCFG_SMODE 0x00000020 /* Enable slow transmit mode */

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#define BIGMAC_TXCFG_CIGN 0x00000040 /* Ignore transmit collisions */

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#define BIGMAC_TXCFG_FCSOFF 0x00000080 /* Do not emit FCS */

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#define BIGMAC_TXCFG_DBACKOFF 0x00000100 /* Disable backoff */

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#define BIGMAC_TXCFG_FULLDPLX 0x00000200 /* Enable full-duplex */

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#define BIGMAC_TXCFG_DGIVEUP 0x00000400 /* Don't give up on transmits */

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/* BigMac receive config register. */

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#define BIGMAC_RXCFG_ENABLE 0x00000001 /* Enable the receiver */

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#define BIGMAC_RXCFG_PSTRIP 0x00000020 /* Pad byte strip enable */

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#define BIGMAC_RXCFG_PMISC 0x00000040 /* Enable promiscous mode */

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#define BIGMAC_RXCFG_DERR 0x00000080 /* Disable error checking */

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#define BIGMAC_RXCFG_DCRCS 0x00000100 /* Disable CRC stripping */

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#define BIGMAC_RXCFG_REJME 0x00000200 /* Reject packets addressed to me */

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#define BIGMAC_RXCFG_PGRP 0x00000400 /* Enable promisc group mode */

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#define BIGMAC_RXCFG_HENABLE 0x00000800 /* Enable the hash filter */

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#define BIGMAC_RXCFG_AENABLE 0x00001000 /* Enable the address filter */

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/* These are the "Management Interface" (ie. MIF) registers of the transceiver. */

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#define TCVR_BBCLOCK 0x00UL /* Bit bang clock register */

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#define TCVR_BBDATA 0x04UL /* Bit bang data register */

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#define TCVR_BBOENAB 0x08UL /* Bit bang output enable */

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#define TCVR_FRAME 0x0cUL /* Frame control/data register */

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#define TCVR_CFG 0x10UL /* MIF config register */

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#define TCVR_IMASK 0x14UL /* MIF interrupt mask */

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#define TCVR_STATUS 0x18UL /* MIF status */

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#define TCVR_SMACHINE 0x1cUL /* MIF state machine */

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#define TCVR_REG_SIZE 0x20UL

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/* Frame commands. */

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#define FRAME_WRITE 0x50020000

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#define FRAME_READ 0x60020000

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/* Transceiver config register */

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#define TCV_CFG_PSELECT 0x00000001 /* Select PHY */

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#define TCV_CFG_PENABLE 0x00000002 /* Enable MIF polling */

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#define TCV_CFG_BENABLE 0x00000004 /* Enable the "bit banger" oh baby */

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#define TCV_CFG_PREGADDR 0x000000f8 /* Address of poll register */

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#define TCV_CFG_MDIO0 0x00000100 /* MDIO zero, data/attached */

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#define TCV_CFG_MDIO1 0x00000200 /* MDIO one, data/attached */

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#define TCV_CFG_PDADDR 0x00007c00 /* Device PHY address polling */

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/* Here are some PHY addresses. */

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#define TCV_PADDR_ETX 0 /* Internal transceiver */

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#define TCV_PADDR_ITX 1 /* External transceiver */

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/* Transceiver status register */

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#define TCV_STAT_BASIC 0xffff0000 /* The "basic" part */

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#define TCV_STAT_NORMAL 0x0000ffff /* The "non-basic" part */

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/* Inside the Happy Meal transceiver is the physical layer, they use an

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* implementations for National Semiconductor, part number DP83840VCE.

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* You can retrieve the data sheets and programming docs for this beast

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* from http://www.national.com/

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*

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* The DP83840 is capable of both 10 and 100Mbps ethernet, in both

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* half and full duplex mode. It also supports auto negotiation.

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*

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* But.... THIS THING IS A PAIN IN THE ASS TO PROGRAM!

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* Debugging eeprom burnt code is more fun than programming this chip!

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*/

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/* Generic MII registers defined in linux/mii.h, these below

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* are DP83840 specific.

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*/

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#define DP83840_CSCONFIG 0x17 /* CS configuration */

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/* The Carrier Sense config register. */

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#define CSCONFIG_RESV1 0x0001 /* Unused... */

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#define CSCONFIG_LED4 0x0002 /* Pin for full-dplx LED4 */

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#define CSCONFIG_LED1 0x0004 /* Pin for conn-status LED1 */

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#define CSCONFIG_RESV2 0x0008 /* Unused... */

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#define CSCONFIG_TCVDISAB 0x0010 /* Turns off the transceiver */

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#define CSCONFIG_DFBYPASS 0x0020 /* Bypass disconnect function */

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#define CSCONFIG_GLFORCE 0x0040 /* Good link force for 100mbps */

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#define CSCONFIG_CLKTRISTATE 0x0080 /* Tristate 25m clock */

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#define CSCONFIG_RESV3 0x0700 /* Unused... */

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#define CSCONFIG_ENCODE 0x0800 /* 1=MLT-3, 0=binary */

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#define CSCONFIG_RENABLE 0x1000 /* Repeater mode enable */

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#define CSCONFIG_TCDISABLE 0x2000 /* Disable timeout counter */

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#define CSCONFIG_RESV4 0x4000 /* Unused... */

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#define CSCONFIG_NDISABLE 0x8000 /* Disable NRZI */

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/* Happy Meal descriptor rings and such.

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* All descriptor rings must be aligned on a 2K boundary.

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* All receive buffers must be 64 byte aligned.

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* Always write the address first before setting the ownership

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* bits to avoid races with the hardware scanning the ring.

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*/

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struct happy_meal_rxd {

u32 rx_flags;

u32 rx_addr;

};

#define RXFLAG_OWN 0x80000000 /* 1 = hardware, 0 = software */

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#define RXFLAG_OVERFLOW 0x40000000 /* 1 = buffer overflow */

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#define RXFLAG_SIZE 0x3fff0000 /* Size of the buffer */

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#define RXFLAG_CSUM 0x0000ffff /* HW computed checksum */

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struct happy_meal_txd {

u32 tx_flags;

u32 tx_addr;

};

#define TXFLAG_OWN 0x80000000 /* 1 = hardware, 0 = software */

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#define TXFLAG_SOP 0x40000000 /* 1 = start of packet */

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#define TXFLAG_EOP 0x20000000 /* 1 = end of packet */

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#define TXFLAG_CSENABLE 0x10000000 /* 1 = enable hw-checksums */

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#define TXFLAG_CSLOCATION 0x0ff00000 /* Where to stick the csum */

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#define TXFLAG_CSBUFBEGIN 0x000fc000 /* Where to begin checksum */

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#define TXFLAG_SIZE 0x00003fff /* Size of the packet */

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#define TX_RING_SIZE 32 /* Must be >16 and <255, multiple of 16 */

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#define RX_RING_SIZE 32 /* see ERX_CFG_SIZE* for possible values */

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#if (TX_RING_SIZE < 16 || TX_RING_SIZE > 256 || (TX_RING_SIZE % 16) != 0)

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#error TX_RING_SIZE holds illegal value

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#endif

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#define TX_RING_MAXSIZE 256

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#define RX_RING_MAXSIZE 256

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/* We use a 14 byte offset for checksum computation. */

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#if (RX_RING_SIZE == 32)

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#define ERX_CFG_DEFAULT(off) (ERX_CFG_DMAENABLE|((off)<<3)|ERX_CFG_SIZE32|((14/2)<<16))

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#else

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#if (RX_RING_SIZE == 64)

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#define ERX_CFG_DEFAULT(off) (ERX_CFG_DMAENABLE|((off)<<3)|ERX_CFG_SIZE64|((14/2)<<16))

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#else

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#if (RX_RING_SIZE == 128)

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#define ERX_CFG_DEFAULT(off) (ERX_CFG_DMAENABLE|((off)<<3)|ERX_CFG_SIZE128|((14/2)<<16))

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#else

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#if (RX_RING_SIZE == 256)

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#define ERX_CFG_DEFAULT(off) (ERX_CFG_DMAENABLE|((off)<<3)|ERX_CFG_SIZE256|((14/2)<<16))

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#else

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#error RX_RING_SIZE holds illegal value

#endif

#endif

#endif

#endif

#define NEXT_RX(num) (((num) + 1) & (RX_RING_SIZE - 1))

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#define NEXT_TX(num) (((num) + 1) & (TX_RING_SIZE - 1))

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#define PREV_RX(num) (((num) - 1) & (RX_RING_SIZE - 1))

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#define PREV_TX(num) (((num) - 1) & (TX_RING_SIZE - 1))

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#define TX_BUFFS_AVAIL(hp) \

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(((hp)->tx_old <= (hp)->tx_new) ? \

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(hp)->tx_old + (TX_RING_SIZE - 1) - (hp)->tx_new : \

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(hp)->tx_old - (hp)->tx_new - 1)

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#define RX_OFFSET 2

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#define RX_BUF_ALLOC_SIZE (1546 + RX_OFFSET + 64)

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#define RX_COPY_THRESHOLD 256

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struct hmeal_init_block {

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struct happy_meal_rxd happy_meal_rxd[RX_RING_MAXSIZE];

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struct happy_meal_txd happy_meal_txd[TX_RING_MAXSIZE];

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};

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#define hblock_offset(mem, elem) \

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((__u32)((unsigned long)(&(((struct hmeal_init_block *)0)->mem[elem]))))

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/* Now software state stuff. */

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enum happy_transceiver {

external = 0,

internal = 1,

none = 2,

};

/* Timer state engine. */

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enum happy_timer_state {

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arbwait = 0, /* Waiting for auto negotiation to complete. */

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lupwait = 1, /* Auto-neg complete, awaiting link-up status. */

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ltrywait = 2, /* Forcing try of all modes, from fastest to slowest. */

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asleep = 3, /* Time inactive. */

};

struct quattro;

/* Happy happy, joy joy! */

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struct happy_meal {

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void __iomem *gregs; /* Happy meal global registers */

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struct hmeal_init_block *happy_block; /* RX and TX descriptors (CPU addr) */

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#if defined(CONFIG_SBUS) && defined(CONFIG_PCI)

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u32 (*read_desc32)(u32 *);

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void (*write_txd)(struct happy_meal_txd *, u32, u32);

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void (*write_rxd)(struct happy_meal_rxd *, u32, u32);

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u32 (*dma_map)(void *, void *, long, int);

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void (*dma_unmap)(void *, u32, long, int);

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void (*dma_sync_for_cpu)(void *, u32, long, int);

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void (*dma_sync_for_device)(void *, u32, long, int);

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#endif

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/* This is either a sbus_dev or a pci_dev. */

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void *happy_dev;

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spinlock_t happy_lock;

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struct sk_buff *rx_skbs[RX_RING_SIZE];

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struct sk_buff *tx_skbs[TX_RING_SIZE];

420

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int rx_new, tx_new, rx_old, tx_old;

422

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struct net_device_stats net_stats; /* Statistical counters */

424

425

#if defined(CONFIG_SBUS) && defined(CONFIG_PCI)

426

u32 (*read32)(void __iomem *);

427

void (*write32)(void __iomem *, u32);

428

#endif

429

430

void __iomem *etxregs; /* External transmitter regs */

431

void __iomem *erxregs; /* External receiver regs */

432

void __iomem *bigmacregs; /* BIGMAC core regs */

433

void __iomem *tcvregs; /* MIF transceiver regs */

434

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dma_addr_t hblock_dvma; /* DVMA visible address happy block */

436

unsigned int happy_flags; /* Driver state flags */

437

enum happy_transceiver tcvr_type; /* Kind of transceiver in use */

438

unsigned int happy_bursts; /* Get your mind out of the gutter */

439

unsigned int paddr; /* PHY address for transceiver */

440

unsigned short hm_revision; /* Happy meal revision */

441

unsigned short sw_bmcr; /* SW copy of BMCR */

442

unsigned short sw_bmsr; /* SW copy of BMSR */

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unsigned short sw_physid1; /* SW copy of PHYSID1 */

444

unsigned short sw_physid2; /* SW copy of PHYSID2 */

445

unsigned short sw_advertise; /* SW copy of ADVERTISE */

446

unsigned short sw_lpa; /* SW copy of LPA */

447

unsigned short sw_expansion; /* SW copy of EXPANSION */

448

unsigned short sw_csconfig; /* SW copy of CSCONFIG */

449

unsigned int auto_speed; /* Auto-nego link speed */

450

unsigned int forced_speed; /* Force mode link speed */

451

unsigned int poll_data; /* MIF poll data */

452

unsigned int poll_flag; /* MIF poll flag */

453

unsigned int linkcheck; /* Have we checked the link yet? */

454

unsigned int lnkup; /* Is the link up as far as we know? */

455

unsigned int lnkdown; /* Trying to force the link down? */

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unsigned int lnkcnt; /* Counter for link-up attempts. */

457

struct timer_list happy_timer; /* To watch the link when coming up. */

458

enum happy_timer_state timer_state; /* State of the auto-neg timer. */

459

unsigned int timer_ticks; /* Number of clicks at each state. */

460

461

struct net_device *dev; /* Backpointer */

462

struct quattro *qfe_parent; /* For Quattro cards */

463

int qfe_ent; /* Which instance on quattro */

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struct happy_meal *next_module;

465

};

466

467

/* Here are the happy flags. */

468

#define HFLAG_POLL 0x00000001 /* We are doing MIF polling */

469

#define HFLAG_FENABLE 0x00000002 /* The MII frame is enabled */

470

#define HFLAG_LANCE 0x00000004 /* We are using lance-mode */

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#define HFLAG_RXENABLE 0x00000008 /* Receiver is enabled */

472

#define HFLAG_AUTO 0x00000010 /* Using auto-negotiation, 0 = force */

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#define HFLAG_FULL 0x00000020 /* Full duplex enable */

474

#define HFLAG_MACFULL 0x00000040 /* Using full duplex in the MAC */

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#define HFLAG_POLLENABLE 0x00000080 /* Actually try MIF polling */

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#define HFLAG_RXCV 0x00000100 /* XXX RXCV ENABLE */

477

#define HFLAG_INIT 0x00000200 /* Init called at least once */

478

#define HFLAG_LINKUP 0x00000400 /* 1 = Link is up */

479

#define HFLAG_PCI 0x00000800 /* PCI based Happy Meal */

480

#define HFLAG_QUATTRO 0x00001000 /* On QFE/Quattro card */

481

482

#define HFLAG_20_21 (HFLAG_POLLENABLE | HFLAG_FENABLE)

483

#define HFLAG_NOT_A0 (HFLAG_POLLENABLE | HFLAG_FENABLE | HFLAG_LANCE | HFLAG_RXCV)

484

485

/* Support for QFE/Quattro cards. */

486

struct quattro {

487

struct net_device *happy_meals[4];

488

489

/* This is either a sbus_dev or a pci_dev. */

490

void *quattro_dev;

491

492

struct quattro *next;

493

494

/* PROM ranges, if any. */

495

#ifdef CONFIG_SBUS

496

struct linux_prom_ranges ranges[8];

#endif

int nranges;

};

/* We use this to acquire receive skb's that we can DMA directly into. */

502

#define ALIGNED_RX_SKB_ADDR(addr) \

503

((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr))

504

#define happy_meal_alloc_skb(__length, __gfp_flags) \

505

({ struct sk_buff *__skb; \

506

__skb = alloc_skb((__length) + 64, (__gfp_flags)); \

507

if(__skb) { \

508

int __offset = (int) ALIGNED_RX_SKB_ADDR(__skb->data); \

509

if(__offset) \

510

skb_reserve(__skb, __offset); \

} \

__skb; \

})

#endif /* !(_SUNHME_H) */