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gerrit-public.fairphone.software / kernel / msm-4.9 / 539eb5bca02ff0b93e17f110ffec18c5b5e744ee / . / arch / arm / boot / dts / armada-370-xp.dtsi
blob: 70c35f8ccf90b1dbaf979e48deeb385829c8e985 [file] [log] [blame]
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200[diff] [blame]1/*
2 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 *
15 * This file contains the definitions that are common to the Armada
16 * 370 and Armada XP SoC.
17 */
18
19/include/ "skeleton.dtsi"
20
21/ {
22 model = "Marvell Armada 370 and XP SoC";
23 compatible = "marvell,armada_370_xp";
24
25 cpus {
26 cpu@0 {
27 compatible = "marvell,sheeva-v7";
28 };
29 };
30
31 mpic: interrupt-controller@d0020000 {
32 compatible = "marvell,mpic";
33 #interrupt-cells = <1>;
34 #address-cells = <1>;
35 #size-cells = <1>;
36 interrupt-controller;
37 };
38
39 soc {
40 #address-cells = <1>;
41 #size-cells = <1>;
42 compatible = "simple-bus";
43 interrupt-parent = <&mpic>;
44 ranges;
45
46 serial@d0012000 {
47 compatible = "ns16550";
48 reg = <0xd0012000 0x100>;
49 reg-shift = <2>;
50 interrupts = <41>;
51 status = "disabled";
52 };
53 serial@d0012100 {
54 compatible = "ns16550";
55 reg = <0xd0012100 0x100>;
56 reg-shift = <2>;
57 interrupts = <42>;
58 status = "disabled";
59 };
60
61 timer@d0020300 {
62 compatible = "marvell,armada-370-xp-timer";
63 reg = <0xd0020300 0x30>;
64 interrupts = <37>, <38>, <39>, <40>;
Gregory CLEMENT307c2bf2012-11-17 15:22:25 +0100[diff] [blame]65 clocks = <&coreclk 2>;
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200[diff] [blame]66 };
Thomas Petazzoni5b40bae2012-09-11 14:27:30 +0200[diff] [blame]67
68 addr-decoding@d0020000 {
69 compatible = "marvell,armada-addr-decoding-controller";
70 reg = <0xd0020000 0x258>;
71 };
Gregory CLEMENTa6a6de12012-10-26 14:30:47 +0200[diff] [blame]72
73 sata@d00a0000 {
74 compatible = "marvell,orion-sata";
75 reg = <0xd00a0000 0x2400>;
76 interrupts = <55>;
77 clocks = <&gateclk 15>, <&gateclk 30>;
78 clock-names = "0", "1";
79 status = "disabled";
80 };
81
Thomas Petazzoni323c1012012-09-04 15:06:43 +0200[diff] [blame]82 mdio {
83 #address-cells = <1>;
84 #size-cells = <0>;
85 compatible = "marvell,orion-mdio";
86 reg = <0xd0072004 0x4>;
87 };
88
89 ethernet@d0070000 {
90 compatible = "marvell,armada-370-neta";
91 reg = <0xd0070000 0x2500>;
92 interrupts = <8>;
Thomas Petazzoni4aa935a2012-11-19 14:18:09 +0100[diff] [blame]93 clocks = <&gateclk 4>;
Thomas Petazzoni323c1012012-09-04 15:06:43 +0200[diff] [blame]94 status = "disabled";
95 };
96
97 ethernet@d0074000 {
98 compatible = "marvell,armada-370-neta";
99 reg = <0xd0074000 0x2500>;
100 interrupts = <10>;
Thomas Petazzoni4aa935a2012-11-19 14:18:09 +0100[diff] [blame]101 clocks = <&gateclk 3>;
Thomas Petazzoni323c1012012-09-04 15:06:43 +0200[diff] [blame]102 status = "disabled";
103 };
Nobuhiro Iwamatsu539eb5b2012-10-30 19:41:23 +0900[diff] [blame^]104
105 i2c0: i2c@d0011000 {
106 compatible = "marvell,mv64xxx-i2c";
107 reg = <0xd0011000 0x20>;
108 #address-cells = <1>;
109 #size-cells = <0>;
110 interrupts = <31>;
111 timeout-ms = <1000>;
112 clocks = <&coreclk 0>;
113 status = "disabled";
114 };
115
116 i2c1: i2c@d0011100 {
117 compatible = "marvell,mv64xxx-i2c";
118 reg = <0xd0011100 0x20>;
119 #address-cells = <1>;
120 #size-cells = <0>;
121 interrupts = <32>;
122 timeout-ms = <1000>;
123 clocks = <&coreclk 0>;
124 status = "disabled";
125 };
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200[diff] [blame]126 };
127};
128