Nishanth Menon | a4240d3 | 2016-04-14 12:45:58 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
| 8 | /dts-v1/; |
| 9 | |
| 10 | #include "dra72x.dtsi" |
| 11 | #include <dt-bindings/gpio/gpio.h> |
| 12 | #include <dt-bindings/clk/ti-dra7-atl.h> |
| 13 | |
| 14 | / { |
| 15 | compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; |
| 16 | |
| 17 | aliases { |
| 18 | display0 = &hdmi0; |
| 19 | }; |
| 20 | |
Misael Lopez Cruz | 7172e74 | 2016-05-24 15:00:40 -0500 | [diff] [blame] | 21 | evm_3v3_sw: fixedregulator-evm_3v3 { |
Nishanth Menon | a4240d3 | 2016-04-14 12:45:58 -0500 | [diff] [blame] | 22 | compatible = "regulator-fixed"; |
| 23 | regulator-name = "evm_3v3"; |
| 24 | regulator-min-microvolt = <3300000>; |
| 25 | regulator-max-microvolt = <3300000>; |
| 26 | }; |
| 27 | |
| 28 | aic_dvdd: fixedregulator-aic_dvdd { |
| 29 | /* TPS77018DBVT */ |
| 30 | compatible = "regulator-fixed"; |
| 31 | regulator-name = "aic_dvdd"; |
Misael Lopez Cruz | 7172e74 | 2016-05-24 15:00:40 -0500 | [diff] [blame] | 32 | vin-supply = <&evm_3v3_sw>; |
Nishanth Menon | a4240d3 | 2016-04-14 12:45:58 -0500 | [diff] [blame] | 33 | regulator-min-microvolt = <1800000>; |
| 34 | regulator-max-microvolt = <1800000>; |
| 35 | }; |
| 36 | |
| 37 | evm_3v3_sd: fixedregulator-sd { |
| 38 | compatible = "regulator-fixed"; |
| 39 | regulator-name = "evm_3v3_sd"; |
| 40 | regulator-min-microvolt = <3300000>; |
| 41 | regulator-max-microvolt = <3300000>; |
| 42 | enable-active-high; |
| 43 | gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; |
| 44 | }; |
| 45 | |
| 46 | extcon_usb1: extcon_usb1 { |
| 47 | compatible = "linux,extcon-usb-gpio"; |
| 48 | id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; |
| 49 | }; |
| 50 | |
| 51 | extcon_usb2: extcon_usb2 { |
| 52 | compatible = "linux,extcon-usb-gpio"; |
| 53 | id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; |
| 54 | }; |
| 55 | |
| 56 | hdmi0: connector { |
| 57 | compatible = "hdmi-connector"; |
| 58 | label = "hdmi"; |
| 59 | |
| 60 | type = "a"; |
| 61 | |
| 62 | port { |
| 63 | hdmi_connector_in: endpoint { |
| 64 | remote-endpoint = <&tpd12s015_out>; |
| 65 | }; |
| 66 | }; |
| 67 | }; |
| 68 | |
| 69 | tpd12s015: encoder { |
| 70 | compatible = "ti,tpd12s015"; |
| 71 | |
| 72 | pinctrl-names = "default"; |
| 73 | pinctrl-0 = <&tpd12s015_pins>; |
| 74 | |
| 75 | gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ |
| 76 | <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ |
| 77 | <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ |
| 78 | |
| 79 | ports { |
| 80 | #address-cells = <1>; |
| 81 | #size-cells = <0>; |
| 82 | |
| 83 | port@0 { |
| 84 | reg = <0>; |
| 85 | |
| 86 | tpd12s015_in: endpoint { |
| 87 | remote-endpoint = <&hdmi_out>; |
| 88 | }; |
| 89 | }; |
| 90 | |
| 91 | port@1 { |
| 92 | reg = <1>; |
| 93 | |
| 94 | tpd12s015_out: endpoint { |
| 95 | remote-endpoint = <&hdmi_connector_in>; |
| 96 | }; |
| 97 | }; |
| 98 | }; |
| 99 | }; |
| 100 | |
| 101 | sound0: sound0 { |
| 102 | compatible = "simple-audio-card"; |
| 103 | simple-audio-card,name = "DRA7xx-EVM"; |
| 104 | simple-audio-card,widgets = |
| 105 | "Headphone", "Headphone Jack", |
| 106 | "Line", "Line Out", |
| 107 | "Microphone", "Mic Jack", |
| 108 | "Line", "Line In"; |
| 109 | simple-audio-card,routing = |
| 110 | "Headphone Jack", "HPLOUT", |
| 111 | "Headphone Jack", "HPROUT", |
| 112 | "Line Out", "LLOUT", |
| 113 | "Line Out", "RLOUT", |
| 114 | "MIC3L", "Mic Jack", |
| 115 | "MIC3R", "Mic Jack", |
| 116 | "Mic Jack", "Mic Bias", |
| 117 | "LINE1L", "Line In", |
| 118 | "LINE1R", "Line In"; |
| 119 | simple-audio-card,format = "dsp_b"; |
| 120 | simple-audio-card,bitclock-master = <&sound0_master>; |
| 121 | simple-audio-card,frame-master = <&sound0_master>; |
| 122 | simple-audio-card,bitclock-inversion; |
| 123 | |
| 124 | sound0_master: simple-audio-card,cpu { |
| 125 | sound-dai = <&mcasp3>; |
| 126 | system-clock-frequency = <5644800>; |
| 127 | }; |
| 128 | |
| 129 | simple-audio-card,codec { |
| 130 | sound-dai = <&tlv320aic3106>; |
| 131 | clocks = <&atl_clkin2_ck>; |
| 132 | }; |
| 133 | }; |
| 134 | }; |
| 135 | |
| 136 | &dra7_pmx_core { |
| 137 | i2c1_pins: pinmux_i2c1_pins { |
| 138 | pinctrl-single,pins = < |
| 139 | DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ |
| 140 | DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ |
| 141 | >; |
| 142 | }; |
| 143 | |
| 144 | i2c5_pins: pinmux_i2c5_pins { |
| 145 | pinctrl-single,pins = < |
| 146 | DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */ |
| 147 | DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */ |
| 148 | >; |
| 149 | }; |
| 150 | |
| 151 | i2c5_pins: pinmux_i2c5_pins { |
| 152 | pinctrl-single,pins = < |
| 153 | DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */ |
| 154 | DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */ |
| 155 | >; |
| 156 | }; |
| 157 | |
| 158 | nand_default: nand_default { |
| 159 | pinctrl-single,pins = < |
| 160 | DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ |
| 161 | DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ |
| 162 | DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ |
| 163 | DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ |
| 164 | DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ |
| 165 | DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ |
| 166 | DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ |
| 167 | DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ |
| 168 | DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ |
| 169 | DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ |
| 170 | DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ |
| 171 | DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ |
| 172 | DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ |
| 173 | DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ |
| 174 | DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ |
| 175 | DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ |
| 176 | DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */ |
| 177 | DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ |
| 178 | DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ |
| 179 | DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ |
| 180 | DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */ |
| 181 | DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */ |
| 182 | >; |
| 183 | }; |
| 184 | |
| 185 | usb1_pins: pinmux_usb1_pins { |
| 186 | pinctrl-single,pins = < |
| 187 | DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ |
| 188 | >; |
| 189 | }; |
| 190 | |
| 191 | usb2_pins: pinmux_usb2_pins { |
| 192 | pinctrl-single,pins = < |
| 193 | DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ |
| 194 | >; |
| 195 | }; |
| 196 | |
| 197 | tps65917_pins_default: tps65917_pins_default { |
| 198 | pinctrl-single,pins = < |
| 199 | DRA7XX_CORE_IOPAD(0x3824, PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */ |
| 200 | >; |
| 201 | }; |
| 202 | |
| 203 | mmc1_pins_default: mmc1_pins_default { |
| 204 | pinctrl-single,pins = < |
| 205 | DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ |
| 206 | DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ |
| 207 | DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ |
| 208 | DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ |
| 209 | DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ |
| 210 | DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ |
| 211 | DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ |
| 212 | >; |
| 213 | }; |
| 214 | |
| 215 | mmc2_pins_default: mmc2_pins_default { |
| 216 | pinctrl-single,pins = < |
| 217 | DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ |
| 218 | DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ |
| 219 | DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ |
| 220 | DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ |
| 221 | DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ |
| 222 | DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ |
| 223 | DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ |
| 224 | DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ |
| 225 | DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ |
| 226 | DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ |
| 227 | >; |
| 228 | }; |
| 229 | |
| 230 | dcan1_pins_default: dcan1_pins_default { |
| 231 | pinctrl-single,pins = < |
| 232 | DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ |
| 233 | DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ |
| 234 | >; |
| 235 | }; |
| 236 | |
| 237 | dcan1_pins_sleep: dcan1_pins_sleep { |
| 238 | pinctrl-single,pins = < |
| 239 | DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ |
| 240 | DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ |
| 241 | >; |
| 242 | }; |
| 243 | |
Nishanth Menon | a4240d3 | 2016-04-14 12:45:58 -0500 | [diff] [blame] | 244 | hdmi_pins: pinmux_hdmi_pins { |
| 245 | pinctrl-single,pins = < |
| 246 | DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */ |
| 247 | DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */ |
| 248 | >; |
| 249 | }; |
| 250 | |
| 251 | tpd12s015_pins: pinmux_tpd12s015_pins { |
| 252 | pinctrl-single,pins = < |
| 253 | DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */ |
| 254 | >; |
| 255 | }; |
| 256 | |
| 257 | atl_pins: pinmux_atl_pins { |
| 258 | pinctrl-single,pins = < |
| 259 | DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */ |
| 260 | DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */ |
| 261 | >; |
| 262 | }; |
| 263 | |
| 264 | mcasp3_pins: pinmux_mcasp3_pins { |
| 265 | pinctrl-single,pins = < |
| 266 | DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */ |
| 267 | DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */ |
| 268 | DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */ |
| 269 | DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */ |
| 270 | >; |
| 271 | }; |
| 272 | |
| 273 | mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins { |
| 274 | pinctrl-single,pins = < |
| 275 | DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE15) |
| 276 | DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE15) |
| 277 | DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT_PULLDOWN | MUX_MODE15) |
| 278 | DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE15) |
| 279 | >; |
| 280 | }; |
| 281 | }; |
| 282 | |
| 283 | &i2c1 { |
| 284 | status = "okay"; |
| 285 | pinctrl-names = "default"; |
| 286 | pinctrl-0 = <&i2c1_pins>; |
| 287 | clock-frequency = <400000>; |
| 288 | |
| 289 | tps65917: tps65917@58 { |
| 290 | compatible = "ti,tps65917"; |
| 291 | reg = <0x58>; |
| 292 | |
| 293 | pinctrl-names = "default"; |
| 294 | pinctrl-0 = <&tps65917_pins_default>; |
| 295 | |
| 296 | interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ |
| 297 | interrupt-controller; |
| 298 | #interrupt-cells = <2>; |
| 299 | |
| 300 | ti,system-power-controller; |
| 301 | |
| 302 | tps65917_pmic { |
| 303 | compatible = "ti,tps65917-pmic"; |
| 304 | |
| 305 | tps65917_regulators: regulators { |
| 306 | smps1_reg: smps1 { |
| 307 | /* VDD_MPU */ |
| 308 | regulator-name = "smps1"; |
| 309 | regulator-min-microvolt = <850000>; |
| 310 | regulator-max-microvolt = <1250000>; |
| 311 | regulator-always-on; |
| 312 | regulator-boot-on; |
| 313 | }; |
| 314 | |
| 315 | smps2_reg: smps2 { |
| 316 | /* VDD_CORE */ |
| 317 | regulator-name = "smps2"; |
| 318 | regulator-min-microvolt = <850000>; |
Nishanth Menon | 54d03c5 | 2016-04-20 03:18:39 -0500 | [diff] [blame] | 319 | regulator-max-microvolt = <1150000>; |
Nishanth Menon | a4240d3 | 2016-04-14 12:45:58 -0500 | [diff] [blame] | 320 | regulator-boot-on; |
| 321 | regulator-always-on; |
| 322 | }; |
| 323 | |
| 324 | smps3_reg: smps3 { |
| 325 | /* VDD_GPU IVA DSPEVE */ |
| 326 | regulator-name = "smps3"; |
| 327 | regulator-min-microvolt = <850000>; |
| 328 | regulator-max-microvolt = <1250000>; |
| 329 | regulator-boot-on; |
| 330 | regulator-always-on; |
| 331 | }; |
| 332 | |
| 333 | smps4_reg: smps4 { |
| 334 | /* VDDS1V8 */ |
| 335 | regulator-name = "smps4"; |
| 336 | regulator-min-microvolt = <1800000>; |
| 337 | regulator-max-microvolt = <1800000>; |
| 338 | regulator-always-on; |
| 339 | regulator-boot-on; |
| 340 | }; |
| 341 | |
| 342 | smps5_reg: smps5 { |
| 343 | /* VDD_DDR */ |
| 344 | regulator-name = "smps5"; |
| 345 | regulator-min-microvolt = <1350000>; |
| 346 | regulator-max-microvolt = <1350000>; |
| 347 | regulator-boot-on; |
| 348 | regulator-always-on; |
| 349 | }; |
| 350 | |
| 351 | ldo1_reg: ldo1 { |
| 352 | /* LDO1_OUT --> SDIO */ |
| 353 | regulator-name = "ldo1"; |
| 354 | regulator-min-microvolt = <1800000>; |
| 355 | regulator-max-microvolt = <3300000>; |
| 356 | regulator-always-on; |
| 357 | regulator-boot-on; |
| 358 | regulator-allow-bypass; |
| 359 | }; |
| 360 | |
| 361 | ldo3_reg: ldo3 { |
| 362 | /* VDDA_1V8_PHY */ |
| 363 | regulator-name = "ldo3"; |
| 364 | regulator-min-microvolt = <1800000>; |
| 365 | regulator-max-microvolt = <1800000>; |
| 366 | regulator-boot-on; |
| 367 | regulator-always-on; |
| 368 | }; |
| 369 | |
| 370 | ldo5_reg: ldo5 { |
| 371 | /* VDDA_1V8_PLL */ |
| 372 | regulator-name = "ldo5"; |
| 373 | regulator-min-microvolt = <1800000>; |
| 374 | regulator-max-microvolt = <1800000>; |
| 375 | regulator-always-on; |
| 376 | regulator-boot-on; |
| 377 | }; |
| 378 | |
| 379 | ldo4_reg: ldo4 { |
| 380 | /* VDDA_3V_USB: VDDA_USBHS33 */ |
| 381 | regulator-name = "ldo4"; |
| 382 | regulator-min-microvolt = <3300000>; |
| 383 | regulator-max-microvolt = <3300000>; |
| 384 | regulator-boot-on; |
| 385 | }; |
| 386 | }; |
| 387 | }; |
| 388 | |
| 389 | tps65917_power_button { |
| 390 | compatible = "ti,palmas-pwrbutton"; |
| 391 | interrupt-parent = <&tps65917>; |
| 392 | interrupts = <1 IRQ_TYPE_NONE>; |
| 393 | wakeup-source; |
| 394 | ti,palmas-long-press-seconds = <6>; |
| 395 | }; |
| 396 | }; |
| 397 | |
| 398 | pcf_gpio_21: gpio@21 { |
Roger Quadros | 86f196f | 2016-04-25 15:53:54 +0300 | [diff] [blame] | 399 | compatible = "ti,pcf8575", "nxp,pcf8575"; |
Nishanth Menon | a4240d3 | 2016-04-14 12:45:58 -0500 | [diff] [blame] | 400 | reg = <0x21>; |
| 401 | lines-initial-states = <0x1408>; |
| 402 | gpio-controller; |
| 403 | #gpio-cells = <2>; |
| 404 | interrupt-controller; |
| 405 | #interrupt-cells = <2>; |
| 406 | }; |
| 407 | |
| 408 | tlv320aic3106: tlv320aic3106@19 { |
| 409 | #sound-dai-cells = <0>; |
| 410 | compatible = "ti,tlv320aic3106"; |
| 411 | reg = <0x19>; |
| 412 | adc-settle-ms = <40>; |
| 413 | ai3x-micbias-vg = <1>; /* 2.0V */ |
| 414 | status = "okay"; |
| 415 | |
| 416 | /* Regulators */ |
Misael Lopez Cruz | 7172e74 | 2016-05-24 15:00:40 -0500 | [diff] [blame] | 417 | AVDD-supply = <&evm_3v3_sw>; |
| 418 | IOVDD-supply = <&evm_3v3_sw>; |
| 419 | DRVDD-supply = <&evm_3v3_sw>; |
Nishanth Menon | a4240d3 | 2016-04-14 12:45:58 -0500 | [diff] [blame] | 420 | DVDD-supply = <&aic_dvdd>; |
| 421 | }; |
| 422 | }; |
| 423 | |
| 424 | &i2c5 { |
| 425 | status = "okay"; |
| 426 | pinctrl-names = "default"; |
| 427 | pinctrl-0 = <&i2c5_pins>; |
| 428 | clock-frequency = <400000>; |
| 429 | |
| 430 | pcf_hdmi: pcf8575@26 { |
Roger Quadros | 86f196f | 2016-04-25 15:53:54 +0300 | [diff] [blame] | 431 | compatible = "ti,pcf8575", "nxp,pcf8575"; |
Nishanth Menon | a4240d3 | 2016-04-14 12:45:58 -0500 | [diff] [blame] | 432 | reg = <0x26>; |
| 433 | gpio-controller; |
| 434 | #gpio-cells = <2>; |
| 435 | /* |
| 436 | * initial state is used here to keep the mdio interface |
| 437 | * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and |
| 438 | * VIN2_S0 driven high otherwise Ethernet stops working |
| 439 | * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 |
| 440 | */ |
| 441 | lines-initial-states = <0x0f2b>; |
| 442 | |
| 443 | p1 { |
| 444 | /* vin6_sel_s0: high: VIN6, low: audio */ |
| 445 | gpio-hog; |
| 446 | gpios = <1 GPIO_ACTIVE_HIGH>; |
| 447 | output-low; |
| 448 | line-name = "vin6_sel_s0"; |
| 449 | }; |
| 450 | }; |
| 451 | }; |
| 452 | |
| 453 | &uart1 { |
| 454 | status = "okay"; |
| 455 | interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, |
| 456 | <&dra7_pmx_core 0x3e0>; |
| 457 | }; |
| 458 | |
| 459 | &elm { |
| 460 | status = "okay"; |
| 461 | }; |
| 462 | |
| 463 | &gpmc { |
| 464 | status = "okay"; |
| 465 | pinctrl-names = "default"; |
| 466 | pinctrl-0 = <&nand_default>; |
| 467 | ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ |
| 468 | nand@0,0 { |
| 469 | /* To use NAND, DIP switch SW5 must be set like so: |
| 470 | * SW5.1 (NAND_SELn) = ON (LOW) |
| 471 | * SW5.9 (GPMC_WPN) = OFF (HIGH) |
| 472 | */ |
| 473 | compatible = "ti,omap2-nand"; |
| 474 | reg = <0 0 4>; /* device IO registers */ |
| 475 | interrupt-parent = <&gpmc>; |
| 476 | interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ |
| 477 | <1 IRQ_TYPE_NONE>; /* termcount */ |
| 478 | rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ |
| 479 | ti,nand-ecc-opt = "bch8"; |
| 480 | ti,elm-id = <&elm>; |
| 481 | nand-bus-width = <16>; |
| 482 | gpmc,device-width = <2>; |
| 483 | gpmc,sync-clk-ps = <0>; |
| 484 | gpmc,cs-on-ns = <0>; |
| 485 | gpmc,cs-rd-off-ns = <80>; |
| 486 | gpmc,cs-wr-off-ns = <80>; |
| 487 | gpmc,adv-on-ns = <0>; |
| 488 | gpmc,adv-rd-off-ns = <60>; |
| 489 | gpmc,adv-wr-off-ns = <60>; |
| 490 | gpmc,we-on-ns = <10>; |
| 491 | gpmc,we-off-ns = <50>; |
| 492 | gpmc,oe-on-ns = <4>; |
| 493 | gpmc,oe-off-ns = <40>; |
| 494 | gpmc,access-ns = <40>; |
| 495 | gpmc,wr-access-ns = <80>; |
| 496 | gpmc,rd-cycle-ns = <80>; |
| 497 | gpmc,wr-cycle-ns = <80>; |
| 498 | gpmc,bus-turnaround-ns = <0>; |
| 499 | gpmc,cycle2cycle-delay-ns = <0>; |
| 500 | gpmc,clk-activation-ns = <0>; |
| 501 | gpmc,wr-data-mux-bus-ns = <0>; |
| 502 | /* MTD partition table */ |
| 503 | /* All SPL-* partitions are sized to minimal length |
| 504 | * which can be independently programmable. For |
| 505 | * NAND flash this is equal to size of erase-block */ |
| 506 | #address-cells = <1>; |
| 507 | #size-cells = <1>; |
| 508 | partition@0 { |
| 509 | label = "NAND.SPL"; |
| 510 | reg = <0x00000000 0x000020000>; |
| 511 | }; |
| 512 | partition@1 { |
| 513 | label = "NAND.SPL.backup1"; |
| 514 | reg = <0x00020000 0x00020000>; |
| 515 | }; |
| 516 | partition@2 { |
| 517 | label = "NAND.SPL.backup2"; |
| 518 | reg = <0x00040000 0x00020000>; |
| 519 | }; |
| 520 | partition@3 { |
| 521 | label = "NAND.SPL.backup3"; |
| 522 | reg = <0x00060000 0x00020000>; |
| 523 | }; |
| 524 | partition@4 { |
| 525 | label = "NAND.u-boot-spl-os"; |
| 526 | reg = <0x00080000 0x00040000>; |
| 527 | }; |
| 528 | partition@5 { |
| 529 | label = "NAND.u-boot"; |
| 530 | reg = <0x000c0000 0x00100000>; |
| 531 | }; |
| 532 | partition@6 { |
| 533 | label = "NAND.u-boot-env"; |
| 534 | reg = <0x001c0000 0x00020000>; |
| 535 | }; |
| 536 | partition@7 { |
| 537 | label = "NAND.u-boot-env.backup1"; |
| 538 | reg = <0x001e0000 0x00020000>; |
| 539 | }; |
| 540 | partition@8 { |
| 541 | label = "NAND.kernel"; |
| 542 | reg = <0x00200000 0x00800000>; |
| 543 | }; |
| 544 | partition@9 { |
| 545 | label = "NAND.file-system"; |
| 546 | reg = <0x00a00000 0x0f600000>; |
| 547 | }; |
| 548 | }; |
| 549 | }; |
| 550 | |
| 551 | &usb2_phy1 { |
| 552 | phy-supply = <&ldo4_reg>; |
| 553 | }; |
| 554 | |
| 555 | &usb2_phy2 { |
| 556 | phy-supply = <&ldo4_reg>; |
| 557 | }; |
| 558 | |
| 559 | &omap_dwc3_1 { |
| 560 | extcon = <&extcon_usb1>; |
| 561 | }; |
| 562 | |
| 563 | &omap_dwc3_2 { |
| 564 | extcon = <&extcon_usb2>; |
| 565 | }; |
| 566 | |
| 567 | &usb1 { |
| 568 | dr_mode = "peripheral"; |
| 569 | pinctrl-names = "default"; |
| 570 | pinctrl-0 = <&usb1_pins>; |
| 571 | }; |
| 572 | |
| 573 | &usb2 { |
| 574 | dr_mode = "host"; |
| 575 | pinctrl-names = "default"; |
| 576 | pinctrl-0 = <&usb2_pins>; |
| 577 | }; |
| 578 | |
| 579 | &mmc1 { |
| 580 | status = "okay"; |
| 581 | pinctrl-names = "default"; |
| 582 | pinctrl-0 = <&mmc1_pins_default>; |
| 583 | vmmc-supply = <&evm_3v3_sd>; |
| 584 | vmmc_aux-supply = <&ldo1_reg>; |
| 585 | bus-width = <4>; |
| 586 | /* |
| 587 | * SDCD signal is not being used here - using the fact that GPIO mode |
| 588 | * is a viable alternative |
| 589 | */ |
| 590 | cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; |
| 591 | max-frequency = <192000000>; |
| 592 | }; |
| 593 | |
| 594 | &mmc2 { |
| 595 | /* SW5-3 in ON position */ |
| 596 | status = "okay"; |
| 597 | pinctrl-names = "default"; |
| 598 | pinctrl-0 = <&mmc2_pins_default>; |
| 599 | |
Misael Lopez Cruz | 7172e74 | 2016-05-24 15:00:40 -0500 | [diff] [blame] | 600 | vmmc-supply = <&evm_3v3_sw>; |
Nishanth Menon | a4240d3 | 2016-04-14 12:45:58 -0500 | [diff] [blame] | 601 | bus-width = <8>; |
| 602 | ti,non-removable; |
| 603 | max-frequency = <192000000>; |
| 604 | }; |
| 605 | |
| 606 | &dra7_pmx_core { |
| 607 | cpsw_default: cpsw_default { |
| 608 | pinctrl-single,pins = < |
| 609 | /* Slave 2 */ |
| 610 | DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ |
| 611 | DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ |
| 612 | DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ |
| 613 | DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ |
| 614 | DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ |
| 615 | DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ |
| 616 | DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ |
| 617 | DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ |
| 618 | DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ |
| 619 | DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ |
| 620 | DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ |
| 621 | DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ |
| 622 | >; |
| 623 | |
| 624 | }; |
| 625 | |
| 626 | cpsw_sleep: cpsw_sleep { |
| 627 | pinctrl-single,pins = < |
| 628 | /* Slave 2 */ |
| 629 | DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15) |
| 630 | DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15) |
| 631 | DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15) |
| 632 | DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15) |
| 633 | DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15) |
| 634 | DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15) |
| 635 | DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15) |
| 636 | DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15) |
| 637 | DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15) |
| 638 | DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15) |
| 639 | DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15) |
| 640 | DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15) |
| 641 | >; |
| 642 | }; |
| 643 | |
| 644 | davinci_mdio_default: davinci_mdio_default { |
| 645 | pinctrl-single,pins = < |
| 646 | /* MDIO */ |
| 647 | DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ |
| 648 | DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ |
| 649 | >; |
| 650 | }; |
| 651 | |
| 652 | davinci_mdio_sleep: davinci_mdio_sleep { |
| 653 | pinctrl-single,pins = < |
| 654 | DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15) |
| 655 | DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15) |
| 656 | >; |
| 657 | }; |
| 658 | }; |
| 659 | |
| 660 | &mac { |
| 661 | status = "okay"; |
| 662 | pinctrl-names = "default", "sleep"; |
| 663 | pinctrl-0 = <&cpsw_default>; |
| 664 | pinctrl-1 = <&cpsw_sleep>; |
| 665 | }; |
| 666 | |
| 667 | &davinci_mdio { |
| 668 | pinctrl-names = "default", "sleep"; |
| 669 | pinctrl-0 = <&davinci_mdio_default>; |
| 670 | pinctrl-1 = <&davinci_mdio_sleep>; |
| 671 | }; |
| 672 | |
| 673 | &dcan1 { |
| 674 | status = "ok"; |
| 675 | pinctrl-names = "default", "sleep", "active"; |
| 676 | pinctrl-0 = <&dcan1_pins_sleep>; |
| 677 | pinctrl-1 = <&dcan1_pins_sleep>; |
| 678 | pinctrl-2 = <&dcan1_pins_default>; |
| 679 | }; |
| 680 | |
| 681 | &qspi { |
| 682 | status = "okay"; |
Nishanth Menon | a4240d3 | 2016-04-14 12:45:58 -0500 | [diff] [blame] | 683 | |
Vignesh R | b7a1922 | 2016-04-20 17:03:00 +0530 | [diff] [blame] | 684 | spi-max-frequency = <64000000>; |
Nishanth Menon | a4240d3 | 2016-04-14 12:45:58 -0500 | [diff] [blame] | 685 | m25p80@0 { |
| 686 | compatible = "s25fl256s1"; |
Vignesh R | b7a1922 | 2016-04-20 17:03:00 +0530 | [diff] [blame] | 687 | spi-max-frequency = <64000000>; |
Nishanth Menon | a4240d3 | 2016-04-14 12:45:58 -0500 | [diff] [blame] | 688 | reg = <0>; |
| 689 | spi-tx-bus-width = <1>; |
| 690 | spi-rx-bus-width = <4>; |
Nishanth Menon | a4240d3 | 2016-04-14 12:45:58 -0500 | [diff] [blame] | 691 | #address-cells = <1>; |
| 692 | #size-cells = <1>; |
| 693 | |
| 694 | /* MTD partition table. |
| 695 | * The ROM checks the first four physical blocks |
| 696 | * for a valid file to boot and the flash here is |
| 697 | * 64KiB block size. |
| 698 | */ |
| 699 | partition@0 { |
| 700 | label = "QSPI.SPL"; |
| 701 | reg = <0x00000000 0x000010000>; |
| 702 | }; |
| 703 | partition@1 { |
| 704 | label = "QSPI.SPL.backup1"; |
| 705 | reg = <0x00010000 0x00010000>; |
| 706 | }; |
| 707 | partition@2 { |
| 708 | label = "QSPI.SPL.backup2"; |
| 709 | reg = <0x00020000 0x00010000>; |
| 710 | }; |
| 711 | partition@3 { |
| 712 | label = "QSPI.SPL.backup3"; |
| 713 | reg = <0x00030000 0x00010000>; |
| 714 | }; |
| 715 | partition@4 { |
| 716 | label = "QSPI.u-boot"; |
| 717 | reg = <0x00040000 0x00100000>; |
| 718 | }; |
| 719 | partition@5 { |
| 720 | label = "QSPI.u-boot-spl-os"; |
| 721 | reg = <0x00140000 0x00080000>; |
| 722 | }; |
| 723 | partition@6 { |
| 724 | label = "QSPI.u-boot-env"; |
| 725 | reg = <0x001c0000 0x00010000>; |
| 726 | }; |
| 727 | partition@7 { |
| 728 | label = "QSPI.u-boot-env.backup1"; |
| 729 | reg = <0x001d0000 0x0010000>; |
| 730 | }; |
| 731 | partition@8 { |
| 732 | label = "QSPI.kernel"; |
| 733 | reg = <0x001e0000 0x0800000>; |
| 734 | }; |
| 735 | partition@9 { |
| 736 | label = "QSPI.file-system"; |
| 737 | reg = <0x009e0000 0x01620000>; |
| 738 | }; |
| 739 | }; |
| 740 | }; |
| 741 | |
| 742 | &dss { |
| 743 | status = "ok"; |
| 744 | |
| 745 | vdda_video-supply = <&ldo5_reg>; |
| 746 | }; |
| 747 | |
| 748 | &hdmi { |
| 749 | status = "ok"; |
| 750 | |
| 751 | pinctrl-names = "default"; |
| 752 | pinctrl-0 = <&hdmi_pins>; |
| 753 | |
| 754 | port { |
| 755 | hdmi_out: endpoint { |
| 756 | remote-endpoint = <&tpd12s015_in>; |
| 757 | }; |
| 758 | }; |
| 759 | }; |
| 760 | |
| 761 | &atl { |
| 762 | pinctrl-names = "default"; |
| 763 | pinctrl-0 = <&atl_pins>; |
| 764 | |
| 765 | assigned-clocks = <&abe_dpll_sys_clk_mux>, |
| 766 | <&atl_gfclk_mux>, |
| 767 | <&dpll_abe_ck>, |
| 768 | <&dpll_abe_m2x2_ck>, |
| 769 | <&atl_clkin2_ck>; |
| 770 | assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; |
| 771 | assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>; |
| 772 | |
| 773 | status = "okay"; |
| 774 | |
| 775 | atl2 { |
| 776 | bws = <DRA7_ATL_WS_MCASP2_FSX>; |
| 777 | aws = <DRA7_ATL_WS_MCASP3_FSX>; |
| 778 | }; |
| 779 | }; |
| 780 | |
| 781 | &mcasp3 { |
| 782 | #sound-dai-cells = <0>; |
| 783 | pinctrl-names = "default", "sleep"; |
| 784 | pinctrl-0 = <&mcasp3_pins>; |
| 785 | pinctrl-1 = <&mcasp3_sleep_pins>; |
| 786 | |
| 787 | assigned-clocks = <&mcasp3_ahclkx_mux>; |
| 788 | assigned-clock-parents = <&atl_clkin2_ck>; |
| 789 | |
| 790 | status = "okay"; |
| 791 | |
| 792 | op-mode = <0>; /* MCASP_IIS_MODE */ |
| 793 | tdm-slots = <2>; |
| 794 | /* 4 serializer */ |
| 795 | serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ |
| 796 | 1 2 0 0 |
| 797 | >; |
| 798 | tx-num-evt = <32>; |
| 799 | rx-num-evt = <32>; |
| 800 | }; |
| 801 | |
| 802 | &mailbox5 { |
| 803 | status = "okay"; |
| 804 | mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { |
| 805 | status = "okay"; |
| 806 | }; |
| 807 | mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { |
| 808 | status = "okay"; |
| 809 | }; |
| 810 | }; |
| 811 | |
| 812 | &mailbox6 { |
| 813 | status = "okay"; |
| 814 | mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { |
| 815 | status = "okay"; |
| 816 | }; |
| 817 | }; |