blob: 3437bb3968445f20ff409093c60b9b8c1f3aa494 [file] [log] [blame]
Andrew Lunn9eb61f42012-05-12 14:57:59 +02001/dts-v1/;
2
Ezequiel Garcia0ab61292013-07-26 10:18:02 -03003#include "kirkwood.dtsi"
4#include "kirkwood-6282.dtsi"
5#include "kirkwood-ts219.dtsi"
Andrew Lunn9eb61f42012-05-12 14:57:59 +02006
7/ {
Andrew Lunn1f6e46b2012-11-17 17:00:46 +01008 ocp@f1000000 {
Sebastian Hesselbartha9483962014-04-30 14:56:32 +02009 pinctrl: pin-controller@10000 {
Andrew Lunn1f6e46b2012-11-17 17:00:46 +010010
Thomas Petazzonia4936cf2013-05-24 11:44:56 +020011 pinctrl-0 = <&pmx_ram_size &pmx_board_id>;
Andrew Lunn1f6e46b2012-11-17 17:00:46 +010012 pinctrl-names = "default";
13
14 pmx_ram_size: pmx-ram-size {
15 /* RAM: 0: 256 MB, 1: 512 MB */
16 marvell,pins = "mpp36";
17 marvell,function = "gpio";
18 };
19 pmx_reset_button: pmx-reset-button {
20 marvell,pins = "mpp37";
21 marvell,function = "gpio";
22 };
23 pmx_USB_copy_button: pmx-USB-copy-button {
24 marvell,pins = "mpp43";
25 marvell,function = "gpio";
26 };
27 pmx_board_id: pmx-board-id {
28 /* 0: TS-11x, 1: TS-21x */
29 marvell,pins = "mpp44";
30 marvell,function = "gpio";
31 };
32 };
33 };
34
Andrew Lunn9eb61f42012-05-12 14:57:59 +020035 gpio_keys {
36 compatible = "gpio-keys";
37 #address-cells = <1>;
38 #size-cells = <0>;
Thomas Petazzonia4936cf2013-05-24 11:44:56 +020039 pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>;
40 pinctrl-names = "default";
41
Andrew Lunn395c7552016-04-03 04:03:43 +020042 copy {
Andrew Lunn9eb61f42012-05-12 14:57:59 +020043 label = "USB Copy";
Andrew Lunn23301192013-12-04 16:51:38 +010044 linux,code = <KEY_COPY>;
Andrew Lunn3a31f2d72013-12-04 16:51:39 +010045 gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
Andrew Lunn9eb61f42012-05-12 14:57:59 +020046 };
Andrew Lunn395c7552016-04-03 04:03:43 +020047 reset {
Andrew Lunn9eb61f42012-05-12 14:57:59 +020048 label = "Reset";
Andrew Lunn23301192013-12-04 16:51:38 +010049 linux,code = <KEY_RESTART>;
Andrew Lunn3a31f2d72013-12-04 16:51:39 +010050 gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
Andrew Lunn9eb61f42012-05-12 14:57:59 +020051 };
52 };
Sebastian Hesselbarth876e2332013-07-07 22:34:56 +020053};
54
55&ethphy0 { reg = <0>; };
Andrew Lunneb13cf82016-04-03 04:03:47 +020056
57&pcie1 { status = "okay"; };