blob: 142217cd01f47850e93f974f13b2383f7f80e5af [file] [log] [blame]
Rong Wang161e7732011-11-17 23:17:04 +08001/*
2 * Driver for CSR SiRFprimaII onboard UARTs.
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/module.h>
10#include <linux/ioport.h>
11#include <linux/platform_device.h>
12#include <linux/init.h>
13#include <linux/sysrq.h>
14#include <linux/console.h>
15#include <linux/tty.h>
16#include <linux/tty_flip.h>
17#include <linux/serial_core.h>
18#include <linux/serial.h>
19#include <linux/clk.h>
20#include <linux/of.h>
21#include <linux/slab.h>
22#include <linux/io.h>
23#include <asm/irq.h>
24#include <asm/mach/irq.h>
Linus Walleij5c9bdc32012-02-16 19:36:21 +010025#include <linux/pinctrl/consumer.h>
Rong Wang161e7732011-11-17 23:17:04 +080026
27#include "sirfsoc_uart.h"
28
29static unsigned int
30sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count);
31static unsigned int
32sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count);
33static struct uart_driver sirfsoc_uart_drv;
34
35static const struct sirfsoc_baudrate_to_regv baudrate_to_regv[] = {
36 {4000000, 2359296},
37 {3500000, 1310721},
38 {3000000, 1572865},
39 {2500000, 1245186},
40 {2000000, 1572866},
41 {1500000, 1245188},
42 {1152000, 1638404},
43 {1000000, 1572869},
44 {921600, 1114120},
45 {576000, 1245196},
46 {500000, 1245198},
47 {460800, 1572876},
48 {230400, 1310750},
49 {115200, 1310781},
50 {57600, 1310843},
51 {38400, 1114328},
52 {19200, 1114545},
53 {9600, 1114979},
54};
55
56static struct sirfsoc_uart_port sirfsoc_uart_ports[SIRFSOC_UART_NR] = {
57 [0] = {
58 .port = {
59 .iotype = UPIO_MEM,
60 .flags = UPF_BOOT_AUTOCONF,
61 .line = 0,
62 },
63 },
64 [1] = {
65 .port = {
66 .iotype = UPIO_MEM,
67 .flags = UPF_BOOT_AUTOCONF,
68 .line = 1,
69 },
70 },
71 [2] = {
72 .port = {
73 .iotype = UPIO_MEM,
74 .flags = UPF_BOOT_AUTOCONF,
75 .line = 2,
76 },
77 },
Barry Song5425e032012-12-25 17:32:04 +080078 [3] = {
79 .port = {
80 .iotype = UPIO_MEM,
81 .flags = UPF_BOOT_AUTOCONF,
82 .line = 3,
83 },
84 },
85 [4] = {
86 .port = {
87 .iotype = UPIO_MEM,
88 .flags = UPF_BOOT_AUTOCONF,
89 .line = 4,
90 },
91 },
Rong Wang161e7732011-11-17 23:17:04 +080092};
93
94static inline struct sirfsoc_uart_port *to_sirfport(struct uart_port *port)
95{
96 return container_of(port, struct sirfsoc_uart_port, port);
97}
98
99static inline unsigned int sirfsoc_uart_tx_empty(struct uart_port *port)
100{
101 unsigned long reg;
102 reg = rd_regl(port, SIRFUART_TX_FIFO_STATUS);
103 if (reg & SIRFUART_FIFOEMPTY_MASK(port))
104 return TIOCSER_TEMT;
105 else
106 return 0;
107}
108
109static unsigned int sirfsoc_uart_get_mctrl(struct uart_port *port)
110{
111 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
112 if (!(sirfport->ms_enabled)) {
113 goto cts_asserted;
114 } else if (sirfport->hw_flow_ctrl) {
115 if (!(rd_regl(port, SIRFUART_AFC_CTRL) &
116 SIRFUART_CTS_IN_STATUS))
117 goto cts_asserted;
118 else
119 goto cts_deasserted;
120 }
121cts_deasserted:
122 return TIOCM_CAR | TIOCM_DSR;
123cts_asserted:
124 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
125}
126
127static void sirfsoc_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
128{
129 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
130 unsigned int assert = mctrl & TIOCM_RTS;
131 unsigned int val = assert ? SIRFUART_AFC_CTRL_RX_THD : 0x0;
132 unsigned int current_val;
133 if (sirfport->hw_flow_ctrl) {
134 current_val = rd_regl(port, SIRFUART_AFC_CTRL) & ~0xFF;
135 val |= current_val;
136 wr_regl(port, SIRFUART_AFC_CTRL, val);
137 }
138}
139
140static void sirfsoc_uart_stop_tx(struct uart_port *port)
141{
142 unsigned int regv;
143 regv = rd_regl(port, SIRFUART_INT_EN);
144 wr_regl(port, SIRFUART_INT_EN, regv & ~SIRFUART_TX_INT_EN);
145}
146
147void sirfsoc_uart_start_tx(struct uart_port *port)
148{
149 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
150 unsigned long regv;
151 sirfsoc_uart_pio_tx_chars(sirfport, 1);
152 wr_regl(port, SIRFUART_TX_FIFO_OP, SIRFUART_TX_FIFO_START);
153 regv = rd_regl(port, SIRFUART_INT_EN);
154 wr_regl(port, SIRFUART_INT_EN, regv | SIRFUART_TX_INT_EN);
155}
156
157static void sirfsoc_uart_stop_rx(struct uart_port *port)
158{
159 unsigned long regv;
160 wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
161 regv = rd_regl(port, SIRFUART_INT_EN);
162 wr_regl(port, SIRFUART_INT_EN, regv & ~SIRFUART_RX_IO_INT_EN);
163}
164
165static void sirfsoc_uart_disable_ms(struct uart_port *port)
166{
167 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
168 unsigned long reg;
169 sirfport->ms_enabled = 0;
170 if (!sirfport->hw_flow_ctrl)
171 return;
172 reg = rd_regl(port, SIRFUART_AFC_CTRL);
173 wr_regl(port, SIRFUART_AFC_CTRL, reg & ~0x3FF);
174 reg = rd_regl(port, SIRFUART_INT_EN);
175 wr_regl(port, SIRFUART_INT_EN, reg & ~SIRFUART_CTS_INT_EN);
176}
177
178static void sirfsoc_uart_enable_ms(struct uart_port *port)
179{
180 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
181 unsigned long reg;
182 unsigned long flg;
183 if (!sirfport->hw_flow_ctrl)
184 return;
185 flg = SIRFUART_AFC_RX_EN | SIRFUART_AFC_TX_EN;
186 reg = rd_regl(port, SIRFUART_AFC_CTRL);
187 wr_regl(port, SIRFUART_AFC_CTRL, reg | flg);
188 reg = rd_regl(port, SIRFUART_INT_EN);
189 wr_regl(port, SIRFUART_INT_EN, reg | SIRFUART_CTS_INT_EN);
190 uart_handle_cts_change(port,
191 !(rd_regl(port, SIRFUART_AFC_CTRL) & SIRFUART_CTS_IN_STATUS));
192 sirfport->ms_enabled = 1;
193}
194
195static void sirfsoc_uart_break_ctl(struct uart_port *port, int break_state)
196{
197 unsigned long ulcon = rd_regl(port, SIRFUART_LINE_CTRL);
198 if (break_state)
199 ulcon |= SIRFUART_SET_BREAK;
200 else
201 ulcon &= ~SIRFUART_SET_BREAK;
202 wr_regl(port, SIRFUART_LINE_CTRL, ulcon);
203}
204
205static unsigned int
206sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count)
207{
208 unsigned int ch, rx_count = 0;
209 struct tty_struct *tty;
210
211 tty = tty_port_tty_get(&port->state->port);
212 if (!tty)
213 return -ENODEV;
214
215 while (!(rd_regl(port, SIRFUART_RX_FIFO_STATUS) &
216 SIRFUART_FIFOEMPTY_MASK(port))) {
217 ch = rd_regl(port, SIRFUART_RX_FIFO_DATA) | SIRFUART_DUMMY_READ;
218 if (unlikely(uart_handle_sysrq_char(port, ch)))
219 continue;
220 uart_insert_char(port, 0, 0, ch, TTY_NORMAL);
221 rx_count++;
222 if (rx_count >= max_rx_count)
223 break;
224 }
225
226 port->icount.rx += rx_count;
227 tty_flip_buffer_push(tty);
228 tty_kref_put(tty);
229
230 return rx_count;
231}
232
233static unsigned int
234sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count)
235{
236 struct uart_port *port = &sirfport->port;
237 struct circ_buf *xmit = &port->state->xmit;
238 unsigned int num_tx = 0;
239 while (!uart_circ_empty(xmit) &&
240 !(rd_regl(port, SIRFUART_TX_FIFO_STATUS) &
241 SIRFUART_FIFOFULL_MASK(port)) &&
242 count--) {
243 wr_regl(port, SIRFUART_TX_FIFO_DATA, xmit->buf[xmit->tail]);
244 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
245 port->icount.tx++;
246 num_tx++;
247 }
248 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
249 uart_write_wakeup(port);
250 return num_tx;
251}
252
253static irqreturn_t sirfsoc_uart_isr(int irq, void *dev_id)
254{
255 unsigned long intr_status;
256 unsigned long cts_status;
257 unsigned long flag = TTY_NORMAL;
258 struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id;
259 struct uart_port *port = &sirfport->port;
260 struct uart_state *state = port->state;
261 struct circ_buf *xmit = &port->state->xmit;
Barry Song5425e032012-12-25 17:32:04 +0800262 spin_lock(&port->lock);
Rong Wang161e7732011-11-17 23:17:04 +0800263 intr_status = rd_regl(port, SIRFUART_INT_STATUS);
264 wr_regl(port, SIRFUART_INT_STATUS, intr_status);
265 intr_status &= rd_regl(port, SIRFUART_INT_EN);
266 if (unlikely(intr_status & (SIRFUART_ERR_INT_STAT))) {
267 if (intr_status & SIRFUART_RXD_BREAK) {
268 if (uart_handle_break(port))
269 goto recv_char;
270 uart_insert_char(port, intr_status,
271 SIRFUART_RX_OFLOW, 0, TTY_BREAK);
Barry Song5425e032012-12-25 17:32:04 +0800272 spin_unlock(&port->lock);
Rong Wang161e7732011-11-17 23:17:04 +0800273 return IRQ_HANDLED;
274 }
275 if (intr_status & SIRFUART_RX_OFLOW)
276 port->icount.overrun++;
277 if (intr_status & SIRFUART_FRM_ERR) {
278 port->icount.frame++;
279 flag = TTY_FRAME;
280 }
281 if (intr_status & SIRFUART_PARITY_ERR)
282 flag = TTY_PARITY;
283 wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_RESET);
284 wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
285 wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_START);
286 intr_status &= port->read_status_mask;
287 uart_insert_char(port, intr_status,
288 SIRFUART_RX_OFLOW_INT, 0, flag);
289 }
290recv_char:
291 if (intr_status & SIRFUART_CTS_INT_EN) {
292 cts_status = !(rd_regl(port, SIRFUART_AFC_CTRL) &
293 SIRFUART_CTS_IN_STATUS);
294 if (cts_status != 0) {
295 uart_handle_cts_change(port, 1);
296 } else {
297 uart_handle_cts_change(port, 0);
298 wake_up_interruptible(&state->port.delta_msr_wait);
299 }
300 }
301 if (intr_status & SIRFUART_RX_IO_INT_EN)
302 sirfsoc_uart_pio_rx_chars(port, SIRFSOC_UART_IO_RX_MAX_CNT);
303 if (intr_status & SIRFUART_TX_INT_EN) {
304 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
Barry Song5425e032012-12-25 17:32:04 +0800305 spin_unlock(&port->lock);
Rong Wang161e7732011-11-17 23:17:04 +0800306 return IRQ_HANDLED;
307 } else {
308 sirfsoc_uart_pio_tx_chars(sirfport,
309 SIRFSOC_UART_IO_TX_REASONABLE_CNT);
310 if ((uart_circ_empty(xmit)) &&
311 (rd_regl(port, SIRFUART_TX_FIFO_STATUS) &
312 SIRFUART_FIFOEMPTY_MASK(port)))
313 sirfsoc_uart_stop_tx(port);
314 }
315 }
Barry Song5425e032012-12-25 17:32:04 +0800316 spin_unlock(&port->lock);
Rong Wang161e7732011-11-17 23:17:04 +0800317 return IRQ_HANDLED;
318}
319
320static void sirfsoc_uart_start_rx(struct uart_port *port)
321{
322 unsigned long regv;
323 regv = rd_regl(port, SIRFUART_INT_EN);
324 wr_regl(port, SIRFUART_INT_EN, regv | SIRFUART_RX_IO_INT_EN);
325 wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_RESET);
326 wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
327 wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_START);
328}
329
330static unsigned int
331sirfsoc_calc_sample_div(unsigned long baud_rate,
332 unsigned long ioclk_rate, unsigned long *setted_baud)
333{
334 unsigned long min_delta = ~0UL;
335 unsigned short sample_div;
336 unsigned int regv = 0;
337 unsigned long ioclk_div;
338 unsigned long baud_tmp;
339 int temp_delta;
340
341 for (sample_div = SIRF_MIN_SAMPLE_DIV;
342 sample_div <= SIRF_MAX_SAMPLE_DIV; sample_div++) {
343 ioclk_div = (ioclk_rate / (baud_rate * (sample_div + 1))) - 1;
344 if (ioclk_div > SIRF_IOCLK_DIV_MAX)
345 continue;
346 baud_tmp = ioclk_rate / ((ioclk_div + 1) * (sample_div + 1));
347 temp_delta = baud_tmp - baud_rate;
348 temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta;
349 if (temp_delta < min_delta) {
350 regv = regv & (~SIRF_IOCLK_DIV_MASK);
351 regv = regv | ioclk_div;
352 regv = regv & (~SIRF_SAMPLE_DIV_MASK);
353 regv = regv | (sample_div << SIRF_SAMPLE_DIV_SHIFT);
354 min_delta = temp_delta;
355 *setted_baud = baud_tmp;
356 }
357 }
358 return regv;
359}
360
361static void sirfsoc_uart_set_termios(struct uart_port *port,
362 struct ktermios *termios,
363 struct ktermios *old)
364{
365 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
366 unsigned long ioclk_rate;
367 unsigned long config_reg = 0;
368 unsigned long baud_rate;
369 unsigned long setted_baud;
370 unsigned long flags;
371 unsigned long ic;
372 unsigned int clk_div_reg = 0;
373 unsigned long temp_reg_val;
374 unsigned long rx_time_out;
375 int threshold_div;
376 int temp;
377
378 ioclk_rate = 150000000;
379 switch (termios->c_cflag & CSIZE) {
380 default:
381 case CS8:
382 config_reg |= SIRFUART_DATA_BIT_LEN_8;
383 break;
384 case CS7:
385 config_reg |= SIRFUART_DATA_BIT_LEN_7;
386 break;
387 case CS6:
388 config_reg |= SIRFUART_DATA_BIT_LEN_6;
389 break;
390 case CS5:
391 config_reg |= SIRFUART_DATA_BIT_LEN_5;
392 break;
393 }
394 if (termios->c_cflag & CSTOPB)
395 config_reg |= SIRFUART_STOP_BIT_LEN_2;
396 baud_rate = uart_get_baud_rate(port, termios, old, 0, 4000000);
397 spin_lock_irqsave(&port->lock, flags);
398 port->read_status_mask = SIRFUART_RX_OFLOW_INT;
399 port->ignore_status_mask = 0;
400 /* read flags */
401 if (termios->c_iflag & INPCK)
402 port->read_status_mask |=
403 SIRFUART_FRM_ERR_INT | SIRFUART_PARITY_ERR_INT;
404 if (termios->c_iflag & (BRKINT | PARMRK))
405 port->read_status_mask |= SIRFUART_RXD_BREAK_INT;
406 /* ignore flags */
407 if (termios->c_iflag & IGNPAR)
408 port->ignore_status_mask |=
409 SIRFUART_FRM_ERR_INT | SIRFUART_PARITY_ERR_INT;
410 if ((termios->c_cflag & CREAD) == 0)
411 port->ignore_status_mask |= SIRFUART_DUMMY_READ;
412 /* enable parity if PARENB is set*/
413 if (termios->c_cflag & PARENB) {
414 if (termios->c_cflag & CMSPAR) {
415 if (termios->c_cflag & PARODD)
416 config_reg |= SIRFUART_STICK_BIT_MARK;
417 else
418 config_reg |= SIRFUART_STICK_BIT_SPACE;
419 } else if (termios->c_cflag & PARODD) {
420 config_reg |= SIRFUART_STICK_BIT_ODD;
421 } else {
422 config_reg |= SIRFUART_STICK_BIT_EVEN;
423 }
424 }
425 /* Hardware Flow Control Settings */
426 if (UART_ENABLE_MS(port, termios->c_cflag)) {
427 if (!sirfport->ms_enabled)
428 sirfsoc_uart_enable_ms(port);
429 } else {
430 if (sirfport->ms_enabled)
431 sirfsoc_uart_disable_ms(port);
432 }
433
434 /* common rate: fast calculation */
435 for (ic = 0; ic < SIRF_BAUD_RATE_SUPPORT_NR; ic++)
436 if (baud_rate == baudrate_to_regv[ic].baud_rate)
437 clk_div_reg = baudrate_to_regv[ic].reg_val;
438 setted_baud = baud_rate;
439 /* arbitary rate setting */
440 if (unlikely(clk_div_reg == 0))
441 clk_div_reg = sirfsoc_calc_sample_div(baud_rate, ioclk_rate,
442 &setted_baud);
443 wr_regl(port, SIRFUART_DIVISOR, clk_div_reg);
444
445 if (tty_termios_baud_rate(termios))
446 tty_termios_encode_baud_rate(termios, setted_baud, setted_baud);
447
448 /* set receive timeout */
449 rx_time_out = SIRFSOC_UART_RX_TIMEOUT(baud_rate, 20000);
450 rx_time_out = (rx_time_out > 0xFFFF) ? 0xFFFF : rx_time_out;
451 config_reg |= SIRFUART_RECV_TIMEOUT(rx_time_out);
452 temp_reg_val = rd_regl(port, SIRFUART_TX_FIFO_OP);
453 wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
454 wr_regl(port, SIRFUART_TX_FIFO_OP,
455 temp_reg_val & ~SIRFUART_TX_FIFO_START);
456 wr_regl(port, SIRFUART_TX_DMA_IO_CTRL, SIRFUART_TX_MODE_IO);
457 wr_regl(port, SIRFUART_RX_DMA_IO_CTRL, SIRFUART_RX_MODE_IO);
458 wr_regl(port, SIRFUART_LINE_CTRL, config_reg);
459
460 /* Reset Rx/Tx FIFO Threshold level for proper baudrate */
461 if (baud_rate < 1000000)
462 threshold_div = 1;
463 else
464 threshold_div = 2;
465 temp = port->line == 1 ? 16 : 64;
466 wr_regl(port, SIRFUART_TX_FIFO_CTRL, temp / threshold_div);
467 wr_regl(port, SIRFUART_RX_FIFO_CTRL, temp / threshold_div);
468 temp_reg_val |= SIRFUART_TX_FIFO_START;
469 wr_regl(port, SIRFUART_TX_FIFO_OP, temp_reg_val);
470 uart_update_timeout(port, termios->c_cflag, baud_rate);
471 sirfsoc_uart_start_rx(port);
472 wr_regl(port, SIRFUART_TX_RX_EN, SIRFUART_TX_EN | SIRFUART_RX_EN);
473 spin_unlock_irqrestore(&port->lock, flags);
474}
475
476static void startup_uart_controller(struct uart_port *port)
477{
478 unsigned long temp_regv;
479 int temp;
480 temp_regv = rd_regl(port, SIRFUART_TX_DMA_IO_CTRL);
481 wr_regl(port, SIRFUART_TX_DMA_IO_CTRL, temp_regv | SIRFUART_TX_MODE_IO);
482 temp_regv = rd_regl(port, SIRFUART_RX_DMA_IO_CTRL);
483 wr_regl(port, SIRFUART_RX_DMA_IO_CTRL, temp_regv | SIRFUART_RX_MODE_IO);
484 wr_regl(port, SIRFUART_TX_DMA_IO_LEN, 0);
485 wr_regl(port, SIRFUART_RX_DMA_IO_LEN, 0);
486 wr_regl(port, SIRFUART_TX_RX_EN, SIRFUART_RX_EN | SIRFUART_TX_EN);
487 wr_regl(port, SIRFUART_TX_FIFO_OP, SIRFUART_TX_FIFO_RESET);
488 wr_regl(port, SIRFUART_TX_FIFO_OP, 0);
489 wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_RESET);
490 wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
491 temp = port->line == 1 ? 16 : 64;
492 wr_regl(port, SIRFUART_TX_FIFO_CTRL, temp);
493 wr_regl(port, SIRFUART_RX_FIFO_CTRL, temp);
494}
495
496static int sirfsoc_uart_startup(struct uart_port *port)
497{
498 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
499 unsigned int index = port->line;
500 int ret;
501 set_irq_flags(port->irq, IRQF_VALID | IRQF_NOAUTOEN);
502 ret = request_irq(port->irq,
503 sirfsoc_uart_isr,
504 0,
505 SIRFUART_PORT_NAME,
506 sirfport);
507 if (ret != 0) {
508 dev_err(port->dev, "UART%d request IRQ line (%d) failed.\n",
509 index, port->irq);
510 goto irq_err;
511 }
512 startup_uart_controller(port);
513 enable_irq(port->irq);
514irq_err:
515 return ret;
516}
517
518static void sirfsoc_uart_shutdown(struct uart_port *port)
519{
520 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
521 wr_regl(port, SIRFUART_INT_EN, 0);
522 free_irq(port->irq, sirfport);
523 if (sirfport->ms_enabled) {
524 sirfsoc_uart_disable_ms(port);
525 sirfport->ms_enabled = 0;
526 }
527}
528
529static const char *sirfsoc_uart_type(struct uart_port *port)
530{
531 return port->type == SIRFSOC_PORT_TYPE ? SIRFUART_PORT_NAME : NULL;
532}
533
534static int sirfsoc_uart_request_port(struct uart_port *port)
535{
536 void *ret;
537 ret = request_mem_region(port->mapbase,
538 SIRFUART_MAP_SIZE, SIRFUART_PORT_NAME);
539 return ret ? 0 : -EBUSY;
540}
541
542static void sirfsoc_uart_release_port(struct uart_port *port)
543{
544 release_mem_region(port->mapbase, SIRFUART_MAP_SIZE);
545}
546
547static void sirfsoc_uart_config_port(struct uart_port *port, int flags)
548{
549 if (flags & UART_CONFIG_TYPE) {
550 port->type = SIRFSOC_PORT_TYPE;
551 sirfsoc_uart_request_port(port);
552 }
553}
554
555static struct uart_ops sirfsoc_uart_ops = {
556 .tx_empty = sirfsoc_uart_tx_empty,
557 .get_mctrl = sirfsoc_uart_get_mctrl,
558 .set_mctrl = sirfsoc_uart_set_mctrl,
559 .stop_tx = sirfsoc_uart_stop_tx,
560 .start_tx = sirfsoc_uart_start_tx,
561 .stop_rx = sirfsoc_uart_stop_rx,
562 .enable_ms = sirfsoc_uart_enable_ms,
563 .break_ctl = sirfsoc_uart_break_ctl,
564 .startup = sirfsoc_uart_startup,
565 .shutdown = sirfsoc_uart_shutdown,
566 .set_termios = sirfsoc_uart_set_termios,
567 .type = sirfsoc_uart_type,
568 .release_port = sirfsoc_uart_release_port,
569 .request_port = sirfsoc_uart_request_port,
570 .config_port = sirfsoc_uart_config_port,
571};
572
573#ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
574static int __init sirfsoc_uart_console_setup(struct console *co, char *options)
575{
576 unsigned int baud = 115200;
577 unsigned int bits = 8;
578 unsigned int parity = 'n';
579 unsigned int flow = 'n';
580 struct uart_port *port = &sirfsoc_uart_ports[co->index].port;
581
582 if (co->index < 0 || co->index >= SIRFSOC_UART_NR)
583 return -EINVAL;
584
585 if (!port->mapbase)
586 return -ENODEV;
587
588 if (options)
589 uart_parse_options(options, &baud, &parity, &bits, &flow);
590 port->cons = co;
591 return uart_set_options(port, co, baud, parity, bits, flow);
592}
593
594static void sirfsoc_uart_console_putchar(struct uart_port *port, int ch)
595{
596 while (rd_regl(port,
597 SIRFUART_TX_FIFO_STATUS) & SIRFUART_FIFOFULL_MASK(port))
598 cpu_relax();
599 wr_regb(port, SIRFUART_TX_FIFO_DATA, ch);
600}
601
602static void sirfsoc_uart_console_write(struct console *co, const char *s,
603 unsigned int count)
604{
605 struct uart_port *port = &sirfsoc_uart_ports[co->index].port;
606 uart_console_write(port, s, count, sirfsoc_uart_console_putchar);
607}
608
609static struct console sirfsoc_uart_console = {
610 .name = SIRFSOC_UART_NAME,
611 .device = uart_console_device,
612 .flags = CON_PRINTBUFFER,
613 .index = -1,
614 .write = sirfsoc_uart_console_write,
615 .setup = sirfsoc_uart_console_setup,
616 .data = &sirfsoc_uart_drv,
617};
618
619static int __init sirfsoc_uart_console_init(void)
620{
621 register_console(&sirfsoc_uart_console);
622 return 0;
623}
624console_initcall(sirfsoc_uart_console_init);
625#endif
626
627static struct uart_driver sirfsoc_uart_drv = {
628 .owner = THIS_MODULE,
629 .driver_name = SIRFUART_PORT_NAME,
630 .nr = SIRFSOC_UART_NR,
631 .dev_name = SIRFSOC_UART_NAME,
632 .major = SIRFSOC_UART_MAJOR,
633 .minor = SIRFSOC_UART_MINOR,
634#ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
635 .cons = &sirfsoc_uart_console,
636#else
637 .cons = NULL,
638#endif
639};
640
641int sirfsoc_uart_probe(struct platform_device *pdev)
642{
643 struct sirfsoc_uart_port *sirfport;
644 struct uart_port *port;
645 struct resource *res;
646 int ret;
647
648 if (of_property_read_u32(pdev->dev.of_node, "cell-index", &pdev->id)) {
649 dev_err(&pdev->dev,
650 "Unable to find cell-index in uart node.\n");
651 ret = -EFAULT;
652 goto err;
653 }
654
655 sirfport = &sirfsoc_uart_ports[pdev->id];
656 port = &sirfport->port;
657 port->dev = &pdev->dev;
658 port->private_data = sirfport;
659
660 if (of_find_property(pdev->dev.of_node, "hw_flow_ctrl", NULL))
661 sirfport->hw_flow_ctrl = 1;
662
663 if (of_property_read_u32(pdev->dev.of_node,
664 "fifosize",
665 &port->fifosize)) {
666 dev_err(&pdev->dev,
667 "Unable to find fifosize in uart node.\n");
668 ret = -EFAULT;
669 goto err;
670 }
671
672 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
673 if (res == NULL) {
674 dev_err(&pdev->dev, "Insufficient resources.\n");
675 ret = -EFAULT;
676 goto err;
677 }
678 port->mapbase = res->start;
679 port->membase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
680 if (!port->membase) {
681 dev_err(&pdev->dev, "Cannot remap resource.\n");
682 ret = -ENOMEM;
683 goto err;
684 }
685 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
686 if (res == NULL) {
687 dev_err(&pdev->dev, "Insufficient resources.\n");
688 ret = -EFAULT;
Julia Lawall9250dd52012-09-01 18:33:09 +0200689 goto err;
Rong Wang161e7732011-11-17 23:17:04 +0800690 }
691 port->irq = res->start;
692
693 if (sirfport->hw_flow_ctrl) {
Stephen Warren6e5e9592012-03-02 13:05:47 -0700694 sirfport->p = pinctrl_get_select_default(&pdev->dev);
Linus Walleij5c9bdc32012-02-16 19:36:21 +0100695 ret = IS_ERR(sirfport->p);
Rong Wang161e7732011-11-17 23:17:04 +0800696 if (ret)
Julia Lawall9250dd52012-09-01 18:33:09 +0200697 goto err;
Rong Wang161e7732011-11-17 23:17:04 +0800698 }
699
700 port->ops = &sirfsoc_uart_ops;
701 spin_lock_init(&port->lock);
702
703 platform_set_drvdata(pdev, sirfport);
704 ret = uart_add_one_port(&sirfsoc_uart_drv, port);
705 if (ret != 0) {
706 dev_err(&pdev->dev, "Cannot add UART port(%d).\n", pdev->id);
707 goto port_err;
708 }
709
710 return 0;
711
712port_err:
713 platform_set_drvdata(pdev, NULL);
Stephen Warren6e5e9592012-03-02 13:05:47 -0700714 if (sirfport->hw_flow_ctrl)
Linus Walleij5c9bdc32012-02-16 19:36:21 +0100715 pinctrl_put(sirfport->p);
Rong Wang161e7732011-11-17 23:17:04 +0800716err:
717 return ret;
718}
719
720static int sirfsoc_uart_remove(struct platform_device *pdev)
721{
722 struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
723 struct uart_port *port = &sirfport->port;
724 platform_set_drvdata(pdev, NULL);
Stephen Warren6e5e9592012-03-02 13:05:47 -0700725 if (sirfport->hw_flow_ctrl)
Linus Walleij5c9bdc32012-02-16 19:36:21 +0100726 pinctrl_put(sirfport->p);
Rong Wang161e7732011-11-17 23:17:04 +0800727 uart_remove_one_port(&sirfsoc_uart_drv, port);
728 return 0;
729}
730
731static int
732sirfsoc_uart_suspend(struct platform_device *pdev, pm_message_t state)
733{
734 struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
735 struct uart_port *port = &sirfport->port;
736 uart_suspend_port(&sirfsoc_uart_drv, port);
737 return 0;
738}
739
740static int sirfsoc_uart_resume(struct platform_device *pdev)
741{
742 struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
743 struct uart_port *port = &sirfport->port;
744 uart_resume_port(&sirfsoc_uart_drv, port);
745 return 0;
746}
747
Bill Pembertonde88b342012-11-19 13:24:32 -0500748static struct of_device_id sirfsoc_uart_ids[] = {
Rong Wang161e7732011-11-17 23:17:04 +0800749 { .compatible = "sirf,prima2-uart", },
Barry Song5425e032012-12-25 17:32:04 +0800750 { .compatible = "sirf,marco-uart", },
Rong Wang161e7732011-11-17 23:17:04 +0800751 {}
752};
753MODULE_DEVICE_TABLE(of, sirfsoc_serial_of_match);
754
755static struct platform_driver sirfsoc_uart_driver = {
756 .probe = sirfsoc_uart_probe,
Bill Pemberton2d47b712012-11-19 13:21:34 -0500757 .remove = sirfsoc_uart_remove,
Rong Wang161e7732011-11-17 23:17:04 +0800758 .suspend = sirfsoc_uart_suspend,
759 .resume = sirfsoc_uart_resume,
760 .driver = {
761 .name = SIRFUART_PORT_NAME,
762 .owner = THIS_MODULE,
763 .of_match_table = sirfsoc_uart_ids,
764 },
765};
766
767static int __init sirfsoc_uart_init(void)
768{
769 int ret = 0;
770
771 ret = uart_register_driver(&sirfsoc_uart_drv);
772 if (ret)
773 goto out;
774
775 ret = platform_driver_register(&sirfsoc_uart_driver);
776 if (ret)
777 uart_unregister_driver(&sirfsoc_uart_drv);
778out:
779 return ret;
780}
781module_init(sirfsoc_uart_init);
782
783static void __exit sirfsoc_uart_exit(void)
784{
785 platform_driver_unregister(&sirfsoc_uart_driver);
786 uart_unregister_driver(&sirfsoc_uart_drv);
787}
788module_exit(sirfsoc_uart_exit);
789
790MODULE_LICENSE("GPL v2");
791MODULE_AUTHOR("Bin Shi <Bin.Shi@csr.com>, Rong Wang<Rong.Wang@csr.com>");
792MODULE_DESCRIPTION("CSR SiRFprimaII Uart Driver");