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Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * pata_hpt3x3 - HPT3x3 driver
3 * (c) Copyright 2005-2006 Red Hat
4 *
5 * Was pata_hpt34x but the naming was confusing as it supported the
6 * 343 and 363 so it has been renamed.
7 *
8 * Based on:
9 * linux/drivers/ide/pci/hpt34x.c Version 0.40 Sept 10, 2002
10 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
11 *
12 * May be copied or modified under the terms of the GNU General Public
13 * License
14 */
Jeff Garzik85cd7252006-08-31 00:03:49 -040015
Jeff Garzik669a5db2006-08-29 18:12:40 -040016#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/pci.h>
19#include <linux/init.h>
20#include <linux/blkdev.h>
21#include <linux/delay.h>
22#include <scsi/scsi_host.h>
23#include <linux/libata.h>
24
25#define DRV_NAME "pata_hpt3x3"
Alan Cox978ff6d2009-01-05 14:12:51 +000026#define DRV_VERSION "0.6.1"
Jeff Garzik669a5db2006-08-29 18:12:40 -040027
Jeff Garzik669a5db2006-08-29 18:12:40 -040028/**
29 * hpt3x3_set_piomode - PIO setup
30 * @ap: ATA interface
31 * @adev: device on the interface
32 *
33 * Set our PIO requirements. This is fairly simple on the HPT3x3 as
34 * all we have to do is clear the MWDMA and UDMA bits then load the
35 * mode number.
36 */
37
38static void hpt3x3_set_piomode(struct ata_port *ap, struct ata_device *adev)
39{
40 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
41 u32 r1, r2;
42 int dn = 2 * ap->port_no + adev->devno;
43
44 pci_read_config_dword(pdev, 0x44, &r1);
45 pci_read_config_dword(pdev, 0x48, &r2);
46 /* Load the PIO timing number */
47 r1 &= ~(7 << (3 * dn));
48 r1 |= (adev->pio_mode - XFER_PIO_0) << (3 * dn);
49 r2 &= ~(0x11 << dn); /* Clear MWDMA and UDMA bits */
50
51 pci_write_config_dword(pdev, 0x44, r1);
52 pci_write_config_dword(pdev, 0x48, r2);
53}
54
Jeff Garzik790956e2007-07-10 21:36:13 -040055#if defined(CONFIG_PATA_HPT3X3_DMA)
Jeff Garzik669a5db2006-08-29 18:12:40 -040056/**
57 * hpt3x3_set_dmamode - DMA timing setup
58 * @ap: ATA interface
59 * @adev: Device being configured
60 *
61 * Set up the channel for MWDMA or UDMA modes. Much the same as with
62 * PIO, load the mode number and then set MWDMA or UDMA flag.
Alan Cox66e7da42007-07-09 11:46:22 -070063 *
64 * 0x44 : bit 0-2 master mode, 3-5 slave mode, etc
65 * 0x48 : bit 4/0 DMA/UDMA bit 5/1 for slave etc
Jeff Garzik669a5db2006-08-29 18:12:40 -040066 */
67
68static void hpt3x3_set_dmamode(struct ata_port *ap, struct ata_device *adev)
69{
70 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
71 u32 r1, r2;
72 int dn = 2 * ap->port_no + adev->devno;
73 int mode_num = adev->dma_mode & 0x0F;
74
75 pci_read_config_dword(pdev, 0x44, &r1);
76 pci_read_config_dword(pdev, 0x48, &r2);
77 /* Load the timing number */
78 r1 &= ~(7 << (3 * dn));
79 r1 |= (mode_num << (3 * dn));
80 r2 &= ~(0x11 << dn); /* Clear MWDMA and UDMA bits */
81
82 if (adev->dma_mode >= XFER_UDMA_0)
Alan Cox978ff6d2009-01-05 14:12:51 +000083 r2 |= (0x01 << dn); /* Ultra mode */
Jeff Garzik669a5db2006-08-29 18:12:40 -040084 else
Alan Cox978ff6d2009-01-05 14:12:51 +000085 r2 |= (0x10 << dn); /* MWDMA */
Jeff Garzik669a5db2006-08-29 18:12:40 -040086
87 pci_write_config_dword(pdev, 0x44, r1);
88 pci_write_config_dword(pdev, 0x48, r2);
89}
Alan Cox978ff6d2009-01-05 14:12:51 +000090
91/**
92 * hpt3x3_freeze - DMA workaround
93 * @ap: port to freeze
94 *
95 * When freezing an HPT3x3 we must stop any pending DMA before
96 * writing to the control register or the chip will hang
97 */
98
Jeff Garzikb63d3952009-01-08 16:28:21 -050099static void hpt3x3_freeze(struct ata_port *ap)
Alan Cox978ff6d2009-01-05 14:12:51 +0000100{
101 void __iomem *mmio = ap->ioaddr.bmdma_addr;
102
103 iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ ATA_DMA_START,
104 mmio + ATA_DMA_CMD);
105 ata_sff_dma_pause(ap);
106 ata_sff_freeze(ap);
107}
108
109/**
110 * hpt3x3_bmdma_setup - DMA workaround
111 * @qc: Queued command
112 *
113 * When issuing BMDMA we must clean up the error/active bits in
114 * software on this device
115 */
116
117static void hpt3x3_bmdma_setup(struct ata_queued_cmd *qc)
118{
119 struct ata_port *ap = qc->ap;
120 u8 r = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
121 r |= ATA_DMA_INTR | ATA_DMA_ERR;
122 iowrite8(r, ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
123 return ata_bmdma_setup(qc);
124}
Jeff Garzik669a5db2006-08-29 18:12:40 -0400125
Alan Cox66e7da42007-07-09 11:46:22 -0700126/**
127 * hpt3x3_atapi_dma - ATAPI DMA check
128 * @qc: Queued command
129 *
130 * Just say no - we don't do ATAPI DMA
131 */
132
133static int hpt3x3_atapi_dma(struct ata_queued_cmd *qc)
134{
135 return 1;
136}
137
Alan Cox978ff6d2009-01-05 14:12:51 +0000138#endif /* CONFIG_PATA_HPT3X3_DMA */
139
Jeff Garzik669a5db2006-08-29 18:12:40 -0400140static struct scsi_host_template hpt3x3_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900141 ATA_BMDMA_SHT(DRV_NAME),
Jeff Garzik669a5db2006-08-29 18:12:40 -0400142};
143
144static struct ata_port_operations hpt3x3_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900145 .inherits = &ata_bmdma_port_ops,
Tejun Heo029cfd62008-03-25 12:22:49 +0900146 .cable_detect = ata_cable_40wire,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400147 .set_piomode = hpt3x3_set_piomode,
Jeff Garzik790956e2007-07-10 21:36:13 -0400148#if defined(CONFIG_PATA_HPT3X3_DMA)
149 .set_dmamode = hpt3x3_set_dmamode,
Alan Cox978ff6d2009-01-05 14:12:51 +0000150 .bmdma_setup = hpt3x3_bmdma_setup,
151 .check_atapi_dma= hpt3x3_atapi_dma,
152 .freeze = hpt3x3_freeze,
Jeff Garzik790956e2007-07-10 21:36:13 -0400153#endif
Alan Cox978ff6d2009-01-05 14:12:51 +0000154
Jeff Garzik669a5db2006-08-29 18:12:40 -0400155};
156
157/**
Alanaff0df02006-11-27 16:25:51 +0000158 * hpt3x3_init_chipset - chip setup
159 * @dev: PCI device
160 *
161 * Perform the setup required at boot and on resume.
162 */
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500163
Alanaff0df02006-11-27 16:25:51 +0000164static void hpt3x3_init_chipset(struct pci_dev *dev)
165{
166 u16 cmd;
167 /* Initialize the board */
168 pci_write_config_word(dev, 0x80, 0x00);
169 /* Check if it is a 343 or a 363. 363 has COMMAND_MEMORY set */
170 pci_read_config_word(dev, PCI_COMMAND, &cmd);
171 if (cmd & PCI_COMMAND_MEMORY)
172 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
173 else
174 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
175}
176
Alanaff0df02006-11-27 16:25:51 +0000177/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400178 * hpt3x3_init_one - Initialise an HPT343/363
Alan Cox66e7da42007-07-09 11:46:22 -0700179 * @pdev: PCI device
Jeff Garzik669a5db2006-08-29 18:12:40 -0400180 * @id: Entry in match table
181 *
Alan Cox66e7da42007-07-09 11:46:22 -0700182 * Perform basic initialisation. We set the device up so we access all
183 * ports via BAR4. This is neccessary to work around errata.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400184 */
185
Alan Cox66e7da42007-07-09 11:46:22 -0700186static int hpt3x3_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400187{
Alan Cox66e7da42007-07-09 11:46:22 -0700188 static int printed_version;
Tejun Heo1626aeb2007-05-04 12:43:58 +0200189 static const struct ata_port_info info = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400190 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100191 .pio_mask = ATA_PIO4,
Alan Cox66e7da42007-07-09 11:46:22 -0700192#if defined(CONFIG_PATA_HPT3X3_DMA)
193 /* Further debug needed */
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100194 .mwdma_mask = ATA_MWDMA2,
195 .udma_mask = ATA_UDMA2,
Alan Cox66e7da42007-07-09 11:46:22 -0700196#endif
Jeff Garzik669a5db2006-08-29 18:12:40 -0400197 .port_ops = &hpt3x3_port_ops
198 };
Alan Cox66e7da42007-07-09 11:46:22 -0700199 /* Register offsets of taskfiles in BAR4 area */
200 static const u8 offset_cmd[2] = { 0x20, 0x28 };
201 static const u8 offset_ctl[2] = { 0x36, 0x3E };
Tejun Heo1626aeb2007-05-04 12:43:58 +0200202 const struct ata_port_info *ppi[] = { &info, NULL };
Alan Cox66e7da42007-07-09 11:46:22 -0700203 struct ata_host *host;
204 int i, rc;
205 void __iomem *base;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400206
Alan Cox66e7da42007-07-09 11:46:22 -0700207 hpt3x3_init_chipset(pdev);
208
209 if (!printed_version++)
210 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
211
212 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
213 if (!host)
214 return -ENOMEM;
215 /* acquire resources and fill host */
216 rc = pcim_enable_device(pdev);
217 if (rc)
218 return rc;
219
220 /* Everything is relative to BAR4 if we set up this way */
221 rc = pcim_iomap_regions(pdev, 1 << 4, DRV_NAME);
222 if (rc == -EBUSY)
223 pcim_pin_device(pdev);
224 if (rc)
225 return rc;
226 host->iomap = pcim_iomap_table(pdev);
227 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
228 if (rc)
229 return rc;
230 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
231 if (rc)
232 return rc;
233
234 base = host->iomap[4]; /* Bus mastering base */
235
236 for (i = 0; i < host->n_ports; i++) {
Tejun Heocbcdd872007-08-18 13:14:55 +0900237 struct ata_port *ap = host->ports[i];
238 struct ata_ioports *ioaddr = &ap->ioaddr;
Alan Cox66e7da42007-07-09 11:46:22 -0700239
240 ioaddr->cmd_addr = base + offset_cmd[i];
241 ioaddr->altstatus_addr =
242 ioaddr->ctl_addr = base + offset_ctl[i];
243 ioaddr->scr_addr = NULL;
Tejun Heo9363c382008-04-07 22:47:16 +0900244 ata_sff_std_ports(ioaddr);
Alan Cox66e7da42007-07-09 11:46:22 -0700245 ioaddr->bmdma_addr = base + 8 * i;
Tejun Heocbcdd872007-08-18 13:14:55 +0900246
247 ata_port_pbar_desc(ap, 4, -1, "ioport");
248 ata_port_pbar_desc(ap, 4, offset_cmd[i], "cmd");
Alan Cox66e7da42007-07-09 11:46:22 -0700249 }
250 pci_set_master(pdev);
Tejun Heo9363c382008-04-07 22:47:16 +0900251 return ata_host_activate(host, pdev->irq, ata_sff_interrupt,
252 IRQF_SHARED, &hpt3x3_sht);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400253}
254
Tejun Heo438ac6d2007-03-02 17:31:26 +0900255#ifdef CONFIG_PM
Alanaff0df02006-11-27 16:25:51 +0000256static int hpt3x3_reinit_one(struct pci_dev *dev)
257{
258 hpt3x3_init_chipset(dev);
259 return ata_pci_device_resume(dev);
260}
Tejun Heo438ac6d2007-03-02 17:31:26 +0900261#endif
Alanaff0df02006-11-27 16:25:51 +0000262
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400263static const struct pci_device_id hpt3x3[] = {
264 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT343), },
265
266 { },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400267};
268
269static struct pci_driver hpt3x3_pci_driver = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400270 .name = DRV_NAME,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400271 .id_table = hpt3x3,
272 .probe = hpt3x3_init_one,
Alanaff0df02006-11-27 16:25:51 +0000273 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900274#ifdef CONFIG_PM
Alanaff0df02006-11-27 16:25:51 +0000275 .suspend = ata_pci_device_suspend,
276 .resume = hpt3x3_reinit_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900277#endif
Jeff Garzik669a5db2006-08-29 18:12:40 -0400278};
279
280static int __init hpt3x3_init(void)
281{
282 return pci_register_driver(&hpt3x3_pci_driver);
283}
284
285
286static void __exit hpt3x3_exit(void)
287{
288 pci_unregister_driver(&hpt3x3_pci_driver);
289}
290
291
292MODULE_AUTHOR("Alan Cox");
293MODULE_DESCRIPTION("low-level driver for the Highpoint HPT343/363");
294MODULE_LICENSE("GPL");
295MODULE_DEVICE_TABLE(pci, hpt3x3);
296MODULE_VERSION(DRV_VERSION);
297
298module_init(hpt3x3_init);
Jeff Garzikb63d3952009-01-08 16:28:21 -0500299module_exit(hpt3x3_exit);