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Hans Verkuil54450f52012-07-18 05:45:16 -03001/*
2 * adv7604 - Analog Devices ADV7604 video decoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21#ifndef _ADV7604_
22#define _ADV7604_
23
24/* Analog input muxing modes (AFE register 0x02, [2:0]) */
25enum adv7604_ain_sel {
26 ADV7604_AIN1_2_3_NC_SYNC_1_2 = 0,
27 ADV7604_AIN4_5_6_NC_SYNC_2_1 = 1,
28 ADV7604_AIN7_8_9_NC_SYNC_3_1 = 2,
29 ADV7604_AIN10_11_12_NC_SYNC_4_1 = 3,
30 ADV7604_AIN9_4_5_6_SYNC_2_1 = 4,
31};
32
33/* Bus rotation and reordering (IO register 0x04, [7:5]) */
34enum adv7604_op_ch_sel {
35 ADV7604_OP_CH_SEL_GBR = 0,
36 ADV7604_OP_CH_SEL_GRB = 1,
37 ADV7604_OP_CH_SEL_BGR = 2,
38 ADV7604_OP_CH_SEL_RGB = 3,
39 ADV7604_OP_CH_SEL_BRG = 4,
40 ADV7604_OP_CH_SEL_RBG = 5,
41};
42
43/* Primary mode (IO register 0x01, [3:0]) */
44enum adv7604_prim_mode {
45 ADV7604_PRIM_MODE_COMP = 1,
46 ADV7604_PRIM_MODE_RGB = 2,
47 ADV7604_PRIM_MODE_HDMI_COMP = 5,
48 ADV7604_PRIM_MODE_HDMI_GR = 6,
49};
50
51/* Input Color Space (IO register 0x02, [7:4]) */
52enum adv7604_inp_color_space {
53 ADV7604_INP_COLOR_SPACE_LIM_RGB = 0,
54 ADV7604_INP_COLOR_SPACE_FULL_RGB = 1,
55 ADV7604_INP_COLOR_SPACE_LIM_YCbCr_601 = 2,
56 ADV7604_INP_COLOR_SPACE_LIM_YCbCr_709 = 3,
57 ADV7604_INP_COLOR_SPACE_XVYCC_601 = 4,
58 ADV7604_INP_COLOR_SPACE_XVYCC_709 = 5,
59 ADV7604_INP_COLOR_SPACE_FULL_YCbCr_601 = 6,
60 ADV7604_INP_COLOR_SPACE_FULL_YCbCr_709 = 7,
61 ADV7604_INP_COLOR_SPACE_AUTO = 0xf,
62};
63
64/* Select output format (IO register 0x03, [7:0]) */
65enum adv7604_op_format_sel {
66 ADV7604_OP_FORMAT_SEL_SDR_ITU656_8 = 0x00,
67 ADV7604_OP_FORMAT_SEL_SDR_ITU656_10 = 0x01,
68 ADV7604_OP_FORMAT_SEL_SDR_ITU656_12_MODE0 = 0x02,
69 ADV7604_OP_FORMAT_SEL_SDR_ITU656_12_MODE1 = 0x06,
70 ADV7604_OP_FORMAT_SEL_SDR_ITU656_12_MODE2 = 0x0a,
71 ADV7604_OP_FORMAT_SEL_DDR_422_8 = 0x20,
72 ADV7604_OP_FORMAT_SEL_DDR_422_10 = 0x21,
73 ADV7604_OP_FORMAT_SEL_DDR_422_12_MODE0 = 0x22,
74 ADV7604_OP_FORMAT_SEL_DDR_422_12_MODE1 = 0x23,
75 ADV7604_OP_FORMAT_SEL_DDR_422_12_MODE2 = 0x24,
76 ADV7604_OP_FORMAT_SEL_SDR_444_24 = 0x40,
77 ADV7604_OP_FORMAT_SEL_SDR_444_30 = 0x41,
78 ADV7604_OP_FORMAT_SEL_SDR_444_36_MODE0 = 0x42,
79 ADV7604_OP_FORMAT_SEL_DDR_444_24 = 0x60,
80 ADV7604_OP_FORMAT_SEL_DDR_444_30 = 0x61,
81 ADV7604_OP_FORMAT_SEL_DDR_444_36 = 0x62,
82 ADV7604_OP_FORMAT_SEL_SDR_ITU656_16 = 0x80,
83 ADV7604_OP_FORMAT_SEL_SDR_ITU656_20 = 0x81,
84 ADV7604_OP_FORMAT_SEL_SDR_ITU656_24_MODE0 = 0x82,
85 ADV7604_OP_FORMAT_SEL_SDR_ITU656_24_MODE1 = 0x86,
86 ADV7604_OP_FORMAT_SEL_SDR_ITU656_24_MODE2 = 0x8a,
87};
88
89/* Platform dependent definition */
90struct adv7604_platform_data {
91 /* connector - HDMI or DVI? */
92 unsigned connector_hdmi:1;
93
94 /* DIS_PWRDNB: 1 if the PWRDNB pin is unused and unconnected */
95 unsigned disable_pwrdnb:1;
96
97 /* DIS_CABLE_DET_RST: 1 if the 5V pins are unused and unconnected */
98 unsigned disable_cable_det_rst:1;
99
100 /* Analog input muxing mode */
101 enum adv7604_ain_sel ain_sel;
102
103 /* Bus rotation and reordering */
104 enum adv7604_op_ch_sel op_ch_sel;
105
106 /* Primary mode */
107 enum adv7604_prim_mode prim_mode;
108
109 /* Select output format */
110 enum adv7604_op_format_sel op_format_sel;
111
112 /* IO register 0x02 */
113 unsigned alt_gamma:1;
114 unsigned op_656_range:1;
115 unsigned rgb_out:1;
116 unsigned alt_data_sat:1;
117
118 /* IO register 0x05 */
119 unsigned blank_data:1;
120 unsigned insert_av_codes:1;
121 unsigned replicate_av_codes:1;
122 unsigned invert_cbcr:1;
123
124 /* IO register 0x30 */
125 unsigned output_bus_lsb_to_msb:1;
126
127 /* Free run */
128 unsigned hdmi_free_run_mode;
129
130 /* i2c addresses: 0 == use default */
131 u8 i2c_avlink;
132 u8 i2c_cec;
133 u8 i2c_infoframe;
134 u8 i2c_esdp;
135 u8 i2c_dpp;
136 u8 i2c_afe;
137 u8 i2c_repeater;
138 u8 i2c_edid;
139 u8 i2c_hdmi;
140 u8 i2c_test;
141 u8 i2c_cp;
142 u8 i2c_vdp;
143};
144
145#define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE (V4L2_CID_DV_CLASS_BASE + 0x1000)
146#define V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL (V4L2_CID_DV_CLASS_BASE + 0x1001)
147#define V4L2_CID_ADV_RX_FREE_RUN_COLOR (V4L2_CID_DV_CLASS_BASE + 0x1002)
148
149/* notify events */
150#define ADV7604_HOTPLUG 1
151#define ADV7604_FMT_CHANGE 2
152
153#endif