| David Howells | b75bb23 | 2011-03-18 16:54:29 +0000 | [diff] [blame] | 1 | /* MN10300 CPU core caching macros -*- asm -*- |
| 2 | * |
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. |
| 4 | * Written by David Howells (dhowells@redhat.com) |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public Licence |
| 8 | * as published by the Free Software Foundation; either version |
| 9 | * 2 of the Licence, or (at your option) any later version. |
| 10 | */ |
| 11 | |
| 12 | |
| 13 | ############################################################################### |
| 14 | # |
| 15 | # Invalidate the instruction cache. |
| 16 | # A0: Should hold CHCTR |
| 17 | # D0: Should have been read from CHCTR |
| 18 | # D1: Will be clobbered |
| 19 | # |
| 20 | # On some cores it is necessary to disable the icache whilst we do this. |
| 21 | # |
| 22 | ############################################################################### |
| 23 | .macro invalidate_icache,disable_irq |
| 24 | |
| 25 | #if defined(CONFIG_AM33_2) || defined(CONFIG_AM33_3) |
| 26 | .if \disable_irq |
| 27 | # don't want an interrupt routine seeing a disabled cache |
| 28 | mov epsw,d1 |
| 29 | and ~EPSW_IE,epsw |
| 30 | or EPSW_NMID,epsw |
| 31 | nop |
| 32 | nop |
| 33 | .endif |
| 34 | |
| 35 | # disable the icache |
| 36 | and ~CHCTR_ICEN,d0 |
| 37 | movhu d0,(a0) |
| 38 | |
| 39 | # and wait for it to calm down |
| 40 | setlb |
| 41 | movhu (a0),d0 |
| 42 | btst CHCTR_ICBUSY,d0 |
| 43 | lne |
| 44 | |
| 45 | # invalidate |
| 46 | or CHCTR_ICINV,d0 |
| 47 | movhu d0,(a0) |
| 48 | |
| 49 | # wait for the cache to finish |
| 50 | setlb |
| 51 | movhu (a0),d0 |
| 52 | btst CHCTR_ICBUSY,d0 |
| 53 | lne |
| 54 | |
| 55 | # and reenable it |
| 56 | or CHCTR_ICEN,d0 |
| 57 | movhu d0,(a0) |
| 58 | movhu (a0),d0 |
| 59 | |
| 60 | .if \disable_irq |
| 61 | LOCAL_IRQ_RESTORE(d1) |
| 62 | .endif |
| 63 | |
| 64 | #else /* CONFIG_AM33_2 || CONFIG_AM33_3 */ |
| 65 | |
| 66 | # invalidate |
| 67 | or CHCTR_ICINV,d0 |
| 68 | movhu d0,(a0) |
| 69 | movhu (a0),d0 |
| 70 | |
| 71 | #endif /* CONFIG_AM33_2 || CONFIG_AM33_3 */ |
| 72 | .endm |
| 73 | |
| 74 | ############################################################################### |
| 75 | # |
| 76 | # Invalidate the data cache. |
| 77 | # A0: Should hold CHCTR |
| 78 | # D0: Should have been read from CHCTR |
| 79 | # D1: Will be clobbered |
| 80 | # |
| 81 | # On some cores it is necessary to disable the dcache whilst we do this. |
| 82 | # |
| 83 | ############################################################################### |
| 84 | .macro invalidate_dcache,disable_irq |
| 85 | |
| 86 | #if defined(CONFIG_AM33_2) || defined(CONFIG_AM33_3) |
| 87 | .if \disable_irq |
| 88 | # don't want an interrupt routine seeing a disabled cache |
| 89 | mov epsw,d1 |
| 90 | and ~EPSW_IE,epsw |
| 91 | or EPSW_NMID,epsw |
| 92 | nop |
| 93 | nop |
| 94 | .endif |
| 95 | |
| 96 | # disable the dcache |
| 97 | and ~CHCTR_DCEN,d0 |
| 98 | movhu d0,(a0) |
| 99 | |
| 100 | # and wait for it to calm down |
| 101 | setlb |
| 102 | movhu (a0),d0 |
| 103 | btst CHCTR_DCBUSY,d0 |
| 104 | lne |
| 105 | |
| 106 | # invalidate |
| 107 | or CHCTR_DCINV,d0 |
| 108 | movhu d0,(a0) |
| 109 | |
| 110 | # wait for the cache to finish |
| 111 | setlb |
| 112 | movhu (a0),d0 |
| 113 | btst CHCTR_DCBUSY,d0 |
| 114 | lne |
| 115 | |
| 116 | # and reenable it |
| 117 | or CHCTR_DCEN,d0 |
| 118 | movhu d0,(a0) |
| 119 | movhu (a0),d0 |
| 120 | |
| 121 | .if \disable_irq |
| 122 | LOCAL_IRQ_RESTORE(d1) |
| 123 | .endif |
| 124 | |
| 125 | #else /* CONFIG_AM33_2 || CONFIG_AM33_3 */ |
| 126 | |
| 127 | # invalidate |
| 128 | or CHCTR_DCINV,d0 |
| 129 | movhu d0,(a0) |
| 130 | movhu (a0),d0 |
| 131 | |
| 132 | #endif /* CONFIG_AM33_2 || CONFIG_AM33_3 */ |
| 133 | .endm |