blob: 007f3c24d3f2981cf684d78019b467fc7d5f36b0 [file] [log] [blame]
Benjamin Herrenschmidt61974032007-12-21 15:39:26 +11001/*
2 * Device Tree Source for EP405
3 *
4 * Copyright 2007 IBM Corp.
5 * Benjamin Herrenschmidt <benh@kernel.crashing.org>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without
9 * any warranty of any kind, whether express or implied.
10 */
11
12/ {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 model = "ep405";
16 compatible = "ep405";
17 dcr-parent = <&/cpus/PowerPC,405GP@0>;
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 PowerPC,405GP@0 {
24 device_type = "cpu";
25 reg = <0>;
26 clock-frequency = <bebc200>; /* Filled in by zImage */
27 timebase-frequency = <0>; /* Filled in by zImage */
28 i-cache-line-size = <20>;
29 d-cache-line-size = <20>;
30 i-cache-size = <4000>;
31 d-cache-size = <4000>;
32 dcr-controller;
33 dcr-access-method = "native";
34 };
35 };
36
37 memory {
38 device_type = "memory";
39 reg = <0 0>; /* Filled in by zImage */
40 };
41
42 UIC0: interrupt-controller {
43 compatible = "ibm,uic";
44 interrupt-controller;
45 cell-index = <0>;
46 dcr-reg = <0c0 9>;
47 #address-cells = <0>;
48 #size-cells = <0>;
49 #interrupt-cells = <2>;
50 };
51
52 plb {
53 compatible = "ibm,plb3";
54 #address-cells = <1>;
55 #size-cells = <1>;
56 ranges;
57 clock-frequency = <0>; /* Filled in by zImage */
58
59 SDRAM0: memory-controller {
60 compatible = "ibm,sdram-405gp";
61 dcr-reg = <010 2>;
62 };
63
64 MAL: mcmal {
65 compatible = "ibm,mcmal-405gp", "ibm,mcmal";
66 dcr-reg = <180 62>;
67 num-tx-chans = <1>;
68 num-rx-chans = <1>;
69 interrupt-parent = <&UIC0>;
70 interrupts = <
71 b 4 /* TXEOB */
72 c 4 /* RXEOB */
73 a 4 /* SERR */
74 d 4 /* TXDE */
75 e 4 /* RXDE */>;
76 };
77
78 POB0: opb {
79 compatible = "ibm,opb-405gp", "ibm,opb";
80 #address-cells = <1>;
81 #size-cells = <1>;
82 ranges = <ef600000 ef600000 a00000>;
83 dcr-reg = <0a0 5>;
84 clock-frequency = <0>; /* Filled in by zImage */
85
86 UART0: serial@ef600300 {
87 device_type = "serial";
88 compatible = "ns16550";
89 reg = <ef600300 8>;
90 virtual-reg = <ef600300>;
91 clock-frequency = <0>; /* Filled in by zImage */
92 current-speed = <2580>;
93 interrupt-parent = <&UIC0>;
94 interrupts = <0 4>;
95 };
96
97 UART1: serial@ef600400 {
98 device_type = "serial";
99 compatible = "ns16550";
100 reg = <ef600400 8>;
101 virtual-reg = <ef600400>;
102 clock-frequency = <0>; /* Filled in by zImage */
103 current-speed = <2580>;
104 interrupt-parent = <&UIC0>;
105 interrupts = <1 4>;
106 };
107
108 IIC: i2c@ef600500 {
109 compatible = "ibm,iic-405gp", "ibm,iic";
110 reg = <ef600500 11>;
111 interrupt-parent = <&UIC0>;
112 interrupts = <2 4>;
113 };
114
115 GPIO: gpio@ef600700 {
116 compatible = "ibm,gpio-405gp";
117 reg = <ef600700 20>;
118 };
119
120 EMAC: ethernet@ef600800 {
121 linux,network-index = <0>;
122 device_type = "network";
123 compatible = "ibm,emac-405gp", "ibm,emac";
124 interrupt-parent = <&UIC0>;
125 interrupts = <
126 f 4 /* Ethernet */
127 9 4 /* Ethernet Wake Up */>;
128 local-mac-address = [000000000000]; /* Filled in by zImage */
129 reg = <ef600800 70>;
130 mal-device = <&MAL>;
131 mal-tx-channel = <0>;
132 mal-rx-channel = <0>;
133 cell-index = <0>;
134 max-frame-size = <5dc>;
135 rx-fifo-size = <1000>;
136 tx-fifo-size = <800>;
137 phy-mode = "rmii";
138 phy-map = <00000000>;
139 };
140
141 };
142
143 EBC0: ebc {
144 compatible = "ibm,ebc-405gp", "ibm,ebc";
145 dcr-reg = <012 2>;
146 #address-cells = <2>;
147 #size-cells = <1>;
148
149
150 /* The ranges property is supplied by the bootwrapper
151 * and is based on the firmware's configuration of the
152 * EBC bridge
153 */
154 clock-frequency = <0>; /* Filled in by zImage */
155
156 /* NVRAM and RTC */
157 nvrtc@4,200000 {
158 compatible = "ds1742";
159 reg = <4 200000 0>; /* size fixed up by zImage */
160 };
161
162 /* "BCSR" CPLD contains a PCI irq controller */
163 bcsr@4,0 {
164 compatible = "ep405-bcsr";
165 reg = <4 0 10>;
166 interrupt-controller;
167 /* Routing table */
168 irq-routing = [ 00 /* SYSERR */
169 01 /* STTM */
170 01 /* RTC */
171 01 /* FENET */
172 02 /* NB PCIIRQ mux ? */
173 03 /* SB Winbond 8259 ? */
174 04 /* Serial Ring */
175 05 /* USB (ep405pc) */
176 06 /* XIRQ 0 */
177 06 /* XIRQ 1 */
178 06 /* XIRQ 2 */
179 06 /* XIRQ 3 */
180 06 /* XIRQ 4 */
181 06 /* XIRQ 5 */
182 06 /* XIRQ 6 */
183 07]; /* Reserved */
184 };
185 };
186
187 PCI0: pci@ec000000 {
188 device_type = "pci";
189 #interrupt-cells = <1>;
190 #size-cells = <2>;
191 #address-cells = <3>;
192 compatible = "ibm,plb405gp-pci", "ibm,plb-pci";
193 primary;
194 reg = <eec00000 8 /* Config space access */
195 eed80000 4 /* IACK */
196 eed80000 4 /* Special cycle */
197 ef480000 40>; /* Internal registers */
198
199 /* Outbound ranges, one memory and one IO,
200 * later cannot be changed. Chip supports a second
201 * IO range but we don't use it for now
202 */
203 ranges = <02000000 0 80000000 80000000 0 20000000
204 01000000 0 00000000 e8000000 0 00010000>;
205
206 /* Inbound 2GB range starting at 0 */
207 dma-ranges = <42000000 0 0 0 0 80000000>;
208
209 /* That's all I know about IRQs on that thing ... */
210 interrupt-map-mask = <f800 0 0 0>;
211 interrupt-map = <
212 /* USB */
213 7000 0 0 0 &UIC0 1e 8 /* IRQ5 */
214 >;
215 };
216 };
217
218 chosen {
219 linux,stdout-path = "/plb/opb/serial@ef600300";
220 };
221};