blob: aa64a475278134eb3eafea4bb5cb7db40459b8da [file] [log] [blame]
Lew Glendenning29175772006-10-20 14:41:04 -07001/*
2 * esb2rom.c
3 *
4 * Normal mappings of flash chips in physical memory
5 * through the Intel ESB2 Southbridge.
6 *
7 * This was derived from ichxrom.c in May 2006 by
8 * Lew Glendenning <lglendenning@lnxi.com>
9 *
10 * Eric Biederman, of course, was a major help in this effort.
11 */
12
13#include <linux/module.h>
14#include <linux/types.h>
15#include <linux/version.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <asm/io.h>
19#include <linux/mtd/mtd.h>
20#include <linux/mtd/map.h>
21#include <linux/mtd/cfi.h>
22#include <linux/mtd/flashchip.h>
23#include <linux/pci.h>
24#include <linux/pci_ids.h>
25#include <linux/list.h>
26
27#define MOD_NAME KBUILD_BASENAME
28
29#define ADDRESS_NAME_LEN 18
30
31#define ROM_PROBE_STEP_SIZE (64*1024) /* 64KiB */
32
Cyrill Gorcunovdc164bb2007-03-06 02:39:45 -080033#define BIOS_CNTL 0xDC
Lew Glendenning29175772006-10-20 14:41:04 -070034#define BIOS_LOCK_ENABLE 0x02
35#define BIOS_WRITE_ENABLE 0x01
36
37/* This became a 16-bit register, and EN2 has disappeared */
38#define FWH_DEC_EN1 0xD8
39#define FWH_F8_EN 0x8000
40#define FWH_F0_EN 0x4000
41#define FWH_E8_EN 0x2000
42#define FWH_E0_EN 0x1000
43#define FWH_D8_EN 0x0800
44#define FWH_D0_EN 0x0400
45#define FWH_C8_EN 0x0200
46#define FWH_C0_EN 0x0100
47#define FWH_LEGACY_F_EN 0x0080
48#define FWH_LEGACY_E_EN 0x0040
49/* reserved 0x0020 and 0x0010 */
50#define FWH_70_EN 0x0008
51#define FWH_60_EN 0x0004
52#define FWH_50_EN 0x0002
53#define FWH_40_EN 0x0001
54
55/* these are 32-bit values */
56#define FWH_SEL1 0xD0
57#define FWH_SEL2 0xD4
58
59#define FWH_8MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \
60 FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN | \
61 FWH_70_EN | FWH_60_EN | FWH_50_EN | FWH_40_EN)
62
63#define FWH_7MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \
64 FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN | \
65 FWH_70_EN | FWH_60_EN | FWH_50_EN)
66
67#define FWH_6MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \
68 FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN | \
69 FWH_70_EN | FWH_60_EN)
70
71#define FWH_5MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \
72 FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN | \
73 FWH_70_EN)
74
75#define FWH_4MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \
76 FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN)
77
78#define FWH_3_5MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \
79 FWH_D8_EN | FWH_D0_EN | FWH_C8_EN)
80
81#define FWH_3MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \
82 FWH_D8_EN | FWH_D0_EN)
83
84#define FWH_2_5MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \
85 FWH_D8_EN)
86
87#define FWH_2MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN)
88
89#define FWH_1_5MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN)
90
91#define FWH_1MiB (FWH_F8_EN | FWH_F0_EN)
92
93#define FWH_0_5MiB (FWH_F8_EN)
94
95
96struct esb2rom_window {
97 void __iomem* virt;
98 unsigned long phys;
99 unsigned long size;
100 struct list_head maps;
101 struct resource rsrc;
102 struct pci_dev *pdev;
103};
104
105struct esb2rom_map_info {
106 struct list_head list;
107 struct map_info map;
108 struct mtd_info *mtd;
109 struct resource rsrc;
110 char map_name[sizeof(MOD_NAME) + 2 + ADDRESS_NAME_LEN];
111};
112
113static struct esb2rom_window esb2rom_window = {
114 .maps = LIST_HEAD_INIT(esb2rom_window.maps),
115};
116
117static void esb2rom_cleanup(struct esb2rom_window *window)
118{
119 struct esb2rom_map_info *map, *scratch;
120 u8 byte;
121
122 /* Disable writes through the rom window */
123 pci_read_config_byte(window->pdev, BIOS_CNTL, &byte);
124 pci_write_config_byte(window->pdev, BIOS_CNTL,
125 byte & ~BIOS_WRITE_ENABLE);
126
127 /* Free all of the mtd devices */
128 list_for_each_entry_safe(map, scratch, &window->maps, list) {
129 if (map->rsrc.parent)
130 release_resource(&map->rsrc);
131 del_mtd_device(map->mtd);
132 map_destroy(map->mtd);
133 list_del(&map->list);
134 kfree(map);
135 }
136 if (window->rsrc.parent)
137 release_resource(&window->rsrc);
138 if (window->virt) {
139 iounmap(window->virt);
140 window->virt = NULL;
141 window->phys = 0;
142 window->size = 0;
Lew Glendenning29175772006-10-20 14:41:04 -0700143 }
Alan Coxc7438d02006-10-20 14:41:06 -0700144 pci_dev_put(window->pdev);
Lew Glendenning29175772006-10-20 14:41:04 -0700145}
146
147static int __devinit esb2rom_init_one(struct pci_dev *pdev,
Cyrill Gorcunovdc164bb2007-03-06 02:39:45 -0800148 const struct pci_device_id *ent)
Lew Glendenning29175772006-10-20 14:41:04 -0700149{
150 static char *rom_probe_types[] = { "cfi_probe", "jedec_probe", NULL };
151 struct esb2rom_window *window = &esb2rom_window;
152 struct esb2rom_map_info *map = NULL;
153 unsigned long map_top;
154 u8 byte;
155 u16 word;
156
157 /* For now I just handle the ecb2 and I assume there
158 * are not a lot of resources up at the top of the address
159 * space. It is possible to handle other devices in the
160 * top 16MiB but it is very painful. Also since
161 * you can only really attach a FWH to an ICHX there
162 * a number of simplifications you can make.
163 *
164 * Also you can page firmware hubs if an 8MiB window isn't enough
165 * but don't currently handle that case either.
166 */
Alan Coxc7438d02006-10-20 14:41:06 -0700167 window->pdev = pci_dev_get(pdev);
Lew Glendenning29175772006-10-20 14:41:04 -0700168
169 /* RLG: experiment 2. Force the window registers to the widest values */
170
171/*
172 pci_read_config_word(pdev, FWH_DEC_EN1, &word);
173 printk(KERN_DEBUG "Original FWH_DEC_EN1 : %x\n", word);
174 pci_write_config_byte(pdev, FWH_DEC_EN1, 0xff);
175 pci_read_config_byte(pdev, FWH_DEC_EN1, &byte);
176 printk(KERN_DEBUG "New FWH_DEC_EN1 : %x\n", byte);
177
178 pci_read_config_byte(pdev, FWH_DEC_EN2, &byte);
179 printk(KERN_DEBUG "Original FWH_DEC_EN2 : %x\n", byte);
180 pci_write_config_byte(pdev, FWH_DEC_EN2, 0x0f);
181 pci_read_config_byte(pdev, FWH_DEC_EN2, &byte);
182 printk(KERN_DEBUG "New FWH_DEC_EN2 : %x\n", byte);
183*/
184
185 /* Find a region continuous to the end of the ROM window */
186 window->phys = 0;
187 pci_read_config_word(pdev, FWH_DEC_EN1, &word);
Cyrill Gorcunovdc164bb2007-03-06 02:39:45 -0800188 printk(KERN_DEBUG "pci_read_config_word : %x\n", word);
Lew Glendenning29175772006-10-20 14:41:04 -0700189
190 if ((word & FWH_8MiB) == FWH_8MiB)
191 window->phys = 0xff400000;
192 else if ((word & FWH_7MiB) == FWH_7MiB)
193 window->phys = 0xff500000;
194 else if ((word & FWH_6MiB) == FWH_6MiB)
195 window->phys = 0xff600000;
196 else if ((word & FWH_5MiB) == FWH_5MiB)
197 window->phys = 0xFF700000;
198 else if ((word & FWH_4MiB) == FWH_4MiB)
199 window->phys = 0xffc00000;
200 else if ((word & FWH_3_5MiB) == FWH_3_5MiB)
201 window->phys = 0xffc80000;
202 else if ((word & FWH_3MiB) == FWH_3MiB)
203 window->phys = 0xffd00000;
204 else if ((word & FWH_2_5MiB) == FWH_2_5MiB)
205 window->phys = 0xffd80000;
206 else if ((word & FWH_2MiB) == FWH_2MiB)
207 window->phys = 0xffe00000;
208 else if ((word & FWH_1_5MiB) == FWH_1_5MiB)
209 window->phys = 0xffe80000;
210 else if ((word & FWH_1MiB) == FWH_1MiB)
211 window->phys = 0xfff00000;
212 else if ((word & FWH_0_5MiB) == FWH_0_5MiB)
213 window->phys = 0xfff80000;
214
Cyrill Gorcunovdc164bb2007-03-06 02:39:45 -0800215 if (window->phys == 0) {
216 printk(KERN_ERR MOD_NAME ": Rom window is closed\n");
217 goto out;
218 }
219
Lew Glendenning29175772006-10-20 14:41:04 -0700220 /* reserved 0x0020 and 0x0010 */
221 window->phys -= 0x400000UL;
222 window->size = (0xffffffffUL - window->phys) + 1UL;
223
224 /* Enable writes through the rom window */
225 pci_read_config_byte(pdev, BIOS_CNTL, &byte);
226 if (!(byte & BIOS_WRITE_ENABLE) && (byte & (BIOS_LOCK_ENABLE))) {
227 /* The BIOS will generate an error if I enable
228 * this device, so don't even try.
229 */
230 printk(KERN_ERR MOD_NAME ": firmware access control, I can't enable writes\n");
231 goto out;
232 }
233 pci_write_config_byte(pdev, BIOS_CNTL, byte | BIOS_WRITE_ENABLE);
234
235 /*
236 * Try to reserve the window mem region. If this fails then
237 * it is likely due to the window being "reseved" by the BIOS.
238 */
239 window->rsrc.name = MOD_NAME;
240 window->rsrc.start = window->phys;
241 window->rsrc.end = window->phys + window->size - 1;
242 window->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
243 if (request_resource(&iomem_resource, &window->rsrc)) {
244 window->rsrc.parent = NULL;
245 printk(KERN_DEBUG MOD_NAME
246 ": %s(): Unable to register resource"
247 " 0x%.08llx-0x%.08llx - kernel bug?\n",
248 __func__,
249 (unsigned long long)window->rsrc.start,
250 (unsigned long long)window->rsrc.end);
251 }
252
253 /* Map the firmware hub into my address space. */
254 window->virt = ioremap_nocache(window->phys, window->size);
255 if (!window->virt) {
256 printk(KERN_ERR MOD_NAME ": ioremap(%08lx, %08lx) failed\n",
257 window->phys, window->size);
258 goto out;
259 }
260
261 /* Get the first address to look for an rom chip at */
262 map_top = window->phys;
263 if ((window->phys & 0x3fffff) != 0) {
264 /* if not aligned on 4MiB, look 4MiB lower in address space */
265 map_top = window->phys + 0x400000;
266 }
267#if 1
268 /* The probe sequence run over the firmware hub lock
269 * registers sets them to 0x7 (no access).
270 * (Insane hardware design, but most copied Intel's.)
271 * ==> Probe at most the last 4M of the address space.
272 */
273 if (map_top < 0xffc00000)
274 map_top = 0xffc00000;
275#endif
276 /* Loop through and look for rom chips */
277 while ((map_top - 1) < 0xffffffffUL) {
278 struct cfi_private *cfi;
279 unsigned long offset;
280 int i;
281
282 if (!map)
283 map = kmalloc(sizeof(*map), GFP_KERNEL);
284 if (!map) {
285 printk(KERN_ERR MOD_NAME ": kmalloc failed");
286 goto out;
287 }
288 memset(map, 0, sizeof(*map));
289 INIT_LIST_HEAD(&map->list);
290 map->map.name = map->map_name;
291 map->map.phys = map_top;
292 offset = map_top - window->phys;
293 map->map.virt = (void __iomem *)
294 (((unsigned long)(window->virt)) + offset);
295 map->map.size = 0xffffffffUL - map_top + 1UL;
296 /* Set the name of the map to the address I am trying */
Andrew Morton5ad0fdc2007-02-17 16:02:08 -0800297 sprintf(map->map_name, "%s @%08Lx",
298 MOD_NAME, (unsigned long long)map->map.phys);
Lew Glendenning29175772006-10-20 14:41:04 -0700299
300 /* Firmware hubs only use vpp when being programmed
301 * in a factory setting. So in-place programming
302 * needs to use a different method.
303 */
304 for(map->map.bankwidth = 32; map->map.bankwidth;
305 map->map.bankwidth >>= 1) {
306 char **probe_type;
307 /* Skip bankwidths that are not supported */
308 if (!map_bankwidth_supported(map->map.bankwidth))
309 continue;
310
311 /* Setup the map methods */
312 simple_map_init(&map->map);
313
314 /* Try all of the probe methods */
315 probe_type = rom_probe_types;
316 for(; *probe_type; probe_type++) {
317 map->mtd = do_map_probe(*probe_type, &map->map);
318 if (map->mtd)
319 goto found;
320 }
321 }
322 map_top += ROM_PROBE_STEP_SIZE;
323 continue;
324 found:
325 /* Trim the size if we are larger than the map */
326 if (map->mtd->size > map->map.size) {
327 printk(KERN_WARNING MOD_NAME
328 " rom(%u) larger than window(%lu). fixing...\n",
329 map->mtd->size, map->map.size);
330 map->mtd->size = map->map.size;
331 }
332 if (window->rsrc.parent) {
333 /*
334 * Registering the MTD device in iomem may not be possible
335 * if there is a BIOS "reserved" and BUSY range. If this
336 * fails then continue anyway.
337 */
338 map->rsrc.name = map->map_name;
339 map->rsrc.start = map->map.phys;
340 map->rsrc.end = map->map.phys + map->mtd->size - 1;
341 map->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
342 if (request_resource(&window->rsrc, &map->rsrc)) {
343 printk(KERN_ERR MOD_NAME
344 ": cannot reserve MTD resource\n");
345 map->rsrc.parent = NULL;
346 }
347 }
348
349 /* Make the whole region visible in the map */
350 map->map.virt = window->virt;
351 map->map.phys = window->phys;
352 cfi = map->map.fldrv_priv;
353 for(i = 0; i < cfi->numchips; i++)
354 cfi->chips[i].start += offset;
355
356 /* Now that the mtd devices is complete claim and export it */
357 map->mtd->owner = THIS_MODULE;
358 if (add_mtd_device(map->mtd)) {
359 map_destroy(map->mtd);
360 map->mtd = NULL;
361 goto out;
362 }
363
364 /* Calculate the new value of map_top */
365 map_top += map->mtd->size;
366
367 /* File away the map structure */
368 list_add(&map->list, &window->maps);
369 map = NULL;
370 }
371
372 out:
373 /* Free any left over map structures */
374 kfree(map);
375
376 /* See if I have any map structures */
377 if (list_empty(&window->maps)) {
378 esb2rom_cleanup(window);
379 return -ENODEV;
380 }
381 return 0;
382}
383
384static void __devexit esb2rom_remove_one (struct pci_dev *pdev)
385{
386 struct esb2rom_window *window = &esb2rom_window;
387 esb2rom_cleanup(window);
388}
389
390static struct pci_device_id esb2rom_pci_tbl[] __devinitdata = {
391 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0,
392 PCI_ANY_ID, PCI_ANY_ID, },
393 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
394 PCI_ANY_ID, PCI_ANY_ID, },
395 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
396 PCI_ANY_ID, PCI_ANY_ID, },
397 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
398 PCI_ANY_ID, PCI_ANY_ID, },
399 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1,
400 PCI_ANY_ID, PCI_ANY_ID, },
401 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
402 PCI_ANY_ID, PCI_ANY_ID, },
403 { 0, },
404};
405
406#if 0
407MODULE_DEVICE_TABLE(pci, esb2rom_pci_tbl);
408
409static struct pci_driver esb2rom_driver = {
410 .name = MOD_NAME,
411 .id_table = esb2rom_pci_tbl,
412 .probe = esb2rom_init_one,
413 .remove = esb2rom_remove_one,
414};
415#endif
416
417static int __init init_esb2rom(void)
418{
419 struct pci_dev *pdev;
420 struct pci_device_id *id;
421 int retVal;
422
423 pdev = NULL;
424 for (id = esb2rom_pci_tbl; id->vendor; id++) {
425 printk(KERN_DEBUG "device id = %x\n", id->device);
Alan Coxc7438d02006-10-20 14:41:06 -0700426 pdev = pci_get_device(id->vendor, id->device, NULL);
Lew Glendenning29175772006-10-20 14:41:04 -0700427 if (pdev) {
428 printk(KERN_DEBUG "matched device = %x\n", id->device);
429 break;
430 }
431 }
432 if (pdev) {
433 printk(KERN_DEBUG "matched device id %x\n", id->device);
434 retVal = esb2rom_init_one(pdev, &esb2rom_pci_tbl[0]);
Alan Coxc7438d02006-10-20 14:41:06 -0700435 pci_dev_put(pdev);
Lew Glendenning29175772006-10-20 14:41:04 -0700436 printk(KERN_DEBUG "retVal = %d\n", retVal);
437 return retVal;
438 }
439 return -ENXIO;
440#if 0
441 return pci_register_driver(&esb2rom_driver);
442#endif
443}
444
445static void __exit cleanup_esb2rom(void)
446{
447 esb2rom_remove_one(esb2rom_window.pdev);
448}
449
450module_init(init_esb2rom);
451module_exit(cleanup_esb2rom);
452
453MODULE_LICENSE("GPL");
454MODULE_AUTHOR("Lew Glendenning <lglendenning@lnxi.com>");
455MODULE_DESCRIPTION("MTD map driver for BIOS chips on the ESB2 southbridge");