Huang Zhenhua | cf36cc2 | 2017-11-28 18:29:37 +0800 | [diff] [blame] | 1 | /* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. |
Zhenhua Huang | 1e9cb66 | 2017-08-18 17:42:24 +0800 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
Can Guo | 4532cf6 | 2017-08-31 16:45:19 +0800 | [diff] [blame] | 12 | |
Huang Zhenhua | cf36cc2 | 2017-11-28 18:29:37 +0800 | [diff] [blame] | 13 | #include <dt-bindings/clock/qcom,gcc-sdm845.h> |
| 14 | #include <dt-bindings/clock/qcom,camcc-sdm845.h> |
| 15 | #include <dt-bindings/clock/qcom,dispcc-sdm845.h> |
| 16 | #include <dt-bindings/clock/qcom,rpmh.h> |
| 17 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 18 | |
Fenglin Wu | a3e0a6a | 2017-09-18 09:11:44 +0800 | [diff] [blame] | 19 | #include "sdm845-pmic-overlay.dtsi" |
| 20 | #include "sdm845-pinctrl-overlay.dtsi" |
Ashay Jaiswal | cc0c423 | 2018-05-21 15:37:53 +0530 | [diff] [blame] | 21 | |
| 22 | &qupv3_se10_i2c { |
Fenglin Wu | adc0a6e | 2017-09-26 09:05:06 +0800 | [diff] [blame] | 23 | #include "smb1355.dtsi" |
Ashay Jaiswal | cc0c423 | 2018-05-21 15:37:53 +0530 | [diff] [blame] | 24 | }; |
Fenglin Wu | a3e0a6a | 2017-09-18 09:11:44 +0800 | [diff] [blame] | 25 | |
Fenglin Wu | 7ba6590 | 2017-10-10 08:56:15 +0800 | [diff] [blame] | 26 | &vendor { |
xiaowang | febe997 | 2017-09-18 15:02:54 +0800 | [diff] [blame] | 27 | bluetooth: bt_wcn3990 { |
| 28 | compatible = "qca,wcn3990"; |
| 29 | qca,bt-vdd-io-supply = <&pm8998_s3>; |
| 30 | qca,bt-vdd-xtal-supply = <&pm8998_s5>; |
| 31 | qca,bt-vdd-core-supply = <&pm8998_l7>; |
| 32 | qca,bt-vdd-pa-supply = <&pm8998_l17>; |
| 33 | qca,bt-vdd-ldo-supply = <&pm8998_l25>; |
| 34 | |
| 35 | qca,bt-vdd-io-voltage-level = <1352000 1352000>; |
| 36 | qca,bt-vdd-xtal-voltage-level = <2040000 2040000>; |
| 37 | qca,bt-vdd-core-voltage-level = <1800000 1800000>; |
| 38 | qca,bt-vdd-pa-voltage-level = <1304000 1304000>; |
| 39 | qca,bt-vdd-ldo-voltage-level = <3312000 3312000>; |
| 40 | |
| 41 | qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */ |
| 42 | qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */ |
| 43 | qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ |
| 44 | qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ |
| 45 | qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */ |
| 46 | }; |
| 47 | |
Fenglin Wu | 7ba6590 | 2017-10-10 08:56:15 +0800 | [diff] [blame] | 48 | qvr_batterydata: qcom,battery-data { |
| 49 | qcom,batt-id-range-pct = <15>; |
| 50 | #include "fg-gen3-batterydata-mlp446579-3800mah.dtsi" |
| 51 | }; |
| 52 | }; |
| 53 | |
Fenglin Wu | a3e0a6a | 2017-09-18 09:11:44 +0800 | [diff] [blame] | 54 | &pmi8998_pdphy { |
| 55 | vbus-supply = <&smb2_vbus>; |
| 56 | }; |
| 57 | |
zhenchao | 491be46 | 2017-09-18 19:04:54 +0800 | [diff] [blame] | 58 | &qupv3_se6_4uart { |
| 59 | status = "ok"; |
| 60 | }; |
| 61 | |
Fenglin Wu | adc0a6e | 2017-09-26 09:05:06 +0800 | [diff] [blame] | 62 | &pmi8998_fg { |
Fenglin Wu | 7ba6590 | 2017-10-10 08:56:15 +0800 | [diff] [blame] | 63 | qcom,battery-data = <&qvr_batterydata>; |
Fenglin Wu | adc0a6e | 2017-09-26 09:05:06 +0800 | [diff] [blame] | 64 | qcom,fg-bmd-en-delay-ms = <300>; |
| 65 | }; |
| 66 | |
Fenglin Wu | b58217a | 2017-11-09 09:38:31 +0800 | [diff] [blame] | 67 | &pmi8998_charger { |
| 68 | qcom,battery-data = <&qvr_batterydata>; |
| 69 | qcom,sw-jeita-enable; |
| 70 | }; |
| 71 | |
Rohit Rangwani | fb28786 | 2017-10-26 12:09:10 +0530 | [diff] [blame] | 72 | &qupv3_se3_i2c { |
| 73 | status = "ok"; |
| 74 | nq@28 { |
| 75 | compatible = "qcom,nq-nci"; |
| 76 | reg = <0x28>; |
| 77 | qcom,nq-irq = <&tlmm 63 0x00>; |
| 78 | qcom,nq-ven = <&tlmm 12 0x00>; |
| 79 | qcom,nq-firm = <&tlmm 62 0x00>; |
| 80 | qcom,nq-clkreq = <&pm8998_gpios 21 0x00>; |
| 81 | qcom,nq-esepwr = <&tlmm 116 0x00>; |
| 82 | interrupt-parent = <&tlmm>; |
| 83 | qcom,clk-src = "BBCLK3"; |
| 84 | interrupts = <63 0>; |
| 85 | interrupt-names = "nfc_irq"; |
| 86 | pinctrl-names = "nfc_active", "nfc_suspend"; |
| 87 | pinctrl-0 = <&nfc_int_active |
| 88 | &nfc_enable_active |
| 89 | &nfc_clk_default>; |
| 90 | pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; |
| 91 | clocks = <&clock_rpmh RPMH_LN_BB_CLK3>; |
| 92 | clock-names = "ref_clk"; |
| 93 | }; |
| 94 | }; |
| 95 | |
Fenglin Wu | adc0a6e | 2017-09-26 09:05:06 +0800 | [diff] [blame] | 96 | &qupv3_se10_i2c { |
| 97 | status = "ok"; |
| 98 | }; |
| 99 | |
| 100 | &smb1355_charger_0 { |
| 101 | status = "ok"; |
| 102 | }; |
| 103 | |
| 104 | &smb1355_charger_1 { |
| 105 | status = "ok"; |
| 106 | }; |
| 107 | |
| 108 | &soc { |
| 109 | qcom,qbt1000 { |
| 110 | status = "disabled"; |
| 111 | }; |
| 112 | |
| 113 | gpio_keys { |
| 114 | compatible = "gpio-keys"; |
| 115 | label = "gpio-keys"; |
| 116 | pinctrl-names = "default"; |
| 117 | pinctrl-0 = <&key_vol_up_default |
| 118 | &key_home_default>; |
| 119 | |
| 120 | vol_up { |
| 121 | label = "volume_up"; |
| 122 | gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; |
| 123 | linux,input-type = <1>; |
| 124 | linux,code = <115>; |
| 125 | gpio-key,wakeup; |
| 126 | debounce-interval = <15>; |
| 127 | linux,can-disable; |
| 128 | }; |
| 129 | |
| 130 | home { |
| 131 | label = "home"; |
| 132 | gpios = <&pm8998_gpios 5 GPIO_ACTIVE_LOW>; |
| 133 | linux,input-type = <1>; |
| 134 | linux,code = <102>; |
| 135 | gpio-key,wakeup; |
| 136 | debounce-interval = <15>; |
| 137 | linux,can-disable; |
| 138 | }; |
| 139 | }; |
| 140 | }; |
| 141 | |
Liangliang Lu | 27d58e1 | 2018-01-04 18:26:45 +0800 | [diff] [blame] | 142 | &qusb_phy0 { |
| 143 | qcom,qusb-phy-init-seq = |
| 144 | /* <value reg_offset> */ |
| 145 | <0x23 0x210 /* PWR_CTRL1 */ |
| 146 | 0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */ |
| 147 | 0x7c 0x18c /* PLL_CLOCK_INVERTERS */ |
| 148 | 0x80 0x2c /* PLL_CMODE */ |
| 149 | 0x0a 0x184 /* PLL_LOCK_DELAY */ |
| 150 | 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */ |
| 151 | 0x40 0x194 /* PLL_BIAS_CONTROL_1 */ |
| 152 | 0x20 0x198 /* PLL_BIAS_CONTROL_2 */ |
| 153 | 0x21 0x214 /* PWR_CTRL2 */ |
| 154 | 0x00 0x220 /* IMP_CTRL1 */ |
| 155 | 0x58 0x224 /* IMP_CTRL2 */ |
| 156 | 0x27 0x240 /* TUNE1 */ |
| 157 | 0x29 0x244 /* TUNE2 */ |
| 158 | 0xca 0x248 /* TUNE3 */ |
| 159 | 0x04 0x24c /* TUNE4 */ |
| 160 | 0x03 0x250 /* TUNE5 */ |
| 161 | 0x00 0x23c /* CHG_CTRL2 */ |
| 162 | 0x22 0x210>; /* PWR_CTRL1 */ |
| 163 | }; |
| 164 | |
Fenglin Wu | adc0a6e | 2017-09-26 09:05:06 +0800 | [diff] [blame] | 165 | &pmi8998_haptics { |
| 166 | qcom,vmax-mv = <1800>; |
| 167 | qcom,wave-play-rate-us = <4255>; |
| 168 | qcom,lra-auto-mode; |
| 169 | status = "okay"; |
| 170 | }; |
| 171 | |
Zhenhua Huang | 7bf9d14 | 2017-09-07 14:08:13 +0800 | [diff] [blame] | 172 | &qupv3_se9_2uart { |
| 173 | status = "ok"; |
| 174 | }; |
| 175 | |
Can Guo | 4532cf6 | 2017-08-31 16:45:19 +0800 | [diff] [blame] | 176 | &ufsphy_mem { |
| 177 | compatible = "qcom,ufs-phy-qmp-v3"; |
| 178 | |
| 179 | vdda-phy-supply = <&pm8998_l1>; /* 0.88v */ |
| 180 | vdda-pll-supply = <&pm8998_l26>; /* 1.2v */ |
| 181 | vdda-phy-max-microamp = <62900>; |
| 182 | vdda-pll-max-microamp = <18300>; |
| 183 | |
| 184 | status = "ok"; |
| 185 | }; |
| 186 | |
| 187 | &ufshc_mem { |
| 188 | vdd-hba-supply = <&ufs_phy_gdsc>; |
| 189 | vdd-hba-fixed-regulator; |
| 190 | vcc-supply = <&pm8998_l20>; |
Can Guo | 09c060c | 2017-12-21 18:10:10 +0800 | [diff] [blame] | 191 | vcc-voltage-level = <2950000 2960000>; |
Can Guo | 4532cf6 | 2017-08-31 16:45:19 +0800 | [diff] [blame] | 192 | vccq2-supply = <&pm8998_s4>; |
| 193 | vcc-max-microamp = <600000>; |
| 194 | vccq2-max-microamp = <600000>; |
| 195 | |
| 196 | qcom,vddp-ref-clk-supply = <&pm8998_l2>; |
| 197 | qcom,vddp-ref-clk-max-microamp = <100>; |
| 198 | |
| 199 | status = "ok"; |
| 200 | }; |
Can Guo | 52d0484 | 2017-09-28 09:38:22 +0800 | [diff] [blame] | 201 | |
| 202 | &sdhc_2 { |
| 203 | vdd-supply = <&pm8998_l21>; |
| 204 | qcom,vdd-voltage-level = <2950000 2960000>; |
| 205 | qcom,vdd-current-level = <200 800000>; |
| 206 | |
| 207 | vdd-io-supply = <&pm8998_l13>; |
| 208 | qcom,vdd-io-voltage-level = <1808000 2960000>; |
| 209 | qcom,vdd-io-current-level = <200 22000>; |
| 210 | |
| 211 | pinctrl-names = "active", "sleep"; |
Can Guo | fb1fe7a | 2018-01-03 13:10:53 +0800 | [diff] [blame] | 212 | pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &storage_cd>; |
| 213 | pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &storage_cd>; |
Can Guo | 52d0484 | 2017-09-28 09:38:22 +0800 | [diff] [blame] | 214 | |
| 215 | cd-gpios = <&tlmm 126 GPIO_ACTIVE_HIGH>; |
| 216 | |
| 217 | status = "ok"; |
| 218 | }; |
Hamad Kadmany | c364419 | 2017-11-02 18:59:55 +0200 | [diff] [blame] | 219 | |
| 220 | &wil6210 { |
| 221 | status = "ok"; |
| 222 | }; |
Jin Fu | 9e861b9 | 2018-01-17 17:37:32 +0800 | [diff] [blame] | 223 | |
| 224 | &qupv3_se5_i2c { |
| 225 | status = "ok"; |
| 226 | synaptics_dsx@20 { |
| 227 | compatible = "synaptics,dsx-i2c"; |
| 228 | reg = <0x20>; |
| 229 | interrupt-parent = <&tlmm>; |
| 230 | interrupts = <122 0x2008>; |
| 231 | vdd-supply = <&pm8998_l14>; |
| 232 | avdd-supply = <&pm8998_l28>; |
| 233 | pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", |
| 234 | "pmx_ts_release"; |
| 235 | pinctrl-0 = <&ts_int_active &ts_reset_active>; |
| 236 | pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; |
| 237 | pinctrl-2 = <&ts_release>; |
| 238 | synaptics,pwr-reg-name = "avdd"; |
| 239 | synaptics,bus-reg-name = "vdd"; |
| 240 | synaptics,ub-i2c-addr = <0x2c>; |
| 241 | synaptics,irq-gpio = <&tlmm 122 0x2008>; |
| 242 | synaptics,reset-gpio = <&tlmm 99 0x0>; |
| 243 | synaptics,irq-on-state = <0>; |
| 244 | synaptics,power-delay-ms = <200>; |
| 245 | synaptics,reset-delay-ms = <200>; |
| 246 | synaptics,reset-on-state = <0>; |
| 247 | synaptics,reset-active-ms = <20>; |
| 248 | }; |
| 249 | }; |