Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 1 | /* |
| 2 | comedi/drivers/ni_at_a2150.c |
| 3 | Driver for National Instruments AT-A2150 boards |
| 4 | Copyright (C) 2001, 2002 Frank Mori Hess <fmhess@users.sourceforge.net> |
| 5 | |
| 6 | COMEDI - Linux Control and Measurement Device Interface |
| 7 | Copyright (C) 2000 David A. Schleef <ds@schleef.org> |
| 8 | |
| 9 | This program is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 2 of the License, or |
| 12 | (at your option) any later version. |
| 13 | |
| 14 | This program is distributed in the hope that it will be useful, |
| 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | GNU General Public License for more details. |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 18 | */ |
| 19 | /* |
| 20 | Driver: ni_at_a2150 |
| 21 | Description: National Instruments AT-A2150 |
| 22 | Author: Frank Mori Hess |
| 23 | Status: works |
| 24 | Devices: [National Instruments] AT-A2150C (at_a2150c), AT-2150S (at_a2150s) |
| 25 | |
| 26 | If you want to ac couple the board's inputs, use AREF_OTHER. |
| 27 | |
| 28 | Configuration options: |
| 29 | [0] - I/O port base address |
| 30 | [1] - IRQ (optional, required for timed conversions) |
| 31 | [2] - DMA (optional, required for timed conversions) |
| 32 | |
| 33 | */ |
| 34 | /* |
| 35 | Yet another driver for obsolete hardware brought to you by Frank Hess. |
| 36 | Testing and debugging help provided by Dave Andruczyk. |
| 37 | |
| 38 | This driver supports the boards: |
| 39 | |
| 40 | AT-A2150C |
| 41 | AT-A2150S |
| 42 | |
| 43 | The only difference is their master clock frequencies. |
| 44 | |
| 45 | Options: |
| 46 | [0] - base io address |
| 47 | [1] - irq |
| 48 | [2] - dma channel |
| 49 | |
| 50 | References (from ftp://ftp.natinst.com/support/manuals): |
| 51 | |
| 52 | 320360.pdf AT-A2150 User Manual |
| 53 | |
| 54 | TODO: |
| 55 | |
| 56 | analog level triggering |
| 57 | TRIG_WAKE_EOS |
| 58 | |
| 59 | */ |
| 60 | |
H Hartley Sweeten | ce157f8 | 2013-06-24 17:04:43 -0700 | [diff] [blame] | 61 | #include <linux/module.h> |
| 62 | #include <linux/delay.h> |
Greg Kroah-Hartman | 25436dc | 2009-04-27 15:14:34 -0700 | [diff] [blame] | 63 | #include <linux/interrupt.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 64 | #include <linux/slab.h> |
Greg Kroah-Hartman | 845d131 | 2011-06-09 12:20:28 -0700 | [diff] [blame] | 65 | #include <linux/io.h> |
H Hartley Sweeten | ce157f8 | 2013-06-24 17:04:43 -0700 | [diff] [blame] | 66 | |
H Hartley Sweeten | 1a97f14 | 2015-01-14 10:05:09 -0700 | [diff] [blame] | 67 | #include "../comedidev.h" |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 68 | |
H Hartley Sweeten | 1a97f14 | 2015-01-14 10:05:09 -0700 | [diff] [blame] | 69 | #include "comedi_isadma.h" |
H Hartley Sweeten | e875132 | 2015-02-23 14:57:44 -0700 | [diff] [blame] | 70 | #include "comedi_8254.h" |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 71 | |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 72 | #define A2150_DMA_BUFFER_SIZE 0xff00 /* size in bytes of dma buffer */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 73 | |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 74 | /* Registers and bits */ |
| 75 | #define CONFIG_REG 0x0 |
| 76 | #define CHANNEL_BITS(x) ((x) & 0x7) |
| 77 | #define CHANNEL_MASK 0x7 |
| 78 | #define CLOCK_SELECT_BITS(x) (((x) & 0x3) << 3) |
| 79 | #define CLOCK_DIVISOR_BITS(x) (((x) & 0x3) << 5) |
| 80 | #define CLOCK_MASK (0xf << 3) |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 81 | #define ENABLE0_BIT 0x80 /* enable (don't internally ground) channels 0 and 1 */ |
| 82 | #define ENABLE1_BIT 0x100 /* enable (don't internally ground) channels 2 and 3 */ |
| 83 | #define AC0_BIT 0x200 /* ac couple channels 0,1 */ |
| 84 | #define AC1_BIT 0x400 /* ac couple channels 2,3 */ |
| 85 | #define APD_BIT 0x800 /* analog power down */ |
| 86 | #define DPD_BIT 0x1000 /* digital power down */ |
| 87 | #define TRIGGER_REG 0x2 /* trigger config register */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 88 | #define POST_TRIGGER_BITS 0x2 |
| 89 | #define DELAY_TRIGGER_BITS 0x3 |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 90 | #define HW_TRIG_EN 0x10 /* enable hardware trigger */ |
| 91 | #define FIFO_START_REG 0x6 /* software start aquistion trigger */ |
| 92 | #define FIFO_RESET_REG 0x8 /* clears fifo + fifo flags */ |
| 93 | #define FIFO_DATA_REG 0xa /* read data */ |
| 94 | #define DMA_TC_CLEAR_REG 0xe /* clear dma terminal count interrupt */ |
| 95 | #define STATUS_REG 0x12 /* read only */ |
| 96 | #define FNE_BIT 0x1 /* fifo not empty */ |
| 97 | #define OVFL_BIT 0x8 /* fifo overflow */ |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 98 | #define EDAQ_BIT 0x10 /* end of acquisition interrupt */ |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 99 | #define DCAL_BIT 0x20 /* offset calibration in progress */ |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 100 | #define INTR_BIT 0x40 /* interrupt has occurred */ |
| 101 | #define DMA_TC_BIT 0x80 /* dma terminal count interrupt has occurred */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 102 | #define ID_BITS(x) (((x) >> 8) & 0x3) |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 103 | #define IRQ_DMA_CNTRL_REG 0x12 /* write only */ |
| 104 | #define DMA_CHAN_BITS(x) ((x) & 0x7) /* sets dma channel */ |
| 105 | #define DMA_EN_BIT 0x8 /* enables dma */ |
| 106 | #define IRQ_LVL_BITS(x) (((x) & 0xf) << 4) /* sets irq level */ |
| 107 | #define FIFO_INTR_EN_BIT 0x100 /* enable fifo interrupts */ |
| 108 | #define FIFO_INTR_FHF_BIT 0x200 /* interrupt fifo half full */ |
Joglekar Tejas | 51bb618 | 2015-06-01 09:44:51 +0530 | [diff] [blame] | 109 | #define DMA_INTR_EN_BIT 0x800 /* enable interrupt on dma terminal count */ |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 110 | #define DMA_DEM_EN_BIT 0x1000 /* enables demand mode dma */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 111 | #define I8253_BASE_REG 0x14 |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 112 | |
Bill Pemberton | 92b635c | 2009-03-19 17:59:18 -0400 | [diff] [blame] | 113 | struct a2150_board { |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 114 | const char *name; |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 115 | int clock[4]; /* master clock periods, in nanoseconds */ |
| 116 | int num_clocks; /* number of available master clock speeds */ |
| 117 | int ai_speed; /* maximum conversion rate in nanoseconds */ |
Bill Pemberton | 92b635c | 2009-03-19 17:59:18 -0400 | [diff] [blame] | 118 | }; |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 119 | |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 120 | /* analog input range */ |
Bill Pemberton | 9ced1de | 2009-03-16 22:05:31 -0400 | [diff] [blame] | 121 | static const struct comedi_lrange range_a2150 = { |
H Hartley Sweeten | 168a210 | 2013-12-09 17:31:24 -0700 | [diff] [blame] | 122 | 1, { |
| 123 | BIP_RANGE(2.828) |
| 124 | } |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 125 | }; |
| 126 | |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 127 | /* enum must match board indices */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 128 | enum { a2150_c, a2150_s }; |
Bill Pemberton | 92b635c | 2009-03-19 17:59:18 -0400 | [diff] [blame] | 129 | static const struct a2150_board a2150_boards[] = { |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 130 | { |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 131 | .name = "at-a2150c", |
| 132 | .clock = {31250, 22676, 20833, 19531}, |
| 133 | .num_clocks = 4, |
| 134 | .ai_speed = 19531, |
| 135 | }, |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 136 | { |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 137 | .name = "at-a2150s", |
| 138 | .clock = {62500, 50000, 41667, 0}, |
| 139 | .num_clocks = 3, |
| 140 | .ai_speed = 41667, |
| 141 | }, |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 142 | }; |
| 143 | |
Bill Pemberton | 3cc3872 | 2009-03-16 22:16:07 -0400 | [diff] [blame] | 144 | struct a2150_private { |
H Hartley Sweeten | 1a97f14 | 2015-01-14 10:05:09 -0700 | [diff] [blame] | 145 | struct comedi_isadma *dma; |
H Hartley Sweeten | 4547854 | 2015-01-12 10:55:46 -0700 | [diff] [blame] | 146 | unsigned int count; /* number of data points left to be taken */ |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 147 | int irq_dma_bits; /* irq/dma register bits */ |
| 148 | int config_bits; /* config register bits */ |
Bill Pemberton | 3cc3872 | 2009-03-16 22:16:07 -0400 | [diff] [blame] | 149 | }; |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 150 | |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 151 | /* interrupt service routine */ |
Jiri Slaby | 70265d2 | 2009-03-26 09:34:06 +0100 | [diff] [blame] | 152 | static irqreturn_t a2150_interrupt(int irq, void *d) |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 153 | { |
Bill Pemberton | 71b5f4f | 2009-03-16 22:05:08 -0400 | [diff] [blame] | 154 | struct comedi_device *dev = d; |
H Hartley Sweeten | 9a1a6cf | 2012-10-15 10:15:52 -0700 | [diff] [blame] | 155 | struct a2150_private *devpriv = dev->private; |
H Hartley Sweeten | 1a97f14 | 2015-01-14 10:05:09 -0700 | [diff] [blame] | 156 | struct comedi_isadma *dma = devpriv->dma; |
| 157 | struct comedi_isadma_desc *desc = &dma->desc[0]; |
Bill Pemberton | 34c4392 | 2009-03-16 22:05:14 -0400 | [diff] [blame] | 158 | struct comedi_subdevice *s = dev->read_subdev; |
H Hartley Sweeten | 1a97f14 | 2015-01-14 10:05:09 -0700 | [diff] [blame] | 159 | struct comedi_async *async = s->async; |
| 160 | struct comedi_cmd *cmd = &async->cmd; |
| 161 | unsigned short *buf = desc->virt_addr; |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 162 | unsigned int max_points, num_points, residue, leftover; |
Ian Abbott | 2fb5cd3 | 2013-10-16 14:40:24 +0100 | [diff] [blame] | 163 | unsigned short dpnt; |
H Hartley Sweeten | 1a97f14 | 2015-01-14 10:05:09 -0700 | [diff] [blame] | 164 | int status; |
| 165 | int i; |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 166 | |
H Hartley Sweeten | 1a97f14 | 2015-01-14 10:05:09 -0700 | [diff] [blame] | 167 | if (!dev->attached) |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 168 | return IRQ_HANDLED; |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 169 | |
| 170 | status = inw(dev->iobase + STATUS_REG); |
H Hartley Sweeten | 1a97f14 | 2015-01-14 10:05:09 -0700 | [diff] [blame] | 171 | if ((status & INTR_BIT) == 0) |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 172 | return IRQ_NONE; |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 173 | |
| 174 | if (status & OVFL_BIT) { |
H Hartley Sweeten | 3e6cb74 | 2015-01-20 12:06:02 -0700 | [diff] [blame] | 175 | async->events |= COMEDI_CB_ERROR; |
H Hartley Sweeten | 4a706e2 | 2014-09-18 11:11:28 -0700 | [diff] [blame] | 176 | comedi_handle_events(dev, s); |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 177 | } |
| 178 | |
| 179 | if ((status & DMA_TC_BIT) == 0) { |
H Hartley Sweeten | 3e6cb74 | 2015-01-20 12:06:02 -0700 | [diff] [blame] | 180 | async->events |= COMEDI_CB_ERROR; |
H Hartley Sweeten | 4a706e2 | 2014-09-18 11:11:28 -0700 | [diff] [blame] | 181 | comedi_handle_events(dev, s); |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 182 | return IRQ_HANDLED; |
| 183 | } |
| 184 | |
H Hartley Sweeten | 10f3a2d | 2015-01-13 10:16:36 -0700 | [diff] [blame] | 185 | /* |
| 186 | * residue is the number of bytes left to be done on the dma |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 187 | * transfer. It should always be zero at this point unless |
| 188 | * the stop_src is set to external triggering. |
| 189 | */ |
H Hartley Sweeten | 1a97f14 | 2015-01-14 10:05:09 -0700 | [diff] [blame] | 190 | residue = comedi_isadma_disable(desc->chan); |
H Hartley Sweeten | 10f3a2d | 2015-01-13 10:16:36 -0700 | [diff] [blame] | 191 | |
| 192 | /* figure out how many points to read */ |
H Hartley Sweeten | 1a97f14 | 2015-01-14 10:05:09 -0700 | [diff] [blame] | 193 | max_points = comedi_bytes_to_samples(s, desc->size); |
H Hartley Sweeten | 10f3a2d | 2015-01-13 10:16:36 -0700 | [diff] [blame] | 194 | num_points = max_points - comedi_bytes_to_samples(s, residue); |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 195 | if (devpriv->count < num_points && cmd->stop_src == TRIG_COUNT) |
| 196 | num_points = devpriv->count; |
| 197 | |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 198 | /* figure out how many points will be stored next time */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 199 | leftover = 0; |
| 200 | if (cmd->stop_src == TRIG_NONE) { |
H Hartley Sweeten | 1a97f14 | 2015-01-14 10:05:09 -0700 | [diff] [blame] | 201 | leftover = comedi_bytes_to_samples(s, desc->size); |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 202 | } else if (devpriv->count > max_points) { |
| 203 | leftover = devpriv->count - max_points; |
| 204 | if (leftover > max_points) |
| 205 | leftover = max_points; |
| 206 | } |
| 207 | /* there should only be a residue if collection was stopped by having |
| 208 | * the stop_src set to an external trigger, in which case there |
| 209 | * will be no more data |
| 210 | */ |
| 211 | if (residue) |
| 212 | leftover = 0; |
| 213 | |
| 214 | for (i = 0; i < num_points; i++) { |
| 215 | /* write data point to comedi buffer */ |
H Hartley Sweeten | 6d26275 | 2015-01-12 10:55:51 -0700 | [diff] [blame] | 216 | dpnt = buf[i]; |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 217 | /* convert from 2's complement to unsigned coding */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 218 | dpnt ^= 0x8000; |
H Hartley Sweeten | 7138e89 | 2014-10-22 15:36:28 -0700 | [diff] [blame] | 219 | comedi_buf_write_samples(s, &dpnt, 1); |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 220 | if (cmd->stop_src == TRIG_COUNT) { |
| 221 | if (--devpriv->count == 0) { /* end of acquisition */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 222 | async->events |= COMEDI_CB_EOA; |
| 223 | break; |
| 224 | } |
| 225 | } |
| 226 | } |
H Hartley Sweeten | c92b0b2 | 2015-01-13 10:16:35 -0700 | [diff] [blame] | 227 | /* re-enable dma */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 228 | if (leftover) { |
H Hartley Sweeten | 1a97f14 | 2015-01-14 10:05:09 -0700 | [diff] [blame] | 229 | desc->size = comedi_samples_to_bytes(s, leftover); |
| 230 | comedi_isadma_program(desc); |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 231 | } |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 232 | |
H Hartley Sweeten | 4a706e2 | 2014-09-18 11:11:28 -0700 | [diff] [blame] | 233 | comedi_handle_events(dev, s); |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 234 | |
| 235 | /* clear interrupt */ |
| 236 | outw(0x00, dev->iobase + DMA_TC_CLEAR_REG); |
| 237 | |
| 238 | return IRQ_HANDLED; |
| 239 | } |
| 240 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 241 | static int a2150_cancel(struct comedi_device *dev, struct comedi_subdevice *s) |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 242 | { |
H Hartley Sweeten | 9a1a6cf | 2012-10-15 10:15:52 -0700 | [diff] [blame] | 243 | struct a2150_private *devpriv = dev->private; |
H Hartley Sweeten | 1a97f14 | 2015-01-14 10:05:09 -0700 | [diff] [blame] | 244 | struct comedi_isadma *dma = devpriv->dma; |
| 245 | struct comedi_isadma_desc *desc = &dma->desc[0]; |
H Hartley Sweeten | 9a1a6cf | 2012-10-15 10:15:52 -0700 | [diff] [blame] | 246 | |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 247 | /* disable dma on card */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 248 | devpriv->irq_dma_bits &= ~DMA_INTR_EN_BIT & ~DMA_EN_BIT; |
| 249 | outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG); |
| 250 | |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 251 | /* disable computer's dma */ |
H Hartley Sweeten | 1a97f14 | 2015-01-14 10:05:09 -0700 | [diff] [blame] | 252 | comedi_isadma_disable(desc->chan); |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 253 | |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 254 | /* clear fifo and reset triggering circuitry */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 255 | outw(0, dev->iobase + FIFO_RESET_REG); |
| 256 | |
| 257 | return 0; |
| 258 | } |
| 259 | |
H Hartley Sweeten | c9bef03 | 2014-07-18 17:01:17 -0700 | [diff] [blame] | 260 | /* |
| 261 | * sets bits in devpriv->clock_bits to nearest approximation of requested |
| 262 | * period, adjusts requested period to actual timing. |
| 263 | */ |
| 264 | static int a2150_get_timing(struct comedi_device *dev, unsigned int *period, |
| 265 | unsigned int flags) |
| 266 | { |
H Hartley Sweeten | 94be3ef | 2015-06-18 10:54:44 -0700 | [diff] [blame] | 267 | const struct a2150_board *board = dev->board_ptr; |
H Hartley Sweeten | c9bef03 | 2014-07-18 17:01:17 -0700 | [diff] [blame] | 268 | struct a2150_private *devpriv = dev->private; |
| 269 | int lub, glb, temp; |
| 270 | int lub_divisor_shift, lub_index, glb_divisor_shift, glb_index; |
| 271 | int i, j; |
| 272 | |
| 273 | /* initialize greatest lower and least upper bounds */ |
| 274 | lub_divisor_shift = 3; |
| 275 | lub_index = 0; |
H Hartley Sweeten | 94be3ef | 2015-06-18 10:54:44 -0700 | [diff] [blame] | 276 | lub = board->clock[lub_index] * (1 << lub_divisor_shift); |
H Hartley Sweeten | c9bef03 | 2014-07-18 17:01:17 -0700 | [diff] [blame] | 277 | glb_divisor_shift = 0; |
H Hartley Sweeten | 94be3ef | 2015-06-18 10:54:44 -0700 | [diff] [blame] | 278 | glb_index = board->num_clocks - 1; |
| 279 | glb = board->clock[glb_index] * (1 << glb_divisor_shift); |
H Hartley Sweeten | c9bef03 | 2014-07-18 17:01:17 -0700 | [diff] [blame] | 280 | |
| 281 | /* make sure period is in available range */ |
| 282 | if (*period < glb) |
| 283 | *period = glb; |
| 284 | if (*period > lub) |
| 285 | *period = lub; |
| 286 | |
| 287 | /* we can multiply period by 1, 2, 4, or 8, using (1 << i) */ |
| 288 | for (i = 0; i < 4; i++) { |
| 289 | /* there are a maximum of 4 master clocks */ |
H Hartley Sweeten | 94be3ef | 2015-06-18 10:54:44 -0700 | [diff] [blame] | 290 | for (j = 0; j < board->num_clocks; j++) { |
H Hartley Sweeten | c9bef03 | 2014-07-18 17:01:17 -0700 | [diff] [blame] | 291 | /* temp is the period in nanosec we are evaluating */ |
H Hartley Sweeten | 94be3ef | 2015-06-18 10:54:44 -0700 | [diff] [blame] | 292 | temp = board->clock[j] * (1 << i); |
H Hartley Sweeten | c9bef03 | 2014-07-18 17:01:17 -0700 | [diff] [blame] | 293 | /* if it is the best match yet */ |
| 294 | if (temp < lub && temp >= *period) { |
| 295 | lub_divisor_shift = i; |
| 296 | lub_index = j; |
| 297 | lub = temp; |
| 298 | } |
| 299 | if (temp > glb && temp <= *period) { |
| 300 | glb_divisor_shift = i; |
| 301 | glb_index = j; |
| 302 | glb = temp; |
| 303 | } |
| 304 | } |
| 305 | } |
Ian Abbott | b544bd6 | 2014-09-03 13:45:55 +0100 | [diff] [blame] | 306 | switch (flags & CMDF_ROUND_MASK) { |
| 307 | case CMDF_ROUND_NEAREST: |
H Hartley Sweeten | c9bef03 | 2014-07-18 17:01:17 -0700 | [diff] [blame] | 308 | default: |
| 309 | /* if least upper bound is better approximation */ |
| 310 | if (lub - *period < *period - glb) |
| 311 | *period = lub; |
| 312 | else |
| 313 | *period = glb; |
| 314 | break; |
Ian Abbott | b544bd6 | 2014-09-03 13:45:55 +0100 | [diff] [blame] | 315 | case CMDF_ROUND_UP: |
H Hartley Sweeten | c9bef03 | 2014-07-18 17:01:17 -0700 | [diff] [blame] | 316 | *period = lub; |
| 317 | break; |
Ian Abbott | b544bd6 | 2014-09-03 13:45:55 +0100 | [diff] [blame] | 318 | case CMDF_ROUND_DOWN: |
H Hartley Sweeten | c9bef03 | 2014-07-18 17:01:17 -0700 | [diff] [blame] | 319 | *period = glb; |
| 320 | break; |
| 321 | } |
| 322 | |
| 323 | /* set clock bits for config register appropriately */ |
| 324 | devpriv->config_bits &= ~CLOCK_MASK; |
| 325 | if (*period == lub) { |
| 326 | devpriv->config_bits |= |
| 327 | CLOCK_SELECT_BITS(lub_index) | |
| 328 | CLOCK_DIVISOR_BITS(lub_divisor_shift); |
| 329 | } else { |
| 330 | devpriv->config_bits |= |
| 331 | CLOCK_SELECT_BITS(glb_index) | |
| 332 | CLOCK_DIVISOR_BITS(glb_divisor_shift); |
| 333 | } |
| 334 | |
| 335 | return 0; |
| 336 | } |
| 337 | |
| 338 | static int a2150_set_chanlist(struct comedi_device *dev, |
| 339 | unsigned int start_channel, |
| 340 | unsigned int num_channels) |
| 341 | { |
| 342 | struct a2150_private *devpriv = dev->private; |
| 343 | |
| 344 | if (start_channel + num_channels > 4) |
| 345 | return -1; |
| 346 | |
| 347 | devpriv->config_bits &= ~CHANNEL_MASK; |
| 348 | |
| 349 | switch (num_channels) { |
| 350 | case 1: |
| 351 | devpriv->config_bits |= CHANNEL_BITS(0x4 | start_channel); |
| 352 | break; |
| 353 | case 2: |
| 354 | if (start_channel == 0) |
| 355 | devpriv->config_bits |= CHANNEL_BITS(0x2); |
| 356 | else if (start_channel == 2) |
| 357 | devpriv->config_bits |= CHANNEL_BITS(0x3); |
| 358 | else |
| 359 | return -1; |
| 360 | break; |
| 361 | case 4: |
| 362 | devpriv->config_bits |= CHANNEL_BITS(0x1); |
| 363 | break; |
| 364 | default: |
| 365 | return -1; |
| 366 | } |
| 367 | |
| 368 | return 0; |
| 369 | } |
| 370 | |
H Hartley Sweeten | 8f61419 | 2014-04-16 14:19:18 -0700 | [diff] [blame] | 371 | static int a2150_ai_check_chanlist(struct comedi_device *dev, |
| 372 | struct comedi_subdevice *s, |
| 373 | struct comedi_cmd *cmd) |
| 374 | { |
| 375 | unsigned int chan0 = CR_CHAN(cmd->chanlist[0]); |
| 376 | unsigned int aref0 = CR_AREF(cmd->chanlist[0]); |
| 377 | int i; |
| 378 | |
| 379 | if (cmd->chanlist_len == 2 && (chan0 == 1 || chan0 == 3)) { |
| 380 | dev_dbg(dev->class_dev, |
| 381 | "length 2 chanlist must be channels 0,1 or channels 2,3\n"); |
| 382 | return -EINVAL; |
| 383 | } |
| 384 | |
| 385 | if (cmd->chanlist_len == 3) { |
| 386 | dev_dbg(dev->class_dev, |
| 387 | "chanlist must have 1,2 or 4 channels\n"); |
| 388 | return -EINVAL; |
| 389 | } |
| 390 | |
| 391 | for (i = 1; i < cmd->chanlist_len; i++) { |
| 392 | unsigned int chan = CR_CHAN(cmd->chanlist[i]); |
| 393 | unsigned int aref = CR_AREF(cmd->chanlist[i]); |
| 394 | |
| 395 | if (chan != (chan0 + i)) { |
| 396 | dev_dbg(dev->class_dev, |
| 397 | "entries in chanlist must be consecutive channels, counting upwards\n"); |
| 398 | return -EINVAL; |
| 399 | } |
| 400 | |
| 401 | if (chan == 2) |
| 402 | aref0 = aref; |
| 403 | if (aref != aref0) { |
| 404 | dev_dbg(dev->class_dev, |
| 405 | "channels 0/1 and 2/3 must have the same analog reference\n"); |
| 406 | return -EINVAL; |
| 407 | } |
| 408 | } |
| 409 | |
| 410 | return 0; |
| 411 | } |
| 412 | |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 413 | static int a2150_ai_cmdtest(struct comedi_device *dev, |
| 414 | struct comedi_subdevice *s, struct comedi_cmd *cmd) |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 415 | { |
H Hartley Sweeten | 94be3ef | 2015-06-18 10:54:44 -0700 | [diff] [blame] | 416 | const struct a2150_board *board = dev->board_ptr; |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 417 | int err = 0; |
H Hartley Sweeten | 75cff54 | 2014-05-27 10:12:51 -0700 | [diff] [blame] | 418 | unsigned int arg; |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 419 | |
H Hartley Sweeten | 27020ff | 2012-09-26 14:11:10 -0700 | [diff] [blame] | 420 | /* Step 1 : check if triggers are trivially valid */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 421 | |
Ian Abbott | ded2468 | 2015-03-27 19:14:21 +0000 | [diff] [blame] | 422 | err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT); |
| 423 | err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_TIMER); |
| 424 | err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW); |
| 425 | err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); |
| 426 | err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE); |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 427 | |
| 428 | if (err) |
| 429 | return 1; |
| 430 | |
H Hartley Sweeten | 27020ff | 2012-09-26 14:11:10 -0700 | [diff] [blame] | 431 | /* Step 2a : make sure trigger sources are unique */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 432 | |
Ian Abbott | ded2468 | 2015-03-27 19:14:21 +0000 | [diff] [blame] | 433 | err |= comedi_check_trigger_is_unique(cmd->start_src); |
| 434 | err |= comedi_check_trigger_is_unique(cmd->stop_src); |
H Hartley Sweeten | 27020ff | 2012-09-26 14:11:10 -0700 | [diff] [blame] | 435 | |
| 436 | /* Step 2b : and mutually compatible */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 437 | |
| 438 | if (err) |
| 439 | return 2; |
| 440 | |
H Hartley Sweeten | dd25484 | 2012-11-13 17:56:26 -0700 | [diff] [blame] | 441 | /* Step 3: check if arguments are trivially valid */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 442 | |
Ian Abbott | ded2468 | 2015-03-27 19:14:21 +0000 | [diff] [blame] | 443 | err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0); |
H Hartley Sweeten | dd25484 | 2012-11-13 17:56:26 -0700 | [diff] [blame] | 444 | |
Ian Abbott | ded2468 | 2015-03-27 19:14:21 +0000 | [diff] [blame] | 445 | if (cmd->convert_src == TRIG_TIMER) { |
| 446 | err |= comedi_check_trigger_arg_min(&cmd->convert_arg, |
H Hartley Sweeten | 94be3ef | 2015-06-18 10:54:44 -0700 | [diff] [blame] | 447 | board->ai_speed); |
Ian Abbott | ded2468 | 2015-03-27 19:14:21 +0000 | [diff] [blame] | 448 | } |
H Hartley Sweeten | dd25484 | 2012-11-13 17:56:26 -0700 | [diff] [blame] | 449 | |
Ian Abbott | ded2468 | 2015-03-27 19:14:21 +0000 | [diff] [blame] | 450 | err |= comedi_check_trigger_arg_min(&cmd->chanlist_len, 1); |
| 451 | err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg, |
| 452 | cmd->chanlist_len); |
H Hartley Sweeten | dd25484 | 2012-11-13 17:56:26 -0700 | [diff] [blame] | 453 | |
| 454 | if (cmd->stop_src == TRIG_COUNT) |
Ian Abbott | ded2468 | 2015-03-27 19:14:21 +0000 | [diff] [blame] | 455 | err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1); |
H Hartley Sweeten | dd25484 | 2012-11-13 17:56:26 -0700 | [diff] [blame] | 456 | else /* TRIG_NONE */ |
Ian Abbott | ded2468 | 2015-03-27 19:14:21 +0000 | [diff] [blame] | 457 | err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0); |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 458 | |
| 459 | if (err) |
| 460 | return 3; |
| 461 | |
| 462 | /* step 4: fix up any arguments */ |
| 463 | |
| 464 | if (cmd->scan_begin_src == TRIG_TIMER) { |
H Hartley Sweeten | 75cff54 | 2014-05-27 10:12:51 -0700 | [diff] [blame] | 465 | arg = cmd->scan_begin_arg; |
| 466 | a2150_get_timing(dev, &arg, cmd->flags); |
Ian Abbott | ded2468 | 2015-03-27 19:14:21 +0000 | [diff] [blame] | 467 | err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, arg); |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 468 | } |
| 469 | |
| 470 | if (err) |
| 471 | return 4; |
| 472 | |
H Hartley Sweeten | 8f61419 | 2014-04-16 14:19:18 -0700 | [diff] [blame] | 473 | /* Step 5: check channel list if it exists */ |
| 474 | if (cmd->chanlist && cmd->chanlist_len > 0) |
| 475 | err |= a2150_ai_check_chanlist(dev, s, cmd); |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 476 | |
| 477 | if (err) |
| 478 | return 5; |
| 479 | |
| 480 | return 0; |
| 481 | } |
| 482 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 483 | static int a2150_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 484 | { |
H Hartley Sweeten | 9a1a6cf | 2012-10-15 10:15:52 -0700 | [diff] [blame] | 485 | struct a2150_private *devpriv = dev->private; |
H Hartley Sweeten | 1a97f14 | 2015-01-14 10:05:09 -0700 | [diff] [blame] | 486 | struct comedi_isadma *dma = devpriv->dma; |
| 487 | struct comedi_isadma_desc *desc = &dma->desc[0]; |
Bill Pemberton | d163679 | 2009-03-16 22:05:20 -0400 | [diff] [blame] | 488 | struct comedi_async *async = s->async; |
Bill Pemberton | ea6d0d4 | 2009-03-16 22:05:47 -0400 | [diff] [blame] | 489 | struct comedi_cmd *cmd = &async->cmd; |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 490 | unsigned int old_config_bits = devpriv->config_bits; |
| 491 | unsigned int trigger_bits; |
| 492 | |
Ian Abbott | 34ae416 | 2014-09-03 13:45:27 +0100 | [diff] [blame] | 493 | if (cmd->flags & CMDF_PRIORITY) { |
H Hartley Sweeten | 770bc73 | 2014-07-17 11:57:35 -0700 | [diff] [blame] | 494 | dev_err(dev->class_dev, |
Ian Abbott | 34ae416 | 2014-09-03 13:45:27 +0100 | [diff] [blame] | 495 | "dma incompatible with hard real-time interrupt (CMDF_PRIORITY), aborting\n"); |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 496 | return -1; |
| 497 | } |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 498 | /* clear fifo and reset triggering circuitry */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 499 | outw(0, dev->iobase + FIFO_RESET_REG); |
| 500 | |
| 501 | /* setup chanlist */ |
| 502 | if (a2150_set_chanlist(dev, CR_CHAN(cmd->chanlist[0]), |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 503 | cmd->chanlist_len) < 0) |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 504 | return -1; |
| 505 | |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 506 | /* setup ac/dc coupling */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 507 | if (CR_AREF(cmd->chanlist[0]) == AREF_OTHER) |
| 508 | devpriv->config_bits |= AC0_BIT; |
| 509 | else |
| 510 | devpriv->config_bits &= ~AC0_BIT; |
| 511 | if (CR_AREF(cmd->chanlist[2]) == AREF_OTHER) |
| 512 | devpriv->config_bits |= AC1_BIT; |
| 513 | else |
| 514 | devpriv->config_bits &= ~AC1_BIT; |
| 515 | |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 516 | /* setup timing */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 517 | a2150_get_timing(dev, &cmd->scan_begin_arg, cmd->flags); |
| 518 | |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 519 | /* send timing, channel, config bits */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 520 | outw(devpriv->config_bits, dev->iobase + CONFIG_REG); |
| 521 | |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 522 | /* initialize number of samples remaining */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 523 | devpriv->count = cmd->stop_arg * cmd->chanlist_len; |
| 524 | |
H Hartley Sweeten | 1a97f14 | 2015-01-14 10:05:09 -0700 | [diff] [blame] | 525 | comedi_isadma_disable(desc->chan); |
H Hartley Sweeten | c92b0b2 | 2015-01-13 10:16:35 -0700 | [diff] [blame] | 526 | |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 527 | /* set size of transfer to fill in 1/3 second */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 528 | #define ONE_THIRD_SECOND 333333333 |
H Hartley Sweeten | 1a97f14 | 2015-01-14 10:05:09 -0700 | [diff] [blame] | 529 | desc->size = comedi_bytes_per_sample(s) * cmd->chanlist_len * |
H Hartley Sweeten | 5bf7d29 | 2015-01-12 10:55:50 -0700 | [diff] [blame] | 530 | ONE_THIRD_SECOND / cmd->scan_begin_arg; |
H Hartley Sweeten | 1a97f14 | 2015-01-14 10:05:09 -0700 | [diff] [blame] | 531 | if (desc->size > desc->maxsize) |
| 532 | desc->size = desc->maxsize; |
| 533 | if (desc->size < comedi_bytes_per_sample(s)) |
| 534 | desc->size = comedi_bytes_per_sample(s); |
| 535 | desc->size -= desc->size % comedi_bytes_per_sample(s); |
H Hartley Sweeten | c92b0b2 | 2015-01-13 10:16:35 -0700 | [diff] [blame] | 536 | |
H Hartley Sweeten | 1a97f14 | 2015-01-14 10:05:09 -0700 | [diff] [blame] | 537 | comedi_isadma_program(desc); |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 538 | |
| 539 | /* clear dma interrupt before enabling it, to try and get rid of that |
| 540 | * one spurious interrupt that has been happening */ |
| 541 | outw(0x00, dev->iobase + DMA_TC_CLEAR_REG); |
| 542 | |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 543 | /* enable dma on card */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 544 | devpriv->irq_dma_bits |= DMA_INTR_EN_BIT | DMA_EN_BIT; |
| 545 | outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG); |
| 546 | |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 547 | /* may need to wait 72 sampling periods if timing was changed */ |
H Hartley Sweeten | e875132 | 2015-02-23 14:57:44 -0700 | [diff] [blame] | 548 | comedi_8254_load(dev->pacer, 2, 72, I8254_MODE0 | I8254_BINARY); |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 549 | |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 550 | /* setup start triggering */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 551 | trigger_bits = 0; |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 552 | /* decide if we need to wait 72 periods for valid data */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 553 | if (cmd->start_src == TRIG_NOW && |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 554 | (old_config_bits & CLOCK_MASK) != |
| 555 | (devpriv->config_bits & CLOCK_MASK)) { |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 556 | /* set trigger source to delay trigger */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 557 | trigger_bits |= DELAY_TRIGGER_BITS; |
| 558 | } else { |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 559 | /* otherwise no delay */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 560 | trigger_bits |= POST_TRIGGER_BITS; |
| 561 | } |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 562 | /* enable external hardware trigger */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 563 | if (cmd->start_src == TRIG_EXT) { |
| 564 | trigger_bits |= HW_TRIG_EN; |
| 565 | } else if (cmd->start_src == TRIG_OTHER) { |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 566 | /* XXX add support for level/slope start trigger using TRIG_OTHER */ |
H Hartley Sweeten | 770bc73 | 2014-07-17 11:57:35 -0700 | [diff] [blame] | 567 | dev_err(dev->class_dev, "you shouldn't see this?\n"); |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 568 | } |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 569 | /* send trigger config bits */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 570 | outw(trigger_bits, dev->iobase + TRIGGER_REG); |
| 571 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 572 | /* start acquisition for soft trigger */ |
Ravishankar karkala Mallikarjunayya | a96b98f | 2011-12-12 10:49:26 +0530 | [diff] [blame] | 573 | if (cmd->start_src == TRIG_NOW) |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 574 | outw(0, dev->iobase + FIFO_START_REG); |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 575 | |
| 576 | return 0; |
| 577 | } |
| 578 | |
H Hartley Sweeten | 33a6d44 | 2014-02-10 11:49:25 -0700 | [diff] [blame] | 579 | static int a2150_ai_eoc(struct comedi_device *dev, |
| 580 | struct comedi_subdevice *s, |
| 581 | struct comedi_insn *insn, |
| 582 | unsigned long context) |
| 583 | { |
| 584 | unsigned int status; |
| 585 | |
| 586 | status = inw(dev->iobase + STATUS_REG); |
| 587 | if (status & FNE_BIT) |
| 588 | return 0; |
| 589 | return -EBUSY; |
| 590 | } |
| 591 | |
Bill Pemberton | da91b26 | 2009-04-09 16:07:03 -0400 | [diff] [blame] | 592 | static int a2150_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 593 | struct comedi_insn *insn, unsigned int *data) |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 594 | { |
H Hartley Sweeten | 9a1a6cf | 2012-10-15 10:15:52 -0700 | [diff] [blame] | 595 | struct a2150_private *devpriv = dev->private; |
H Hartley Sweeten | 33a6d44 | 2014-02-10 11:49:25 -0700 | [diff] [blame] | 596 | unsigned int n; |
| 597 | int ret; |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 598 | |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 599 | /* clear fifo and reset triggering circuitry */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 600 | outw(0, dev->iobase + FIFO_RESET_REG); |
| 601 | |
| 602 | /* setup chanlist */ |
| 603 | if (a2150_set_chanlist(dev, CR_CHAN(insn->chanspec), 1) < 0) |
| 604 | return -1; |
| 605 | |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 606 | /* set dc coupling */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 607 | devpriv->config_bits &= ~AC0_BIT; |
| 608 | devpriv->config_bits &= ~AC1_BIT; |
| 609 | |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 610 | /* send timing, channel, config bits */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 611 | outw(devpriv->config_bits, dev->iobase + CONFIG_REG); |
| 612 | |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 613 | /* disable dma on card */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 614 | devpriv->irq_dma_bits &= ~DMA_INTR_EN_BIT & ~DMA_EN_BIT; |
| 615 | outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG); |
| 616 | |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 617 | /* setup start triggering */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 618 | outw(0, dev->iobase + TRIGGER_REG); |
| 619 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 620 | /* start acquisition for soft trigger */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 621 | outw(0, dev->iobase + FIFO_START_REG); |
| 622 | |
Ravishankar Karkala Mallikarjunayya | 949fd38 | 2012-04-26 15:32:20 +0530 | [diff] [blame] | 623 | /* |
| 624 | * there is a 35.6 sample delay for data to get through the |
| 625 | * antialias filter |
| 626 | */ |
H Hartley Sweeten | 33a6d44 | 2014-02-10 11:49:25 -0700 | [diff] [blame] | 627 | for (n = 0; n < 36; n++) { |
| 628 | ret = comedi_timeout(dev, s, insn, a2150_ai_eoc, 0); |
H Hartley Sweeten | 22ca19d | 2014-02-10 11:49:45 -0700 | [diff] [blame] | 629 | if (ret) |
H Hartley Sweeten | 33a6d44 | 2014-02-10 11:49:25 -0700 | [diff] [blame] | 630 | return ret; |
H Hartley Sweeten | 33a6d44 | 2014-02-10 11:49:25 -0700 | [diff] [blame] | 631 | |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 632 | inw(dev->iobase + FIFO_DATA_REG); |
| 633 | } |
| 634 | |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 635 | /* read data */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 636 | for (n = 0; n < insn->n; n++) { |
H Hartley Sweeten | 33a6d44 | 2014-02-10 11:49:25 -0700 | [diff] [blame] | 637 | ret = comedi_timeout(dev, s, insn, a2150_ai_eoc, 0); |
H Hartley Sweeten | 22ca19d | 2014-02-10 11:49:45 -0700 | [diff] [blame] | 638 | if (ret) |
H Hartley Sweeten | 33a6d44 | 2014-02-10 11:49:25 -0700 | [diff] [blame] | 639 | return ret; |
H Hartley Sweeten | 33a6d44 | 2014-02-10 11:49:25 -0700 | [diff] [blame] | 640 | |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 641 | data[n] = inw(dev->iobase + FIFO_DATA_REG); |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 642 | data[n] ^= 0x8000; |
| 643 | } |
| 644 | |
Bill Pemberton | 30c687c | 2009-03-27 11:31:06 -0400 | [diff] [blame] | 645 | /* clear fifo and reset triggering circuitry */ |
Frank Mori Hess | 01b0a25 | 2009-02-19 10:01:19 -0800 | [diff] [blame] | 646 | outw(0, dev->iobase + FIFO_RESET_REG); |
| 647 | |
| 648 | return n; |
| 649 | } |
| 650 | |
H Hartley Sweeten | 1a97f14 | 2015-01-14 10:05:09 -0700 | [diff] [blame] | 651 | static void a2150_alloc_irq_and_dma(struct comedi_device *dev, |
| 652 | struct comedi_devconfig *it) |
H Hartley Sweeten | 7cbb0ef | 2015-01-12 10:55:48 -0700 | [diff] [blame] | 653 | { |
| 654 | struct a2150_private *devpriv = dev->private; |
| 655 | unsigned int irq_num = it->options[1]; |
| 656 | unsigned int dma_chan = it->options[2]; |
| 657 | |
| 658 | /* |
| 659 | * Only IRQs 15, 14, 12-9, and 7-3 are valid. |
| 660 | * Only DMA channels 7-5 and 3-0 are valid. |
H Hartley Sweeten | 7cbb0ef | 2015-01-12 10:55:48 -0700 | [diff] [blame] | 661 | */ |
| 662 | if (irq_num > 15 || dma_chan > 7 || |
| 663 | !((1 << irq_num) & 0xdef8) || !((1 << dma_chan) & 0xef)) |
| 664 | return; |
| 665 | |
H Hartley Sweeten | 7cbb0ef | 2015-01-12 10:55:48 -0700 | [diff] [blame] | 666 | if (request_irq(irq_num, a2150_interrupt, 0, dev->board_name, dev)) |
| 667 | return; |
H Hartley Sweeten | 7cbb0ef | 2015-01-12 10:55:48 -0700 | [diff] [blame] | 668 | |
H Hartley Sweeten | 1a97f14 | 2015-01-14 10:05:09 -0700 | [diff] [blame] | 669 | /* DMA uses 1 buffer */ |
| 670 | devpriv->dma = comedi_isadma_alloc(dev, 1, dma_chan, dma_chan, |
| 671 | A2150_DMA_BUFFER_SIZE, |
| 672 | COMEDI_ISADMA_READ); |
| 673 | if (!devpriv->dma) { |
| 674 | free_irq(irq_num, dev); |
| 675 | } else { |
| 676 | dev->irq = irq_num; |
| 677 | devpriv->irq_dma_bits = IRQ_LVL_BITS(irq_num) | |
| 678 | DMA_CHAN_BITS(dma_chan); |
| 679 | } |
H Hartley Sweeten | 7cbb0ef | 2015-01-12 10:55:48 -0700 | [diff] [blame] | 680 | } |
| 681 | |
H Hartley Sweeten | b147890 | 2015-01-12 10:55:49 -0700 | [diff] [blame] | 682 | static void a2150_free_dma(struct comedi_device *dev) |
| 683 | { |
| 684 | struct a2150_private *devpriv = dev->private; |
| 685 | |
H Hartley Sweeten | 1a97f14 | 2015-01-14 10:05:09 -0700 | [diff] [blame] | 686 | if (devpriv) |
| 687 | comedi_isadma_free(devpriv->dma); |
H Hartley Sweeten | b147890 | 2015-01-12 10:55:49 -0700 | [diff] [blame] | 688 | } |
| 689 | |
H Hartley Sweeten | 30f2306 | 2015-06-18 10:54:43 -0700 | [diff] [blame] | 690 | static const struct a2150_board *a2150_probe(struct comedi_device *dev) |
H Hartley Sweeten | fe14fa2 | 2012-05-15 17:17:14 -0700 | [diff] [blame] | 691 | { |
H Hartley Sweeten | 30f2306 | 2015-06-18 10:54:43 -0700 | [diff] [blame] | 692 | int id = ID_BITS(inw(dev->iobase + STATUS_REG)); |
H Hartley Sweeten | a95b7cc | 2014-07-16 11:02:03 -0700 | [diff] [blame] | 693 | |
H Hartley Sweeten | 30f2306 | 2015-06-18 10:54:43 -0700 | [diff] [blame] | 694 | if (id >= ARRAY_SIZE(a2150_boards)) |
| 695 | return NULL; |
| 696 | |
| 697 | return &a2150_boards[id]; |
H Hartley Sweeten | fe14fa2 | 2012-05-15 17:17:14 -0700 | [diff] [blame] | 698 | } |
| 699 | |
| 700 | static int a2150_attach(struct comedi_device *dev, struct comedi_devconfig *it) |
| 701 | { |
H Hartley Sweeten | 94be3ef | 2015-06-18 10:54:44 -0700 | [diff] [blame] | 702 | const struct a2150_board *board; |
H Hartley Sweeten | 9a1a6cf | 2012-10-15 10:15:52 -0700 | [diff] [blame] | 703 | struct a2150_private *devpriv; |
H Hartley Sweeten | fe14fa2 | 2012-05-15 17:17:14 -0700 | [diff] [blame] | 704 | struct comedi_subdevice *s; |
H Hartley Sweeten | fe14fa2 | 2012-05-15 17:17:14 -0700 | [diff] [blame] | 705 | static const int timeout = 2000; |
| 706 | int i; |
H Hartley Sweeten | 8b6c569 | 2012-06-12 11:59:33 -0700 | [diff] [blame] | 707 | int ret; |
H Hartley Sweeten | fe14fa2 | 2012-05-15 17:17:14 -0700 | [diff] [blame] | 708 | |
H Hartley Sweeten | 0bdab50 | 2013-06-24 16:55:44 -0700 | [diff] [blame] | 709 | devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); |
H Hartley Sweeten | c34fa26 | 2012-10-23 13:22:37 -0700 | [diff] [blame] | 710 | if (!devpriv) |
| 711 | return -ENOMEM; |
H Hartley Sweeten | fe14fa2 | 2012-05-15 17:17:14 -0700 | [diff] [blame] | 712 | |
H Hartley Sweeten | 862755e | 2014-07-18 17:01:22 -0700 | [diff] [blame] | 713 | ret = comedi_request_region(dev, it->options[0], 0x1c); |
H Hartley Sweeten | 3671cae | 2013-04-09 16:24:42 -0700 | [diff] [blame] | 714 | if (ret) |
| 715 | return ret; |
H Hartley Sweeten | fe14fa2 | 2012-05-15 17:17:14 -0700 | [diff] [blame] | 716 | |
H Hartley Sweeten | 94be3ef | 2015-06-18 10:54:44 -0700 | [diff] [blame] | 717 | board = a2150_probe(dev); |
| 718 | if (!board) |
Ian Abbott | e988e1f | 2014-09-01 14:13:30 +0100 | [diff] [blame] | 719 | return -ENODEV; |
H Hartley Sweeten | 94be3ef | 2015-06-18 10:54:44 -0700 | [diff] [blame] | 720 | dev->board_ptr = board; |
| 721 | dev->board_name = board->name; |
H Hartley Sweeten | fe14fa2 | 2012-05-15 17:17:14 -0700 | [diff] [blame] | 722 | |
H Hartley Sweeten | 1a97f14 | 2015-01-14 10:05:09 -0700 | [diff] [blame] | 723 | /* an IRQ and DMA are required to support async commands */ |
| 724 | a2150_alloc_irq_and_dma(dev, it); |
H Hartley Sweeten | 6cb8e1a | 2013-12-05 13:43:21 -0700 | [diff] [blame] | 725 | |
H Hartley Sweeten | e875132 | 2015-02-23 14:57:44 -0700 | [diff] [blame] | 726 | dev->pacer = comedi_8254_init(dev->iobase + I8253_BASE_REG, |
| 727 | 0, I8254_IO8, 0); |
| 728 | if (!dev->pacer) |
| 729 | return -ENOMEM; |
| 730 | |
H Hartley Sweeten | 8b6c569 | 2012-06-12 11:59:33 -0700 | [diff] [blame] | 731 | ret = comedi_alloc_subdevices(dev, 1); |
| 732 | if (ret) |
| 733 | return ret; |
H Hartley Sweeten | fe14fa2 | 2012-05-15 17:17:14 -0700 | [diff] [blame] | 734 | |
| 735 | /* analog input subdevice */ |
H Hartley Sweeten | ca3caab | 2012-09-05 18:48:20 -0700 | [diff] [blame] | 736 | s = &dev->subdevices[0]; |
H Hartley Sweeten | fe14fa2 | 2012-05-15 17:17:14 -0700 | [diff] [blame] | 737 | s->type = COMEDI_SUBD_AI; |
H Hartley Sweeten | 6cb8e1a | 2013-12-05 13:43:21 -0700 | [diff] [blame] | 738 | s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_OTHER; |
H Hartley Sweeten | fe14fa2 | 2012-05-15 17:17:14 -0700 | [diff] [blame] | 739 | s->n_chan = 4; |
H Hartley Sweeten | fe14fa2 | 2012-05-15 17:17:14 -0700 | [diff] [blame] | 740 | s->maxdata = 0xffff; |
| 741 | s->range_table = &range_a2150; |
H Hartley Sweeten | fe14fa2 | 2012-05-15 17:17:14 -0700 | [diff] [blame] | 742 | s->insn_read = a2150_ai_rinsn; |
H Hartley Sweeten | 7cbb0ef | 2015-01-12 10:55:48 -0700 | [diff] [blame] | 743 | if (dev->irq) { |
H Hartley Sweeten | 6cb8e1a | 2013-12-05 13:43:21 -0700 | [diff] [blame] | 744 | dev->read_subdev = s; |
| 745 | s->subdev_flags |= SDF_CMD_READ; |
| 746 | s->len_chanlist = s->n_chan; |
| 747 | s->do_cmd = a2150_ai_cmd; |
| 748 | s->do_cmdtest = a2150_ai_cmdtest; |
| 749 | s->cancel = a2150_cancel; |
| 750 | } |
H Hartley Sweeten | fe14fa2 | 2012-05-15 17:17:14 -0700 | [diff] [blame] | 751 | |
H Hartley Sweeten | fe14fa2 | 2012-05-15 17:17:14 -0700 | [diff] [blame] | 752 | /* set card's irq and dma levels */ |
| 753 | outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG); |
| 754 | |
| 755 | /* reset and sync adc clock circuitry */ |
| 756 | outw_p(DPD_BIT | APD_BIT, dev->iobase + CONFIG_REG); |
| 757 | outw_p(DPD_BIT, dev->iobase + CONFIG_REG); |
| 758 | /* initialize configuration register */ |
| 759 | devpriv->config_bits = 0; |
| 760 | outw(devpriv->config_bits, dev->iobase + CONFIG_REG); |
| 761 | /* wait until offset calibration is done, then enable analog inputs */ |
| 762 | for (i = 0; i < timeout; i++) { |
| 763 | if ((DCAL_BIT & inw(dev->iobase + STATUS_REG)) == 0) |
| 764 | break; |
| 765 | udelay(1000); |
| 766 | } |
| 767 | if (i == timeout) { |
H Hartley Sweeten | bc0640a | 2014-07-18 13:29:56 -0700 | [diff] [blame] | 768 | dev_err(dev->class_dev, |
| 769 | "timed out waiting for offset calibration to complete\n"); |
H Hartley Sweeten | fe14fa2 | 2012-05-15 17:17:14 -0700 | [diff] [blame] | 770 | return -ETIME; |
| 771 | } |
| 772 | devpriv->config_bits |= ENABLE0_BIT | ENABLE1_BIT; |
| 773 | outw(devpriv->config_bits, dev->iobase + CONFIG_REG); |
| 774 | |
| 775 | return 0; |
| 776 | }; |
| 777 | |
H Hartley Sweeten | 484ecc9 | 2012-05-17 17:11:14 -0700 | [diff] [blame] | 778 | static void a2150_detach(struct comedi_device *dev) |
H Hartley Sweeten | fe14fa2 | 2012-05-15 17:17:14 -0700 | [diff] [blame] | 779 | { |
H Hartley Sweeten | a32c6d0 | 2013-04-18 14:34:19 -0700 | [diff] [blame] | 780 | if (dev->iobase) |
H Hartley Sweeten | fe14fa2 | 2012-05-15 17:17:14 -0700 | [diff] [blame] | 781 | outw(APD_BIT | DPD_BIT, dev->iobase + CONFIG_REG); |
H Hartley Sweeten | b147890 | 2015-01-12 10:55:49 -0700 | [diff] [blame] | 782 | a2150_free_dma(dev); |
H Hartley Sweeten | a32c6d0 | 2013-04-18 14:34:19 -0700 | [diff] [blame] | 783 | comedi_legacy_detach(dev); |
H Hartley Sweeten | fe14fa2 | 2012-05-15 17:17:14 -0700 | [diff] [blame] | 784 | }; |
| 785 | |
| 786 | static struct comedi_driver ni_at_a2150_driver = { |
| 787 | .driver_name = "ni_at_a2150", |
| 788 | .module = THIS_MODULE, |
| 789 | .attach = a2150_attach, |
| 790 | .detach = a2150_detach, |
| 791 | }; |
| 792 | module_comedi_driver(ni_at_a2150_driver); |
| 793 | |
Arun Thomas | 90f703d | 2010-06-06 22:23:29 +0200 | [diff] [blame] | 794 | MODULE_AUTHOR("Comedi http://www.comedi.org"); |
| 795 | MODULE_DESCRIPTION("Comedi low-level driver"); |
| 796 | MODULE_LICENSE("GPL"); |