Larry Finger | fff3340 | 2013-08-21 22:34:11 -0500 | [diff] [blame] | 1 | /****************************************************************************** |
| 2 | * |
| 3 | * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of version 2 of the GNU General Public License as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
Larry Finger | fff3340 | 2013-08-21 22:34:11 -0500 | [diff] [blame] | 14 | ******************************************************************************/ |
| 15 | #ifndef __RTW_PWRCTRL_H_ |
| 16 | #define __RTW_PWRCTRL_H_ |
| 17 | |
| 18 | #include <osdep_service.h> |
| 19 | #include <drv_types.h> |
| 20 | |
| 21 | #define FW_PWR0 0 |
| 22 | #define FW_PWR1 1 |
| 23 | #define FW_PWR2 2 |
| 24 | #define FW_PWR3 3 |
| 25 | #define HW_PWR0 7 |
| 26 | #define HW_PWR1 6 |
| 27 | #define HW_PWR2 2 |
| 28 | #define HW_PWR3 0 |
| 29 | #define HW_PWR4 8 |
| 30 | |
| 31 | #define FW_PWRMSK 0x7 |
| 32 | |
| 33 | #define XMIT_ALIVE BIT(0) |
| 34 | #define RECV_ALIVE BIT(1) |
| 35 | #define CMD_ALIVE BIT(2) |
| 36 | #define EVT_ALIVE BIT(3) |
| 37 | |
| 38 | enum power_mgnt { |
| 39 | PS_MODE_ACTIVE = 0, |
| 40 | PS_MODE_MIN, |
| 41 | PS_MODE_MAX, |
| 42 | PS_MODE_DTIM, |
| 43 | PS_MODE_VOIP, |
| 44 | PS_MODE_UAPSD_WMM, |
| 45 | PS_MODE_UAPSD, |
| 46 | PS_MODE_IBSS, |
| 47 | PS_MODE_WWLAN, |
| 48 | PM_Radio_Off, |
| 49 | PM_Card_Disable, |
| 50 | PS_MODE_NUM |
| 51 | }; |
| 52 | |
| 53 | /* |
| 54 | BIT[2:0] = HW state |
| 55 | BIT[3] = Protocol PS state, 0: register active state, |
| 56 | 1: register sleep state |
| 57 | BIT[4] = sub-state |
| 58 | */ |
| 59 | |
| 60 | #define PS_DPS BIT(0) |
| 61 | #define PS_LCLK (PS_DPS) |
| 62 | #define PS_RF_OFF BIT(1) |
| 63 | #define PS_ALL_ON BIT(2) |
| 64 | #define PS_ST_ACTIVE BIT(3) |
| 65 | |
| 66 | #define PS_ISR_ENABLE BIT(4) |
| 67 | #define PS_IMR_ENABLE BIT(5) |
| 68 | #define PS_ACK BIT(6) |
| 69 | #define PS_TOGGLE BIT(7) |
| 70 | |
| 71 | #define PS_STATE_MASK (0x0F) |
| 72 | #define PS_STATE_HW_MASK (0x07) |
| 73 | #define PS_SEQ_MASK (0xc0) |
| 74 | |
| 75 | #define PS_STATE(x) (PS_STATE_MASK & (x)) |
| 76 | #define PS_STATE_HW(x) (PS_STATE_HW_MASK & (x)) |
| 77 | #define PS_SEQ(x) (PS_SEQ_MASK & (x)) |
| 78 | |
| 79 | #define PS_STATE_S0 (PS_DPS) |
| 80 | #define PS_STATE_S1 (PS_LCLK) |
| 81 | #define PS_STATE_S2 (PS_RF_OFF) |
| 82 | #define PS_STATE_S3 (PS_ALL_ON) |
| 83 | #define PS_STATE_S4 ((PS_ST_ACTIVE) | (PS_ALL_ON)) |
| 84 | |
| 85 | #define PS_IS_RF_ON(x) ((x) & (PS_ALL_ON)) |
| 86 | #define PS_IS_ACTIVE(x) ((x) & (PS_ST_ACTIVE)) |
| 87 | #define CLR_PS_STATE(x) ((x) = ((x) & (0xF0))) |
| 88 | |
| 89 | struct reportpwrstate_parm { |
| 90 | unsigned char mode; |
| 91 | unsigned char state; /* the CPWM value */ |
| 92 | unsigned short rsvd; |
| 93 | }; |
| 94 | |
| 95 | static inline void _init_pwrlock(struct semaphore *plock) |
| 96 | { |
Larry Finger | efbef10 | 2013-12-22 17:36:40 -0600 | [diff] [blame] | 97 | sema_init(plock, 1); |
Larry Finger | fff3340 | 2013-08-21 22:34:11 -0500 | [diff] [blame] | 98 | } |
| 99 | |
Larry Finger | fff3340 | 2013-08-21 22:34:11 -0500 | [diff] [blame] | 100 | static inline void _enter_pwrlock(struct semaphore *plock) |
| 101 | { |
| 102 | _rtw_down_sema(plock); |
| 103 | } |
| 104 | |
| 105 | static inline void _exit_pwrlock(struct semaphore *plock) |
| 106 | { |
Larry Finger | 2ca4ab5 | 2013-12-22 17:36:41 -0600 | [diff] [blame] | 107 | up(plock); |
Larry Finger | fff3340 | 2013-08-21 22:34:11 -0500 | [diff] [blame] | 108 | } |
| 109 | |
| 110 | #define LPS_DELAY_TIME 1*HZ /* 1 sec */ |
| 111 | |
| 112 | #define EXE_PWR_NONE 0x01 |
| 113 | #define EXE_PWR_IPS 0x02 |
| 114 | #define EXE_PWR_LPS 0x04 |
| 115 | |
| 116 | /* RF state. */ |
| 117 | enum rt_rf_power_state { |
| 118 | rf_on, /* RF is on after RFSleep or RFOff */ |
| 119 | rf_sleep, /* 802.11 Power Save mode */ |
| 120 | rf_off, /* HW/SW Radio OFF or Inactive Power Save */ |
| 121 | /* Add the new RF state above this line===== */ |
| 122 | rf_max |
| 123 | }; |
| 124 | |
| 125 | /* RF Off Level for IPS or HW/SW radio off */ |
| 126 | #define RT_RF_OFF_LEVL_ASPM BIT(0) /* PCI ASPM */ |
| 127 | #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /* PCI clock request */ |
| 128 | #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /* PCI D3 mode */ |
| 129 | #define RT_RF_OFF_LEVL_HALT_NIC BIT(3) /* NIC halt, re-init hw param*/ |
| 130 | #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /* FW free, re-download the FW*/ |
| 131 | #define RT_RF_OFF_LEVL_FW_32K BIT(5) /* FW in 32k */ |
| 132 | #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) /* Always enable ASPM and Clock |
| 133 | * Req in initialization. */ |
| 134 | #define RT_RF_LPS_DISALBE_2R BIT(30) /* When LPS is on, disable 2R |
| 135 | * if no packet is RX or TX. */ |
| 136 | #define RT_RF_LPS_LEVEL_ASPM BIT(31) /* LPS with ASPM */ |
| 137 | |
| 138 | #define RT_IN_PS_LEVEL(ppsc, _PS_FLAG) \ |
| 139 | ((ppsc->cur_ps_level & _PS_FLAG) ? true : false) |
| 140 | #define RT_CLEAR_PS_LEVEL(ppsc, _PS_FLAG) \ |
| 141 | (ppsc->cur_ps_level &= (~(_PS_FLAG))) |
| 142 | #define RT_SET_PS_LEVEL(ppsc, _PS_FLAG) \ |
| 143 | (ppsc->cur_ps_level |= _PS_FLAG) |
| 144 | |
| 145 | enum _PS_BBRegBackup_ { |
| 146 | PSBBREG_RF0 = 0, |
| 147 | PSBBREG_RF1, |
| 148 | PSBBREG_RF2, |
| 149 | PSBBREG_AFE0, |
| 150 | PSBBREG_TOTALCNT |
| 151 | }; |
| 152 | |
| 153 | enum { /* for ips_mode */ |
| 154 | IPS_NONE = 0, |
| 155 | IPS_NORMAL, |
| 156 | IPS_LEVEL_2, |
| 157 | }; |
| 158 | |
| 159 | struct pwrctrl_priv { |
| 160 | struct semaphore lock; |
| 161 | volatile u8 rpwm; /* requested power state for fw */ |
| 162 | volatile u8 cpwm; /* fw current power state. updated when |
| 163 | * 1. read from HCPWM 2. driver lowers power level */ |
| 164 | volatile u8 tog; /* toggling */ |
| 165 | volatile u8 cpwm_tog; /* toggling */ |
| 166 | |
| 167 | u8 pwr_mode; |
| 168 | u8 smart_ps; |
| 169 | u8 bcn_ant_mode; |
| 170 | |
| 171 | u32 alives; |
| 172 | struct work_struct cpwm_event; |
| 173 | u8 bpower_saving; |
| 174 | |
| 175 | u8 b_hw_radio_off; |
| 176 | u8 reg_rfoff; |
| 177 | u8 reg_pdnmode; /* powerdown mode */ |
| 178 | u32 rfoff_reason; |
| 179 | |
| 180 | /* RF OFF Level */ |
| 181 | u32 cur_ps_level; |
| 182 | u32 reg_rfps_level; |
| 183 | uint ips_enter_cnts; |
| 184 | uint ips_leave_cnts; |
| 185 | |
| 186 | u8 ips_mode; |
| 187 | u8 ips_mode_req; /* used to accept the mode setting request, |
| 188 | * will update to ipsmode later */ |
| 189 | uint bips_processing; |
Manuel Schölling | e017a92 | 2014-05-25 15:05:24 +0200 | [diff] [blame] | 190 | unsigned long ips_deny_time; /* will deny IPS when system time less than this */ |
Larry Finger | fff3340 | 2013-08-21 22:34:11 -0500 | [diff] [blame] | 191 | u8 ps_processing; /* temp used to mark whether in rtw_ps_processor */ |
| 192 | |
| 193 | u8 bLeisurePs; |
| 194 | u8 LpsIdleCount; |
| 195 | u8 power_mgnt; |
| 196 | u8 bFwCurrentInPSMode; |
| 197 | u32 DelayLPSLastTimeStamp; |
| 198 | u8 btcoex_rfon; |
| 199 | s32 pnp_current_pwr_state; |
| 200 | u8 pnp_bstop_trx; |
| 201 | |
| 202 | u8 bInternalAutoSuspend; |
| 203 | u8 bInSuspend; |
Larry Finger | fff3340 | 2013-08-21 22:34:11 -0500 | [diff] [blame] | 204 | u8 bSupportRemoteWakeup; |
| 205 | struct timer_list pwr_state_check_timer; |
| 206 | int pwr_state_check_interval; |
| 207 | u8 pwr_state_check_cnts; |
| 208 | |
| 209 | int ps_flag; |
| 210 | |
| 211 | enum rt_rf_power_state rf_pwrstate;/* cur power state */ |
| 212 | enum rt_rf_power_state change_rfpwrstate; |
| 213 | |
| 214 | u8 wepkeymask; |
| 215 | u8 bHWPowerdown;/* if support hw power down */ |
| 216 | u8 bHWPwrPindetect; |
| 217 | u8 bkeepfwalive; |
| 218 | u8 brfoffbyhw; |
| 219 | unsigned long PS_BBRegBackup[PSBBREG_TOTALCNT]; |
| 220 | }; |
| 221 | |
| 222 | #define rtw_get_ips_mode_req(pwrctrlpriv) \ |
| 223 | (pwrctrlpriv)->ips_mode_req |
| 224 | |
| 225 | #define rtw_ips_mode_req(pwrctrlpriv, ips_mode) \ |
| 226 | ((pwrctrlpriv)->ips_mode_req = (ips_mode)) |
| 227 | |
| 228 | #define RTW_PWR_STATE_CHK_INTERVAL 2000 |
| 229 | |
| 230 | #define _rtw_set_pwr_state_check_timer(pwrctrlpriv, ms) \ |
Vaishali Thakkar | 4d4efe3 | 2015-03-11 11:41:07 +0530 | [diff] [blame] | 231 | mod_timer(&pwrctrlpriv->pwr_state_check_timer, \ |
| 232 | jiffies + msecs_to_jiffies(ms)) |
Larry Finger | fff3340 | 2013-08-21 22:34:11 -0500 | [diff] [blame] | 233 | |
| 234 | #define rtw_set_pwr_state_check_timer(pwrctrl) \ |
| 235 | _rtw_set_pwr_state_check_timer((pwrctrl), \ |
| 236 | (pwrctrl)->pwr_state_check_interval) |
| 237 | |
| 238 | void rtw_init_pwrctrl_priv(struct adapter *adapter); |
Larry Finger | fff3340 | 2013-08-21 22:34:11 -0500 | [diff] [blame] | 239 | |
| 240 | void rtw_set_ps_mode(struct adapter *adapter, u8 ps_mode, u8 smart_ps, |
| 241 | u8 bcn_ant_mode); |
| 242 | void rtw_set_rpwm(struct adapter *adapter, u8 val8); |
| 243 | void LeaveAllPowerSaveMode(struct adapter *adapter); |
| 244 | void ips_enter(struct adapter *padapter); |
| 245 | int ips_leave(struct adapter *padapter); |
| 246 | |
| 247 | void rtw_ps_processor(struct adapter *padapter); |
| 248 | |
| 249 | enum rt_rf_power_state RfOnOffDetect(struct adapter *iadapter); |
| 250 | |
| 251 | s32 LPS_RF_ON_check(struct adapter *adapter, u32 delay_ms); |
| 252 | void LPS_Enter(struct adapter *adapter); |
| 253 | void LPS_Leave(struct adapter *adapter); |
| 254 | |
Larry Finger | fff3340 | 2013-08-21 22:34:11 -0500 | [diff] [blame] | 255 | int _rtw_pwr_wakeup(struct adapter *adapter, u32 ips_defer_ms, |
| 256 | const char *caller); |
| 257 | #define rtw_pwr_wakeup(adapter) \ |
| 258 | _rtw_pwr_wakeup(adapter, RTW_PWR_STATE_CHK_INTERVAL, __func__) |
| 259 | #define rtw_pwr_wakeup_ex(adapter, ips_deffer_ms) \ |
| 260 | _rtw_pwr_wakeup(adapter, ips_deffer_ms, __func__) |
| 261 | int rtw_pm_set_ips(struct adapter *adapter, u8 mode); |
| 262 | int rtw_pm_set_lps(struct adapter *adapter, u8 mode); |
| 263 | |
| 264 | #endif /* __RTL871X_PWRCTRL_H_ */ |