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Larry Finger364e30e2014-03-28 21:37:41 -05001/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 ******************************************************************************/
15#ifndef __RTW_PWRCTRL_H_
16#define __RTW_PWRCTRL_H_
17
18#include <osdep_service.h>
19#include <drv_types.h>
20
21#define FW_PWR0 0
22#define FW_PWR1 1
23#define FW_PWR2 2
24#define FW_PWR3 3
25
26
27#define HW_PWR0 7
28#define HW_PWR1 6
29#define HW_PWR2 2
30#define HW_PWR3 0
31#define HW_PWR4 8
32
33#define FW_PWRMSK 0x7
34
35
36#define XMIT_ALIVE BIT(0)
37#define RECV_ALIVE BIT(1)
38#define CMD_ALIVE BIT(2)
39#define EVT_ALIVE BIT(3)
40
41enum Power_Mgnt {
42 PS_MODE_ACTIVE = 0,
43 PS_MODE_MIN,
44 PS_MODE_MAX,
45 PS_MODE_DTIM,
46 PS_MODE_VOIP,
47 PS_MODE_UAPSD_WMM,
48 PS_MODE_UAPSD,
49 PS_MODE_IBSS,
50 PS_MODE_WWLAN,
51 PM_Radio_Off,
52 PM_Card_Disable,
53 PS_MODE_NUM
54};
55
56
57/* BIT[2:0] = HW state
58 * BIT[3] = Protocol PS state, 0: active, 1: sleep state
59 * BIT[4] = sub-state
60 */
61
62#define PS_DPS BIT(0)
63#define PS_LCLK (PS_DPS)
64#define PS_RF_OFF BIT(1)
65#define PS_ALL_ON BIT(2)
66#define PS_ST_ACTIVE BIT(3)
67
68#define PS_ISR_ENABLE BIT(4)
69#define PS_IMR_ENABLE BIT(5)
70#define PS_ACK BIT(6)
71#define PS_TOGGLE BIT(7)
72
73#define PS_STATE_MASK (0x0F)
74#define PS_STATE_HW_MASK (0x07)
75#define PS_SEQ_MASK (0xc0)
76
77#define PS_STATE(x) (PS_STATE_MASK & (x))
78#define PS_STATE_HW(x) (PS_STATE_HW_MASK & (x))
79#define PS_SEQ(x) (PS_SEQ_MASK & (x))
80
81#define PS_STATE_S0 (PS_DPS)
82#define PS_STATE_S1 (PS_LCLK)
83#define PS_STATE_S2 (PS_RF_OFF)
84#define PS_STATE_S3 (PS_ALL_ON)
85#define PS_STATE_S4 ((PS_ST_ACTIVE) | (PS_ALL_ON))
86
87
88#define PS_IS_RF_ON(x) ((x) & (PS_ALL_ON))
89#define PS_IS_ACTIVE(x) ((x) & (PS_ST_ACTIVE))
90#define CLR_PS_STATE(x) ((x) = ((x) & (0xF0)))
91
92
93struct reportpwrstate_parm {
94 unsigned char mode;
95 unsigned char state; /* the CPWM value */
96 unsigned short rsvd;
97};
98
99#define LPS_DELAY_TIME (1*HZ) /* 1 sec */
100
101#define EXE_PWR_NONE 0x01
102#define EXE_PWR_IPS 0x02
103#define EXE_PWR_LPS 0x04
104
105/* RF state. */
106enum rt_rf_power_state {
107 rf_on, /* RF is on after RFSleep or RFOff */
108 rf_sleep, /* 802.11 Power Save mode */
109 rf_off, /* HW/SW Radio OFF or Inactive Power Save */
110 /* Add the new RF state above this line===== */
111 rf_max
112};
113
114/* RF Off Level for IPS or HW/SW radio off */
115#define RT_RF_OFF_LEVL_ASPM BIT(0) /* PCI ASPM */
116#define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /* PCI clock request */
117#define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /* PCI D3 mode */
118/* NIC halt, re-init hw params */
119#define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
120/* FW free, re-download the FW */
121#define RT_RF_OFF_LEVL_FREE_FW BIT(4)
122#define RT_RF_OFF_LEVL_FW_32K BIT(5) /* FW in 32k */
123/* Always enable ASPM and Clock Req in initialization. */
124#define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
125/* When LPS is on, disable 2R if no packet is received or transmittd. */
126#define RT_RF_LPS_DISALBE_2R BIT(30)
127#define RT_RF_LPS_LEVEL_ASPM BIT(31) /* LPS with ASPM */
128
129#define RT_IN_PS_LEVEL(ppsc, _PS_FLAG) \
130 ((ppsc->cur_ps_level & _PS_FLAG) ? true : false)
131#define RT_CLEAR_PS_LEVEL(ppsc, _PS_FLAG) \
132 (ppsc->cur_ps_level &= (~(_PS_FLAG)))
133#define RT_SET_PS_LEVEL(ppsc, _PS_FLAG) \
134 (ppsc->cur_ps_level |= _PS_FLAG)
135
136
137enum {
138 PSBBREG_RF0 = 0,
139 PSBBREG_RF1,
140 PSBBREG_RF2,
141 PSBBREG_AFE0,
142 PSBBREG_TOTALCNT
143};
144
145enum { /* for ips_mode */
146 IPS_NONE = 0,
147 IPS_NORMAL,
148 IPS_LEVEL_2,
149};
150
151struct pwrctrl_priv {
152 struct semaphore lock;
153 volatile u8 rpwm; /* requested power state for fw */
154 volatile u8 cpwm; /* fw current power state. updated when 1.
155 * read from HCPWM 2. driver lowers power level
156 */
157 volatile u8 tog; /* toggling */
Larry Finger364e30e2014-03-28 21:37:41 -0500158
159 u8 pwr_mode;
160 u8 smart_ps;
161 u8 bcn_ant_mode;
162
Larry Finger364e30e2014-03-28 21:37:41 -0500163 u8 bpower_saving;
164
Larry Finger364e30e2014-03-28 21:37:41 -0500165 u8 reg_rfoff;
Larry Finger364e30e2014-03-28 21:37:41 -0500166 u32 rfoff_reason;
167
168 /* RF OFF Level */
169 u32 cur_ps_level;
170 u32 reg_rfps_level;
171
172 uint ips_enter23a_cnts;
173 uint ips_leave23a_cnts;
174
175 u8 ips_mode;
176 u8 ips_mode_req; /* used to accept the mode setting request */
177 uint bips_processing;
Larry Fingerc17416e2014-03-28 21:37:42 -0500178 unsigned long ips_deny_time; /* deny IPS when system time is smaller */
Larry Finger364e30e2014-03-28 21:37:41 -0500179 u8 ps_processing; /* used to mark whether in rtw_ps_processor23a */
180
181 u8 bLeisurePs;
182 u8 LpsIdleCount;
183 u8 power_mgnt;
184 u8 bFwCurrentInPSMode;
185 unsigned long DelayLPSLastTimeStamp;
186 u8 btcoex_rfon;
Larry Finger364e30e2014-03-28 21:37:41 -0500187
Larry Finger364e30e2014-03-28 21:37:41 -0500188 u8 bInSuspend;
189#ifdef CONFIG_8723AU_BT_COEXIST
190 u8 bAutoResume;
191 u8 autopm_cnt;
192#endif
193 u8 bSupportRemoteWakeup;
194 struct timer_list pwr_state_check_timer;
195 int pwr_state_check_interval;
196 u8 pwr_state_check_cnts;
197
Larry Finger364e30e2014-03-28 21:37:41 -0500198 enum rt_rf_power_state rf_pwrstate;/* cur power state */
199 enum rt_rf_power_state change_rfpwrstate;
200
Larry Finger364e30e2014-03-28 21:37:41 -0500201 u8 bkeepfwalive;
Larry Finger364e30e2014-03-28 21:37:41 -0500202 unsigned long PS_BBRegBackup[PSBBREG_TOTALCNT];
203};
204
Larry Finger364e30e2014-03-28 21:37:41 -0500205#define RTW_PWR_STATE_CHK_INTERVAL 2000
206
207#define _rtw_set_pwr_state_check_timer(pwrctrlpriv, ms) \
208 (mod_timer(&pwrctrlpriv->pwr_state_check_timer, jiffies + \
209 msecs_to_jiffies(ms)))
210
211#define rtw_set_pwr_state_check_timer(pwrctrlpriv) \
212 (_rtw_set_pwr_state_check_timer((pwrctrlpriv), \
213 (pwrctrlpriv)->pwr_state_check_interval))
214
215void rtw_init_pwrctrl_priv23a(struct rtw_adapter *adapter);
216void rtw_free_pwrctrl_priv(struct rtw_adapter *adapter);
217
218void rtw_set_ps_mode23a(struct rtw_adapter *padapter, u8 ps_mode,
219 u8 smart_ps, u8 bcn_ant_mode);
220void rtw_set_rpwm23a(struct rtw_adapter *padapter, u8 val8);
221void LeaveAllPowerSaveMode23a(struct rtw_adapter *adapter);
222void ips_enter23a(struct rtw_adapter *padapter);
223int ips_leave23a(struct rtw_adapter *padapter);
224
225void rtw_ps_processor23a(struct rtw_adapter *padapter);
226
227enum rt_rf_power_state RfOnOffDetect23a(struct rtw_adapter *adapter);
228
229s32 LPS_RF_ON_check23a(struct rtw_adapter *padapter, u32 delay_ms);
230void LPS_Enter23a(struct rtw_adapter *padapter);
231void LPS_Leave23a(struct rtw_adapter *padapter);
232
Larry Finger364e30e2014-03-28 21:37:41 -0500233void rtw_set_ips_deny23a(struct rtw_adapter *padapter, u32 ms);
234int _rtw_pwr_wakeup23a(struct rtw_adapter *padapter, u32 ips_deffer_ms,
235 const char *caller);
236#define rtw_pwr_wakeup(adapter) _rtw_pwr_wakeup23a(adapter, \
237 RTW_PWR_STATE_CHK_INTERVAL, __func__)
Larry Finger364e30e2014-03-28 21:37:41 -0500238int rtw_pm_set_ips23a(struct rtw_adapter *padapter, u8 mode);
239int rtw_pm_set_lps23a(struct rtw_adapter *padapter, u8 mode);
240
241#endif /* __RTL871X_PWRCTRL_H_ */