blob: 5032141eeeec4ee0cbb46b7d7af7c8a65e76212c [file] [log] [blame]
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +00001/*
2 * MPC512x PSC in SPI mode driver.
3 *
4 * Copyright (C) 2007,2008 Freescale Semiconductor Inc.
5 * Original port from 52xx driver:
6 * Hongjun Chen <hong-jun.chen@freescale.com>
7 *
8 * Fork of mpc52xx_psc_spi.c:
9 * Copyright (C) 2006 TOPTICA Photonics AG., Dragos Carp
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/errno.h>
21#include <linux/interrupt.h>
Grant Likely22ae7822010-07-29 11:49:01 -060022#include <linux/of_address.h>
Rob Herring5af50732013-09-17 14:28:33 -050023#include <linux/of_irq.h>
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +000024#include <linux/of_platform.h>
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +000025#include <linux/completion.h>
26#include <linux/io.h>
27#include <linux/delay.h>
28#include <linux/clk.h>
29#include <linux/spi/spi.h>
30#include <linux/fsl_devices.h>
Anatolij Gustschin86e98742013-04-01 17:29:21 +020031#include <linux/gpio.h>
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +000032#include <asm/mpc52xx_psc.h>
33
34struct mpc512x_psc_spi {
35 void (*cs_control)(struct spi_device *spi, bool on);
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +000036
37 /* driver internal data */
38 struct mpc52xx_psc __iomem *psc;
39 struct mpc512x_psc_fifo __iomem *fifo;
40 unsigned int irq;
41 u8 bits_per_word;
Gerhard Sittiga81a5092013-08-06 22:43:41 +020042 struct clk *clk_mclk;
Gerhard Sittigdff148a2013-11-30 23:51:28 +010043 struct clk *clk_ipg;
Gerhard Sittiga81a5092013-08-06 22:43:41 +020044 u32 mclk_rate;
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +000045
Gerhard Sittigc36e93a2013-06-03 14:03:49 +020046 struct completion txisrdone;
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +000047};
48
49/* controller state */
50struct mpc512x_psc_spi_cs {
51 int bits_per_word;
52 int speed_hz;
53};
54
55/* set clock freq, clock ramp, bits per work
56 * if t is NULL then reset the values to the default values
57 */
58static int mpc512x_psc_spi_transfer_setup(struct spi_device *spi,
59 struct spi_transfer *t)
60{
61 struct mpc512x_psc_spi_cs *cs = spi->controller_state;
62
63 cs->speed_hz = (t && t->speed_hz)
64 ? t->speed_hz : spi->max_speed_hz;
65 cs->bits_per_word = (t && t->bits_per_word)
66 ? t->bits_per_word : spi->bits_per_word;
67 cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
68 return 0;
69}
70
71static void mpc512x_psc_spi_activate_cs(struct spi_device *spi)
72{
73 struct mpc512x_psc_spi_cs *cs = spi->controller_state;
74 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
75 struct mpc52xx_psc __iomem *psc = mps->psc;
76 u32 sicr;
77 u32 ccr;
Gerhard Sittiga81a5092013-08-06 22:43:41 +020078 int speed;
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +000079 u16 bclkdiv;
80
81 sicr = in_be32(&psc->sicr);
82
83 /* Set clock phase and polarity */
84 if (spi->mode & SPI_CPHA)
85 sicr |= 0x00001000;
86 else
87 sicr &= ~0x00001000;
88
89 if (spi->mode & SPI_CPOL)
90 sicr |= 0x00002000;
91 else
92 sicr &= ~0x00002000;
93
94 if (spi->mode & SPI_LSB_FIRST)
95 sicr |= 0x10000000;
96 else
97 sicr &= ~0x10000000;
98 out_be32(&psc->sicr, sicr);
99
100 ccr = in_be32(&psc->ccr);
101 ccr &= 0xFF000000;
Gerhard Sittiga81a5092013-08-06 22:43:41 +0200102 speed = cs->speed_hz;
103 if (!speed)
104 speed = 1000000; /* default 1MHz */
105 bclkdiv = (mps->mclk_rate / speed) - 1;
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000106
107 ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
108 out_be32(&psc->ccr, ccr);
109 mps->bits_per_word = cs->bits_per_word;
110
Anatolij Gustschin86e98742013-04-01 17:29:21 +0200111 if (mps->cs_control && gpio_is_valid(spi->cs_gpio))
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000112 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0);
113}
114
115static void mpc512x_psc_spi_deactivate_cs(struct spi_device *spi)
116{
117 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
118
Anatolij Gustschin86e98742013-04-01 17:29:21 +0200119 if (mps->cs_control && gpio_is_valid(spi->cs_gpio))
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000120 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
121
122}
123
124/* extract and scale size field in txsz or rxsz */
125#define MPC512x_PSC_FIFO_SZ(sz) ((sz & 0x7ff) << 2);
126
127#define EOFBYTE 1
128
129static int mpc512x_psc_spi_transfer_rxtx(struct spi_device *spi,
130 struct spi_transfer *t)
131{
132 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000133 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
Gerhard Sittigc36e93a2013-06-03 14:03:49 +0200134 size_t tx_len = t->len;
Gerhard Sittig5df24ea2013-06-03 14:03:50 +0200135 size_t rx_len = t->len;
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000136 u8 *tx_buf = (u8 *)t->tx_buf;
137 u8 *rx_buf = (u8 *)t->rx_buf;
138
139 if (!tx_buf && !rx_buf && t->len)
140 return -EINVAL;
141
Gerhard Sittig5df24ea2013-06-03 14:03:50 +0200142 while (rx_len || tx_len) {
Gerhard Sittigc36e93a2013-06-03 14:03:49 +0200143 size_t txcount;
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000144 u8 data;
145 size_t fifosz;
Gerhard Sittigc36e93a2013-06-03 14:03:49 +0200146 size_t rxcount;
Gerhard Sittig5df24ea2013-06-03 14:03:50 +0200147 int rxtries;
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000148
149 /*
Gerhard Sittig5df24ea2013-06-03 14:03:50 +0200150 * send the TX bytes in as large a chunk as possible
151 * but neither exceed the TX nor the RX FIFOs
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000152 */
153 fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->txsz));
Gerhard Sittigc36e93a2013-06-03 14:03:49 +0200154 txcount = min(fifosz, tx_len);
Gerhard Sittig5df24ea2013-06-03 14:03:50 +0200155 fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->rxsz));
156 fifosz -= in_be32(&fifo->rxcnt) + 1;
157 txcount = min(fifosz, txcount);
158 if (txcount) {
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000159
Gerhard Sittig5df24ea2013-06-03 14:03:50 +0200160 /* fill the TX FIFO */
161 while (txcount-- > 0) {
162 data = tx_buf ? *tx_buf++ : 0;
163 if (tx_len == EOFBYTE && t->cs_change)
164 setbits32(&fifo->txcmd,
165 MPC512x_PSC_FIFO_EOF);
166 out_8(&fifo->txdata_8, data);
167 tx_len--;
168 }
169
170 /* have the ISR trigger when the TX FIFO is empty */
Wolfram Sang16735d02013-11-14 14:32:02 -0800171 reinit_completion(&mps->txisrdone);
Gerhard Sittig5df24ea2013-06-03 14:03:50 +0200172 out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
173 out_be32(&fifo->tximr, MPC512x_PSC_FIFO_EMPTY);
174 wait_for_completion(&mps->txisrdone);
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000175 }
176
Gerhard Sittig5df24ea2013-06-03 14:03:50 +0200177 /*
178 * consume as much RX data as the FIFO holds, while we
179 * iterate over the transfer's TX data length
180 *
181 * only insist in draining all the remaining RX bytes
182 * when the TX bytes were exhausted (that's at the very
183 * end of this transfer, not when still iterating over
184 * the transfer's chunks)
185 */
186 rxtries = 50;
187 do {
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000188
Gerhard Sittig5df24ea2013-06-03 14:03:50 +0200189 /*
190 * grab whatever was in the FIFO when we started
191 * looking, don't bother fetching what was added to
192 * the FIFO while we read from it -- we'll return
193 * here eventually and prefer sending out remaining
194 * TX data
195 */
196 fifosz = in_be32(&fifo->rxcnt);
197 rxcount = min(fifosz, rx_len);
198 while (rxcount-- > 0) {
199 data = in_8(&fifo->rxdata_8);
200 if (rx_buf)
201 *rx_buf++ = data;
202 rx_len--;
203 }
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000204
Gerhard Sittig5df24ea2013-06-03 14:03:50 +0200205 /*
206 * come back later if there still is TX data to send,
207 * bail out of the RX drain loop if all of the TX data
208 * was sent and all of the RX data was received (i.e.
209 * when the transmission has completed)
210 */
211 if (tx_len)
212 break;
213 if (!rx_len)
214 break;
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000215
Gerhard Sittig5df24ea2013-06-03 14:03:50 +0200216 /*
217 * TX data transmission has completed while RX data
218 * is still pending -- that's a transient situation
219 * which depends on wire speed and specific
220 * hardware implementation details (buffering) yet
221 * should resolve very quickly
222 *
223 * just yield for a moment to not hog the CPU for
224 * too long when running SPI at low speed
225 *
226 * the timeout range is rather arbitrary and tries
227 * to balance throughput against system load; the
228 * chosen values result in a minimal timeout of 50
229 * times 10us and thus work at speeds as low as
230 * some 20kbps, while the maximum timeout at the
231 * transfer's end could be 5ms _if_ nothing else
232 * ticks in the system _and_ RX data still wasn't
233 * received, which only occurs in situations that
234 * are exceptional; removing the unpredictability
235 * of the timeout either decreases throughput
236 * (longer timeouts), or puts more load on the
237 * system (fixed short timeouts) or requires the
238 * use of a timeout API instead of a counter and an
239 * unknown inner delay
240 */
241 usleep_range(10, 100);
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000242
Gerhard Sittig5df24ea2013-06-03 14:03:50 +0200243 } while (--rxtries > 0);
244 if (!tx_len && rx_len && !rxtries) {
245 /*
246 * not enough RX bytes even after several retries
247 * and the resulting rather long timeout?
248 */
249 rxcount = in_be32(&fifo->rxcnt);
250 dev_warn(&spi->dev,
251 "short xfer, missing %zd RX bytes, FIFO level %zd\n",
252 rx_len, rxcount);
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000253 }
254
Gerhard Sittig5df24ea2013-06-03 14:03:50 +0200255 /*
256 * drain and drop RX data which "should not be there" in
257 * the first place, for undisturbed transmission this turns
258 * into a NOP (except for the FIFO level fetch)
259 */
260 if (!tx_len && !rx_len) {
261 while (in_be32(&fifo->rxcnt))
262 in_8(&fifo->rxdata_8);
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000263 }
Gerhard Sittig5df24ea2013-06-03 14:03:50 +0200264
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000265 }
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000266 return 0;
267}
268
Gerhard Sittig85085892013-06-03 14:03:51 +0200269static int mpc512x_psc_spi_msg_xfer(struct spi_master *master,
270 struct spi_message *m)
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000271{
Gerhard Sittig85085892013-06-03 14:03:51 +0200272 struct spi_device *spi;
273 unsigned cs_change;
274 int status;
275 struct spi_transfer *t;
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000276
Gerhard Sittig85085892013-06-03 14:03:51 +0200277 spi = m->spi;
278 cs_change = 1;
279 status = 0;
280 list_for_each_entry(t, &m->transfers, transfer_list) {
281 if (t->bits_per_word || t->speed_hz) {
282 status = mpc512x_psc_spi_transfer_setup(spi, t);
283 if (status < 0)
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000284 break;
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000285 }
286
Gerhard Sittig85085892013-06-03 14:03:51 +0200287 if (cs_change)
288 mpc512x_psc_spi_activate_cs(spi);
289 cs_change = t->cs_change;
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000290
Gerhard Sittig85085892013-06-03 14:03:51 +0200291 status = mpc512x_psc_spi_transfer_rxtx(spi, t);
292 if (status)
293 break;
294 m->actual_length += t->len;
295
296 if (t->delay_usecs)
297 udelay(t->delay_usecs);
298
299 if (cs_change)
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000300 mpc512x_psc_spi_deactivate_cs(spi);
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000301 }
Gerhard Sittig85085892013-06-03 14:03:51 +0200302
303 m->status = status;
304 m->complete(m->context);
305
306 if (status || !cs_change)
307 mpc512x_psc_spi_deactivate_cs(spi);
308
309 mpc512x_psc_spi_transfer_setup(spi, NULL);
310
311 spi_finalize_current_message(master);
312 return status;
313}
314
315static int mpc512x_psc_spi_prep_xfer_hw(struct spi_master *master)
316{
317 struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
318 struct mpc52xx_psc __iomem *psc = mps->psc;
319
320 dev_dbg(&master->dev, "%s()\n", __func__);
321
322 /* Zero MR2 */
323 in_8(&psc->mode);
324 out_8(&psc->mode, 0x0);
325
326 /* enable transmitter/receiver */
327 out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
328
329 return 0;
330}
331
332static int mpc512x_psc_spi_unprep_xfer_hw(struct spi_master *master)
333{
334 struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
335 struct mpc52xx_psc __iomem *psc = mps->psc;
336 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
337
338 dev_dbg(&master->dev, "%s()\n", __func__);
339
340 /* disable transmitter/receiver and fifo interrupt */
341 out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
342 out_be32(&fifo->tximr, 0);
343
344 return 0;
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000345}
346
347static int mpc512x_psc_spi_setup(struct spi_device *spi)
348{
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000349 struct mpc512x_psc_spi_cs *cs = spi->controller_state;
Anatolij Gustschin86e98742013-04-01 17:29:21 +0200350 int ret;
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000351
352 if (spi->bits_per_word % 8)
353 return -EINVAL;
354
355 if (!cs) {
356 cs = kzalloc(sizeof *cs, GFP_KERNEL);
357 if (!cs)
358 return -ENOMEM;
Anatolij Gustschin86e98742013-04-01 17:29:21 +0200359
360 if (gpio_is_valid(spi->cs_gpio)) {
361 ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev));
362 if (ret) {
363 dev_err(&spi->dev, "can't get CS gpio: %d\n",
364 ret);
365 kfree(cs);
366 return ret;
367 }
368 gpio_direction_output(spi->cs_gpio,
369 spi->mode & SPI_CS_HIGH ? 0 : 1);
370 }
371
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000372 spi->controller_state = cs;
373 }
374
375 cs->bits_per_word = spi->bits_per_word;
376 cs->speed_hz = spi->max_speed_hz;
377
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000378 return 0;
379}
380
381static void mpc512x_psc_spi_cleanup(struct spi_device *spi)
382{
Anatolij Gustschin86e98742013-04-01 17:29:21 +0200383 if (gpio_is_valid(spi->cs_gpio))
384 gpio_free(spi->cs_gpio);
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000385 kfree(spi->controller_state);
386}
387
388static int mpc512x_psc_spi_port_config(struct spi_master *master,
389 struct mpc512x_psc_spi *mps)
390{
391 struct mpc52xx_psc __iomem *psc = mps->psc;
392 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000393 u32 sicr;
394 u32 ccr;
Gerhard Sittiga81a5092013-08-06 22:43:41 +0200395 int speed;
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000396 u16 bclkdiv;
397
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000398 /* Reset the PSC into a known state */
399 out_8(&psc->command, MPC52xx_PSC_RST_RX);
400 out_8(&psc->command, MPC52xx_PSC_RST_TX);
401 out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
402
403 /* Disable psc interrupts all useful interrupts are in fifo */
404 out_be16(&psc->isr_imr.imr, 0);
405
406 /* Disable fifo interrupts, will be enabled later */
407 out_be32(&fifo->tximr, 0);
408 out_be32(&fifo->rximr, 0);
409
410 /* Setup fifo slice address and size */
411 /*out_be32(&fifo->txsz, 0x0fe00004);*/
412 /*out_be32(&fifo->rxsz, 0x0ff00004);*/
413
414 sicr = 0x01000000 | /* SIM = 0001 -- 8 bit */
415 0x00800000 | /* GenClk = 1 -- internal clk */
416 0x00008000 | /* SPI = 1 */
417 0x00004000 | /* MSTR = 1 -- SPI master */
418 0x00000800; /* UseEOF = 1 -- SS low until EOF */
419
420 out_be32(&psc->sicr, sicr);
421
422 ccr = in_be32(&psc->ccr);
423 ccr &= 0xFF000000;
Gerhard Sittiga81a5092013-08-06 22:43:41 +0200424 speed = 1000000; /* default 1MHz */
425 bclkdiv = (mps->mclk_rate / speed) - 1;
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000426 ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
427 out_be32(&psc->ccr, ccr);
428
429 /* Set 2ms DTL delay */
430 out_8(&psc->ctur, 0x00);
431 out_8(&psc->ctlr, 0x82);
432
433 /* we don't use the alarms */
434 out_be32(&fifo->rxalarm, 0xfff);
435 out_be32(&fifo->txalarm, 0);
436
437 /* Enable FIFO slices for Rx/Tx */
438 out_be32(&fifo->rxcmd,
439 MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
440 out_be32(&fifo->txcmd,
441 MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
442
443 mps->bits_per_word = 8;
444
Gerhard Sittiga81a5092013-08-06 22:43:41 +0200445 return 0;
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000446}
447
448static irqreturn_t mpc512x_psc_spi_isr(int irq, void *dev_id)
449{
450 struct mpc512x_psc_spi *mps = (struct mpc512x_psc_spi *)dev_id;
451 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
452
Gerhard Sittig85085892013-06-03 14:03:51 +0200453 /* clear interrupt and wake up the rx/tx routine */
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000454 if (in_be32(&fifo->txisr) &
455 in_be32(&fifo->tximr) & MPC512x_PSC_FIFO_EMPTY) {
456 out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
457 out_be32(&fifo->tximr, 0);
Gerhard Sittigc36e93a2013-06-03 14:03:49 +0200458 complete(&mps->txisrdone);
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000459 return IRQ_HANDLED;
460 }
461 return IRQ_NONE;
462}
463
Anatolij Gustschin86e98742013-04-01 17:29:21 +0200464static void mpc512x_spi_cs_control(struct spi_device *spi, bool onoff)
465{
466 gpio_set_value(spi->cs_gpio, onoff);
467}
468
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000469/* bus_num is used only for the case dev->platform_data == NULL */
Grant Likelyfd4a3192012-12-07 16:57:14 +0000470static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
Anatolij Gustschincf40f082010-07-05 12:17:51 +0200471 u32 size, unsigned int irq,
472 s16 bus_num)
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000473{
Jingoo Han8074cf02013-07-30 16:58:59 +0900474 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000475 struct mpc512x_psc_spi *mps;
476 struct spi_master *master;
477 int ret;
478 void *tempp;
Gerhard Sittiga81a5092013-08-06 22:43:41 +0200479 struct clk *clk;
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000480
481 master = spi_alloc_master(dev, sizeof *mps);
482 if (master == NULL)
483 return -ENOMEM;
484
485 dev_set_drvdata(dev, master);
486 mps = spi_master_get_devdata(master);
487 mps->irq = irq;
488
489 if (pdata == NULL) {
Anatolij Gustschin86e98742013-04-01 17:29:21 +0200490 mps->cs_control = mpc512x_spi_cs_control;
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000491 master->bus_num = bus_num;
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000492 } else {
493 mps->cs_control = pdata->cs_control;
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000494 master->bus_num = pdata->bus_num;
495 master->num_chipselect = pdata->max_chipselect;
496 }
497
Anatolij Gustschinc88dd342013-01-14 21:27:00 +0100498 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000499 master->setup = mpc512x_psc_spi_setup;
Gerhard Sittig85085892013-06-03 14:03:51 +0200500 master->prepare_transfer_hardware = mpc512x_psc_spi_prep_xfer_hw;
501 master->transfer_one_message = mpc512x_psc_spi_msg_xfer;
502 master->unprepare_transfer_hardware = mpc512x_psc_spi_unprep_xfer_hw;
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000503 master->cleanup = mpc512x_psc_spi_cleanup;
Anatolij Gustschin12b15e82010-07-27 22:35:58 +0200504 master->dev.of_node = dev->of_node;
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000505
Jingoo Hane1d0cd42013-12-18 10:31:15 +0900506 tempp = devm_ioremap(dev, regaddr, size);
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000507 if (!tempp) {
508 dev_err(dev, "could not ioremap I/O port range\n");
509 ret = -EFAULT;
510 goto free_master;
511 }
512 mps->psc = tempp;
513 mps->fifo =
514 (struct mpc512x_psc_fifo *)(tempp + sizeof(struct mpc52xx_psc));
Jingoo Hane1d0cd42013-12-18 10:31:15 +0900515 ret = devm_request_irq(dev, mps->irq, mpc512x_psc_spi_isr, IRQF_SHARED,
516 "mpc512x-psc-spi", mps);
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000517 if (ret)
518 goto free_master;
Gerhard Sittig85085892013-06-03 14:03:51 +0200519 init_completion(&mps->txisrdone);
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000520
Gerhard Sittigdff148a2013-11-30 23:51:28 +0100521 clk = devm_clk_get(dev, "mclk");
Wei Yongjuneadf69c2013-09-11 19:15:39 +0800522 if (IS_ERR(clk)) {
523 ret = PTR_ERR(clk);
Jingoo Hane1d0cd42013-12-18 10:31:15 +0900524 goto free_master;
Wei Yongjuneadf69c2013-09-11 19:15:39 +0800525 }
Gerhard Sittiga81a5092013-08-06 22:43:41 +0200526 ret = clk_prepare_enable(clk);
527 if (ret)
Jingoo Hane1d0cd42013-12-18 10:31:15 +0900528 goto free_master;
Gerhard Sittiga81a5092013-08-06 22:43:41 +0200529 mps->clk_mclk = clk;
530 mps->mclk_rate = clk_get_rate(clk);
531
Gerhard Sittigdff148a2013-11-30 23:51:28 +0100532 clk = devm_clk_get(dev, "ipg");
533 if (IS_ERR(clk)) {
534 ret = PTR_ERR(clk);
535 goto free_mclk_clock;
536 }
537 ret = clk_prepare_enable(clk);
538 if (ret)
539 goto free_mclk_clock;
540 mps->clk_ipg = clk;
541
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000542 ret = mpc512x_psc_spi_port_config(master, mps);
543 if (ret < 0)
Gerhard Sittigdff148a2013-11-30 23:51:28 +0100544 goto free_ipg_clock;
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000545
Jingoo Haneaa24292013-09-24 13:31:50 +0900546 ret = devm_spi_register_master(dev, master);
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000547 if (ret < 0)
Gerhard Sittigdff148a2013-11-30 23:51:28 +0100548 goto free_ipg_clock;
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000549
550 return ret;
551
Gerhard Sittigdff148a2013-11-30 23:51:28 +0100552free_ipg_clock:
553 clk_disable_unprepare(mps->clk_ipg);
554free_mclk_clock:
Gerhard Sittiga81a5092013-08-06 22:43:41 +0200555 clk_disable_unprepare(mps->clk_mclk);
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000556free_master:
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000557 spi_master_put(master);
558
559 return ret;
560}
561
Grant Likelyfd4a3192012-12-07 16:57:14 +0000562static int mpc512x_psc_spi_do_remove(struct device *dev)
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000563{
Wei Yongjuna4469a42013-11-15 15:48:56 +0800564 struct spi_master *master = dev_get_drvdata(dev);
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000565 struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
566
Gerhard Sittiga81a5092013-08-06 22:43:41 +0200567 clk_disable_unprepare(mps->clk_mclk);
Gerhard Sittigdff148a2013-11-30 23:51:28 +0100568 clk_disable_unprepare(mps->clk_ipg);
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000569
570 return 0;
571}
572
Grant Likelyfd4a3192012-12-07 16:57:14 +0000573static int mpc512x_psc_spi_of_probe(struct platform_device *op)
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000574{
575 const u32 *regaddr_p;
576 u64 regaddr64, size64;
577 s16 id = -1;
578
Anatolij Gustschinef7f2e82010-05-31 18:34:54 +0200579 regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL);
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000580 if (!regaddr_p) {
581 dev_err(&op->dev, "Invalid PSC address\n");
582 return -EINVAL;
583 }
Anatolij Gustschinef7f2e82010-05-31 18:34:54 +0200584 regaddr64 = of_translate_address(op->dev.of_node, regaddr_p);
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000585
586 /* get PSC id (0..11, used by port_config) */
Anatolij Gustschin9d15a3b2013-01-11 01:05:48 +0100587 id = of_alias_get_id(op->dev.of_node, "spi");
588 if (id < 0) {
589 dev_err(&op->dev, "no alias id for %s\n",
590 op->dev.of_node->full_name);
591 return id;
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000592 }
593
594 return mpc512x_psc_spi_do_probe(&op->dev, (u32) regaddr64, (u32) size64,
Anatolij Gustschinef7f2e82010-05-31 18:34:54 +0200595 irq_of_parse_and_map(op->dev.of_node, 0), id);
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000596}
597
Grant Likelyfd4a3192012-12-07 16:57:14 +0000598static int mpc512x_psc_spi_of_remove(struct platform_device *op)
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000599{
600 return mpc512x_psc_spi_do_remove(&op->dev);
601}
602
603static struct of_device_id mpc512x_psc_spi_of_match[] = {
604 { .compatible = "fsl,mpc5121-psc-spi", },
605 {},
606};
607
608MODULE_DEVICE_TABLE(of, mpc512x_psc_spi_of_match);
609
Grant Likely18d306d2011-02-22 21:02:43 -0700610static struct platform_driver mpc512x_psc_spi_of_driver = {
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000611 .probe = mpc512x_psc_spi_of_probe,
Grant Likelyfd4a3192012-12-07 16:57:14 +0000612 .remove = mpc512x_psc_spi_of_remove,
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000613 .driver = {
614 .name = "mpc512x-psc-spi",
615 .owner = THIS_MODULE,
Anatolij Gustschinef7f2e82010-05-31 18:34:54 +0200616 .of_match_table = mpc512x_psc_spi_of_match,
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000617 },
618};
Grant Likely940ab882011-10-05 11:29:49 -0600619module_platform_driver(mpc512x_psc_spi_of_driver);
Anatolij Gustschin6e27388f1b2010-04-30 13:21:27 +0000620
621MODULE_AUTHOR("John Rigby");
622MODULE_DESCRIPTION("MPC512x PSC SPI Driver");
623MODULE_LICENSE("GPL");