Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Freescale Semiconductor, Inc. |
| 3 | * |
Viresh Kumar | 748c876 | 2014-08-28 11:22:24 +0530 | [diff] [blame] | 4 | * Copyright (C) 2014 Linaro. |
| 5 | * Viresh Kumar <viresh.kumar@linaro.org> |
| 6 | * |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 7 | * The OPP code in function set_target() is reused from |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 8 | * drivers/cpufreq/omap-cpufreq.c |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. |
| 13 | */ |
| 14 | |
| 15 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 16 | |
| 17 | #include <linux/clk.h> |
Sudeep KarkadaNagesha | e1825b2 | 2013-09-10 18:59:46 +0100 | [diff] [blame] | 18 | #include <linux/cpu.h> |
Eduardo Valentin | 77cff59 | 2013-07-15 09:09:14 -0400 | [diff] [blame] | 19 | #include <linux/cpu_cooling.h> |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 20 | #include <linux/cpufreq.h> |
Eduardo Valentin | 77cff59 | 2013-07-15 09:09:14 -0400 | [diff] [blame] | 21 | #include <linux/cpumask.h> |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 22 | #include <linux/err.h> |
| 23 | #include <linux/module.h> |
| 24 | #include <linux/of.h> |
Nishanth Menon | e4db1c7 | 2013-09-19 16:03:52 -0500 | [diff] [blame] | 25 | #include <linux/pm_opp.h> |
Shawn Guo | 5553f9e | 2013-01-30 14:27:49 +0000 | [diff] [blame] | 26 | #include <linux/platform_device.h> |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 27 | #include <linux/regulator/consumer.h> |
| 28 | #include <linux/slab.h> |
Eduardo Valentin | 77cff59 | 2013-07-15 09:09:14 -0400 | [diff] [blame] | 29 | #include <linux/thermal.h> |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 30 | |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 31 | struct private_data { |
| 32 | struct device *cpu_dev; |
| 33 | struct regulator *cpu_reg; |
| 34 | struct thermal_cooling_device *cdev; |
| 35 | unsigned int voltage_tolerance; /* in percentage */ |
| 36 | }; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 37 | |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 38 | static int set_target(struct cpufreq_policy *policy, unsigned int index) |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 39 | { |
Nishanth Menon | 47d43ba | 2013-09-19 16:03:51 -0500 | [diff] [blame] | 40 | struct dev_pm_opp *opp; |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 41 | struct cpufreq_frequency_table *freq_table = policy->freq_table; |
| 42 | struct clk *cpu_clk = policy->clk; |
| 43 | struct private_data *priv = policy->driver_data; |
| 44 | struct device *cpu_dev = priv->cpu_dev; |
| 45 | struct regulator *cpu_reg = priv->cpu_reg; |
jhbird.choi@samsung.com | 5df6055 | 2013-03-18 08:09:42 +0000 | [diff] [blame] | 46 | unsigned long volt = 0, volt_old = 0, tol = 0; |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 47 | unsigned int old_freq, new_freq; |
Guennadi Liakhovetski | 0ca6843 | 2013-02-25 18:22:37 +0100 | [diff] [blame] | 48 | long freq_Hz, freq_exact; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 49 | int ret; |
| 50 | |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 51 | freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000); |
Paul Walmsley | 2209b0c | 2013-11-25 18:01:18 -0800 | [diff] [blame] | 52 | if (freq_Hz <= 0) |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 53 | freq_Hz = freq_table[index].frequency * 1000; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 54 | |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 55 | freq_exact = freq_Hz; |
| 56 | new_freq = freq_Hz / 1000; |
| 57 | old_freq = clk_get_rate(cpu_clk) / 1000; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 58 | |
Mark Brown | 4a511de | 2013-08-13 14:58:24 +0200 | [diff] [blame] | 59 | if (!IS_ERR(cpu_reg)) { |
Nishanth Menon | 78e8eb8 | 2013-01-18 19:52:33 +0000 | [diff] [blame] | 60 | rcu_read_lock(); |
Nishanth Menon | 5d4879c | 2013-09-19 16:03:50 -0500 | [diff] [blame] | 61 | opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 62 | if (IS_ERR(opp)) { |
Nishanth Menon | 78e8eb8 | 2013-01-18 19:52:33 +0000 | [diff] [blame] | 63 | rcu_read_unlock(); |
Viresh Kumar | fbd48ca | 2014-08-28 11:22:27 +0530 | [diff] [blame] | 64 | dev_err(cpu_dev, "failed to find OPP for %ld\n", |
| 65 | freq_Hz); |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 66 | return PTR_ERR(opp); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 67 | } |
Nishanth Menon | 5d4879c | 2013-09-19 16:03:50 -0500 | [diff] [blame] | 68 | volt = dev_pm_opp_get_voltage(opp); |
Nishanth Menon | 78e8eb8 | 2013-01-18 19:52:33 +0000 | [diff] [blame] | 69 | rcu_read_unlock(); |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 70 | tol = volt * priv->voltage_tolerance / 100; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 71 | volt_old = regulator_get_voltage(cpu_reg); |
| 72 | } |
| 73 | |
Viresh Kumar | fbd48ca | 2014-08-28 11:22:27 +0530 | [diff] [blame] | 74 | dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", |
| 75 | old_freq / 1000, volt_old ? volt_old / 1000 : -1, |
| 76 | new_freq / 1000, volt ? volt / 1000 : -1); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 77 | |
| 78 | /* scaling up? scale voltage before frequency */ |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 79 | if (!IS_ERR(cpu_reg) && new_freq > old_freq) { |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 80 | ret = regulator_set_voltage_tol(cpu_reg, volt, tol); |
| 81 | if (ret) { |
Viresh Kumar | fbd48ca | 2014-08-28 11:22:27 +0530 | [diff] [blame] | 82 | dev_err(cpu_dev, "failed to scale voltage up: %d\n", |
| 83 | ret); |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 84 | return ret; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 85 | } |
| 86 | } |
| 87 | |
Guennadi Liakhovetski | 0ca6843 | 2013-02-25 18:22:37 +0100 | [diff] [blame] | 88 | ret = clk_set_rate(cpu_clk, freq_exact); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 89 | if (ret) { |
Viresh Kumar | fbd48ca | 2014-08-28 11:22:27 +0530 | [diff] [blame] | 90 | dev_err(cpu_dev, "failed to set clock rate: %d\n", ret); |
Mark Brown | 4a511de | 2013-08-13 14:58:24 +0200 | [diff] [blame] | 91 | if (!IS_ERR(cpu_reg)) |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 92 | regulator_set_voltage_tol(cpu_reg, volt_old, tol); |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 93 | return ret; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 94 | } |
| 95 | |
| 96 | /* scaling down? scale voltage after frequency */ |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 97 | if (!IS_ERR(cpu_reg) && new_freq < old_freq) { |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 98 | ret = regulator_set_voltage_tol(cpu_reg, volt, tol); |
| 99 | if (ret) { |
Viresh Kumar | fbd48ca | 2014-08-28 11:22:27 +0530 | [diff] [blame] | 100 | dev_err(cpu_dev, "failed to scale voltage down: %d\n", |
| 101 | ret); |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 102 | clk_set_rate(cpu_clk, old_freq * 1000); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 103 | } |
| 104 | } |
| 105 | |
Viresh Kumar | fd143b4 | 2013-04-01 12:57:44 +0000 | [diff] [blame] | 106 | return ret; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 107 | } |
| 108 | |
Viresh Kumar | 95b6105 | 2014-08-28 11:22:30 +0530 | [diff] [blame] | 109 | static int allocate_resources(int cpu, struct device **cdev, |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 110 | struct regulator **creg, struct clk **cclk) |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 111 | { |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 112 | struct device *cpu_dev; |
| 113 | struct regulator *cpu_reg; |
| 114 | struct clk *cpu_clk; |
| 115 | int ret = 0; |
Viresh Kumar | 2d2c5e0 | 2014-08-28 11:22:29 +0530 | [diff] [blame] | 116 | char *reg_cpu0 = "cpu0", *reg_cpu = "cpu", *reg; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 117 | |
Viresh Kumar | 95b6105 | 2014-08-28 11:22:30 +0530 | [diff] [blame] | 118 | cpu_dev = get_cpu_device(cpu); |
Sudeep KarkadaNagesha | e1825b2 | 2013-09-10 18:59:46 +0100 | [diff] [blame] | 119 | if (!cpu_dev) { |
Viresh Kumar | 95b6105 | 2014-08-28 11:22:30 +0530 | [diff] [blame] | 120 | pr_err("failed to get cpu%d device\n", cpu); |
Sudeep KarkadaNagesha | e1825b2 | 2013-09-10 18:59:46 +0100 | [diff] [blame] | 121 | return -ENODEV; |
| 122 | } |
Paolo Pisati | f5c3ef2 | 2013-03-28 09:24:29 +0000 | [diff] [blame] | 123 | |
Viresh Kumar | 2d2c5e0 | 2014-08-28 11:22:29 +0530 | [diff] [blame] | 124 | /* Try "cpu0" for older DTs */ |
Viresh Kumar | 95b6105 | 2014-08-28 11:22:30 +0530 | [diff] [blame] | 125 | if (!cpu) |
| 126 | reg = reg_cpu0; |
| 127 | else |
| 128 | reg = reg_cpu; |
Viresh Kumar | 2d2c5e0 | 2014-08-28 11:22:29 +0530 | [diff] [blame] | 129 | |
| 130 | try_again: |
| 131 | cpu_reg = regulator_get_optional(cpu_dev, reg); |
Nishanth Menon | fc31d6f | 2013-05-01 13:38:12 +0000 | [diff] [blame] | 132 | if (IS_ERR(cpu_reg)) { |
| 133 | /* |
Viresh Kumar | 95b6105 | 2014-08-28 11:22:30 +0530 | [diff] [blame] | 134 | * If cpu's regulator supply node is present, but regulator is |
Nishanth Menon | fc31d6f | 2013-05-01 13:38:12 +0000 | [diff] [blame] | 135 | * not yet registered, we should try defering probe. |
| 136 | */ |
| 137 | if (PTR_ERR(cpu_reg) == -EPROBE_DEFER) { |
Viresh Kumar | 95b6105 | 2014-08-28 11:22:30 +0530 | [diff] [blame] | 138 | dev_dbg(cpu_dev, "cpu%d regulator not ready, retry\n", |
| 139 | cpu); |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 140 | return -EPROBE_DEFER; |
Nishanth Menon | fc31d6f | 2013-05-01 13:38:12 +0000 | [diff] [blame] | 141 | } |
Viresh Kumar | 2d2c5e0 | 2014-08-28 11:22:29 +0530 | [diff] [blame] | 142 | |
| 143 | /* Try with "cpu-supply" */ |
| 144 | if (reg == reg_cpu0) { |
| 145 | reg = reg_cpu; |
| 146 | goto try_again; |
| 147 | } |
| 148 | |
Viresh Kumar | 95b6105 | 2014-08-28 11:22:30 +0530 | [diff] [blame] | 149 | dev_warn(cpu_dev, "failed to get cpu%d regulator: %ld\n", |
| 150 | cpu, PTR_ERR(cpu_reg)); |
Nishanth Menon | fc31d6f | 2013-05-01 13:38:12 +0000 | [diff] [blame] | 151 | } |
| 152 | |
Lucas Stach | e3beb0a | 2014-05-16 12:20:42 +0200 | [diff] [blame] | 153 | cpu_clk = clk_get(cpu_dev, NULL); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 154 | if (IS_ERR(cpu_clk)) { |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 155 | /* put regulator */ |
| 156 | if (!IS_ERR(cpu_reg)) |
| 157 | regulator_put(cpu_reg); |
| 158 | |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 159 | ret = PTR_ERR(cpu_clk); |
Viresh Kumar | 48a8624 | 2014-08-28 11:22:26 +0530 | [diff] [blame] | 160 | |
| 161 | /* |
| 162 | * If cpu's clk node is present, but clock is not yet |
| 163 | * registered, we should try defering probe. |
| 164 | */ |
| 165 | if (ret == -EPROBE_DEFER) |
Viresh Kumar | 95b6105 | 2014-08-28 11:22:30 +0530 | [diff] [blame] | 166 | dev_dbg(cpu_dev, "cpu%d clock not ready, retry\n", cpu); |
Viresh Kumar | 48a8624 | 2014-08-28 11:22:26 +0530 | [diff] [blame] | 167 | else |
Viresh Kumar | 95b6105 | 2014-08-28 11:22:30 +0530 | [diff] [blame] | 168 | dev_err(cpu_dev, "failed to get cpu%d clock: %d\n", ret, |
| 169 | cpu); |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 170 | } else { |
| 171 | *cdev = cpu_dev; |
| 172 | *creg = cpu_reg; |
| 173 | *cclk = cpu_clk; |
| 174 | } |
Viresh Kumar | 48a8624 | 2014-08-28 11:22:26 +0530 | [diff] [blame] | 175 | |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 176 | return ret; |
| 177 | } |
| 178 | |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 179 | static int cpufreq_init(struct cpufreq_policy *policy) |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 180 | { |
| 181 | struct cpufreq_frequency_table *freq_table; |
| 182 | struct thermal_cooling_device *cdev; |
| 183 | struct device_node *np; |
| 184 | struct private_data *priv; |
| 185 | struct device *cpu_dev; |
| 186 | struct regulator *cpu_reg; |
| 187 | struct clk *cpu_clk; |
| 188 | unsigned int transition_latency; |
| 189 | int ret; |
| 190 | |
Viresh Kumar | 95b6105 | 2014-08-28 11:22:30 +0530 | [diff] [blame] | 191 | ret = allocate_resources(policy->cpu, &cpu_dev, &cpu_reg, &cpu_clk); |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 192 | if (ret) { |
| 193 | pr_err("%s: Failed to allocate resources\n: %d", __func__, ret); |
| 194 | return ret; |
| 195 | } |
| 196 | |
| 197 | np = of_node_get(cpu_dev->of_node); |
| 198 | if (!np) { |
| 199 | dev_err(cpu_dev, "failed to find cpu%d node\n", policy->cpu); |
| 200 | ret = -ENOENT; |
| 201 | goto out_put_reg_clk; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 202 | } |
| 203 | |
Viresh Kumar | 1bf8cc3 | 2014-07-11 20:24:19 +0530 | [diff] [blame] | 204 | /* OPPs might be populated at runtime, don't check for error here */ |
| 205 | of_init_opp_table(cpu_dev); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 206 | |
Nishanth Menon | 5d4879c | 2013-09-19 16:03:50 -0500 | [diff] [blame] | 207 | ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 208 | if (ret) { |
Viresh Kumar | fbd48ca | 2014-08-28 11:22:27 +0530 | [diff] [blame] | 209 | dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret); |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 210 | goto out_put_node; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 211 | } |
| 212 | |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 213 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
| 214 | if (!priv) { |
| 215 | ret = -ENOMEM; |
| 216 | goto out_free_table; |
| 217 | } |
| 218 | |
| 219 | of_property_read_u32(np, "voltage-tolerance", &priv->voltage_tolerance); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 220 | |
| 221 | if (of_property_read_u32(np, "clock-latency", &transition_latency)) |
| 222 | transition_latency = CPUFREQ_ETERNAL; |
| 223 | |
Philipp Zabel | 43c638e | 2013-09-26 11:19:37 +0200 | [diff] [blame] | 224 | if (!IS_ERR(cpu_reg)) { |
Nishanth Menon | 47d43ba | 2013-09-19 16:03:51 -0500 | [diff] [blame] | 225 | struct dev_pm_opp *opp; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 226 | unsigned long min_uV, max_uV; |
| 227 | int i; |
| 228 | |
| 229 | /* |
| 230 | * OPP is maintained in order of increasing frequency, and |
| 231 | * freq_table initialised from OPP is therefore sorted in the |
| 232 | * same order. |
| 233 | */ |
| 234 | for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) |
| 235 | ; |
Nishanth Menon | 78e8eb8 | 2013-01-18 19:52:33 +0000 | [diff] [blame] | 236 | rcu_read_lock(); |
Nishanth Menon | 5d4879c | 2013-09-19 16:03:50 -0500 | [diff] [blame] | 237 | opp = dev_pm_opp_find_freq_exact(cpu_dev, |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 238 | freq_table[0].frequency * 1000, true); |
Nishanth Menon | 5d4879c | 2013-09-19 16:03:50 -0500 | [diff] [blame] | 239 | min_uV = dev_pm_opp_get_voltage(opp); |
| 240 | opp = dev_pm_opp_find_freq_exact(cpu_dev, |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 241 | freq_table[i-1].frequency * 1000, true); |
Nishanth Menon | 5d4879c | 2013-09-19 16:03:50 -0500 | [diff] [blame] | 242 | max_uV = dev_pm_opp_get_voltage(opp); |
Nishanth Menon | 78e8eb8 | 2013-01-18 19:52:33 +0000 | [diff] [blame] | 243 | rcu_read_unlock(); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 244 | ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV); |
| 245 | if (ret > 0) |
| 246 | transition_latency += ret * 1000; |
| 247 | } |
| 248 | |
Eduardo Valentin | 77cff59 | 2013-07-15 09:09:14 -0400 | [diff] [blame] | 249 | /* |
| 250 | * For now, just loading the cooling device; |
| 251 | * thermal DT code takes care of matching them. |
| 252 | */ |
| 253 | if (of_find_property(np, "#cooling-cells", NULL)) { |
| 254 | cdev = of_cpufreq_cooling_register(np, cpu_present_mask); |
| 255 | if (IS_ERR(cdev)) |
Viresh Kumar | fbd48ca | 2014-08-28 11:22:27 +0530 | [diff] [blame] | 256 | dev_err(cpu_dev, |
| 257 | "running cpufreq without cooling device: %ld\n", |
| 258 | PTR_ERR(cdev)); |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 259 | else |
| 260 | priv->cdev = cdev; |
Eduardo Valentin | 77cff59 | 2013-07-15 09:09:14 -0400 | [diff] [blame] | 261 | } |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 262 | |
| 263 | priv->cpu_dev = cpu_dev; |
| 264 | priv->cpu_reg = cpu_reg; |
| 265 | policy->driver_data = priv; |
| 266 | |
| 267 | policy->clk = cpu_clk; |
| 268 | ret = cpufreq_generic_init(policy, freq_table, transition_latency); |
| 269 | if (ret) |
| 270 | goto out_cooling_unregister; |
| 271 | |
Lucas Stach | f9739d2 | 2014-09-26 15:33:46 +0200 | [diff] [blame] | 272 | of_node_put(np); |
| 273 | |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 274 | return 0; |
| 275 | |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 276 | out_cooling_unregister: |
| 277 | cpufreq_cooling_unregister(priv->cdev); |
| 278 | kfree(priv); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 279 | out_free_table: |
Nishanth Menon | 5d4879c | 2013-09-19 16:03:50 -0500 | [diff] [blame] | 280 | dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 281 | out_put_node: |
| 282 | of_node_put(np); |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 283 | out_put_reg_clk: |
| 284 | clk_put(cpu_clk); |
| 285 | if (!IS_ERR(cpu_reg)) |
| 286 | regulator_put(cpu_reg); |
| 287 | |
| 288 | return ret; |
| 289 | } |
| 290 | |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 291 | static int cpufreq_exit(struct cpufreq_policy *policy) |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 292 | { |
| 293 | struct private_data *priv = policy->driver_data; |
| 294 | |
| 295 | cpufreq_cooling_unregister(priv->cdev); |
| 296 | dev_pm_opp_free_cpufreq_table(priv->cpu_dev, &policy->freq_table); |
| 297 | clk_put(policy->clk); |
| 298 | if (!IS_ERR(priv->cpu_reg)) |
| 299 | regulator_put(priv->cpu_reg); |
| 300 | kfree(priv); |
| 301 | |
| 302 | return 0; |
| 303 | } |
| 304 | |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 305 | static struct cpufreq_driver dt_cpufreq_driver = { |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 306 | .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK, |
| 307 | .verify = cpufreq_generic_frequency_table_verify, |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 308 | .target_index = set_target, |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 309 | .get = cpufreq_generic_get, |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 310 | .init = cpufreq_init, |
| 311 | .exit = cpufreq_exit, |
| 312 | .name = "cpufreq-dt", |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 313 | .attr = cpufreq_generic_attr, |
| 314 | }; |
| 315 | |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 316 | static int dt_cpufreq_probe(struct platform_device *pdev) |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 317 | { |
| 318 | struct device *cpu_dev; |
| 319 | struct regulator *cpu_reg; |
| 320 | struct clk *cpu_clk; |
| 321 | int ret; |
| 322 | |
| 323 | /* |
| 324 | * All per-cluster (CPUs sharing clock/voltages) initialization is done |
| 325 | * from ->init(). In probe(), we just need to make sure that clk and |
| 326 | * regulators are available. Else defer probe and retry. |
| 327 | * |
| 328 | * FIXME: Is checking this only for CPU0 sufficient ? |
| 329 | */ |
Viresh Kumar | 95b6105 | 2014-08-28 11:22:30 +0530 | [diff] [blame] | 330 | ret = allocate_resources(0, &cpu_dev, &cpu_reg, &cpu_clk); |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 331 | if (ret) |
| 332 | return ret; |
| 333 | |
| 334 | clk_put(cpu_clk); |
| 335 | if (!IS_ERR(cpu_reg)) |
| 336 | regulator_put(cpu_reg); |
| 337 | |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 338 | ret = cpufreq_register_driver(&dt_cpufreq_driver); |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 339 | if (ret) |
| 340 | dev_err(cpu_dev, "failed register driver: %d\n", ret); |
| 341 | |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 342 | return ret; |
| 343 | } |
Shawn Guo | 5553f9e | 2013-01-30 14:27:49 +0000 | [diff] [blame] | 344 | |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 345 | static int dt_cpufreq_remove(struct platform_device *pdev) |
Shawn Guo | 5553f9e | 2013-01-30 14:27:49 +0000 | [diff] [blame] | 346 | { |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 347 | cpufreq_unregister_driver(&dt_cpufreq_driver); |
Shawn Guo | 5553f9e | 2013-01-30 14:27:49 +0000 | [diff] [blame] | 348 | return 0; |
| 349 | } |
| 350 | |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 351 | static struct platform_driver dt_cpufreq_platdrv = { |
Shawn Guo | 5553f9e | 2013-01-30 14:27:49 +0000 | [diff] [blame] | 352 | .driver = { |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 353 | .name = "cpufreq-dt", |
Shawn Guo | 5553f9e | 2013-01-30 14:27:49 +0000 | [diff] [blame] | 354 | .owner = THIS_MODULE, |
| 355 | }, |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 356 | .probe = dt_cpufreq_probe, |
| 357 | .remove = dt_cpufreq_remove, |
Shawn Guo | 5553f9e | 2013-01-30 14:27:49 +0000 | [diff] [blame] | 358 | }; |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 359 | module_platform_driver(dt_cpufreq_platdrv); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 360 | |
Viresh Kumar | 748c876 | 2014-08-28 11:22:24 +0530 | [diff] [blame] | 361 | MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>"); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 362 | MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 363 | MODULE_DESCRIPTION("Generic cpufreq driver"); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 364 | MODULE_LICENSE("GPL"); |