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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2** System Bus Adapter (SBA) I/O MMU manager
3**
4** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org>
5** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com>
6** (c) Copyright 2000-2004 Hewlett-Packard Company
7**
8** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)
9**
10** This program is free software; you can redistribute it and/or modify
11** it under the terms of the GNU General Public License as published by
12** the Free Software Foundation; either version 2 of the License, or
13** (at your option) any later version.
14**
15**
16** This module initializes the IOC (I/O Controller) found on B1000/C3000/
17** J5000/J7000/N-class/L-class machines and their successors.
18**
19** FIXME: add DMA hint support programming in both sba and lba modules.
20*/
21
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#include <linux/types.h>
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
25#include <linux/slab.h>
26#include <linux/init.h>
27
28#include <linux/mm.h>
29#include <linux/string.h>
30#include <linux/pci.h>
FUJITA Tomonorib61e8f42007-10-23 09:30:28 +020031#include <linux/scatterlist.h>
FUJITA Tomonori46663442008-03-04 14:29:28 -080032#include <linux/iommu-helper.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070033
34#include <asm/byteorder.h>
35#include <asm/io.h>
36#include <asm/dma.h> /* for DMA_CHUNK_SIZE */
37
38#include <asm/hardware.h> /* for register_parisc_driver() stuff */
39
40#include <linux/proc_fs.h>
Kyle McMartin7ec14e42006-02-06 10:10:15 -070041#include <linux/seq_file.h>
42
Kyle McMartin1790cf92006-08-24 21:32:49 -040043#include <asm/ropes.h>
Kyle McMartin6f034952006-08-13 22:18:57 -040044#include <asm/mckinley.h> /* for proc_mckinley_root */
Linus Torvalds1da177e2005-04-16 15:20:36 -070045#include <asm/runway.h> /* for proc_runway_root */
46#include <asm/pdc.h> /* for PDC_MODEL_* */
47#include <asm/pdcpat.h> /* for is_pdc_pat() */
48#include <asm/parisc-device.h>
49
Linus Torvalds1da177e2005-04-16 15:20:36 -070050#define MODULE_NAME "SBA"
51
Linus Torvalds1da177e2005-04-16 15:20:36 -070052/*
53** The number of debug flags is a clue - this code is fragile.
54** Don't even think about messing with it unless you have
55** plenty of 710's to sacrifice to the computer gods. :^)
56*/
57#undef DEBUG_SBA_INIT
58#undef DEBUG_SBA_RUN
59#undef DEBUG_SBA_RUN_SG
60#undef DEBUG_SBA_RESOURCE
61#undef ASSERT_PDIR_SANITY
62#undef DEBUG_LARGE_SG_ENTRIES
63#undef DEBUG_DMB_TRAP
64
65#ifdef DEBUG_SBA_INIT
66#define DBG_INIT(x...) printk(x)
67#else
68#define DBG_INIT(x...)
69#endif
70
71#ifdef DEBUG_SBA_RUN
72#define DBG_RUN(x...) printk(x)
73#else
74#define DBG_RUN(x...)
75#endif
76
77#ifdef DEBUG_SBA_RUN_SG
78#define DBG_RUN_SG(x...) printk(x)
79#else
80#define DBG_RUN_SG(x...)
81#endif
82
83
84#ifdef DEBUG_SBA_RESOURCE
85#define DBG_RES(x...) printk(x)
86#else
87#define DBG_RES(x...)
88#endif
89
Linus Torvalds1da177e2005-04-16 15:20:36 -070090#define SBA_INLINE __inline__
91
Linus Torvalds1da177e2005-04-16 15:20:36 -070092#define DEFAULT_DMA_HINT_REG 0
93
Kyle McMartin08a64362006-08-24 21:33:40 -040094struct sba_device *sba_list;
95EXPORT_SYMBOL_GPL(sba_list);
Linus Torvalds1da177e2005-04-16 15:20:36 -070096
97static unsigned long ioc_needs_fdc = 0;
98
99/* global count of IOMMUs in the system */
100static unsigned int global_ioc_cnt = 0;
101
102/* PA8700 (Piranha 2.2) bug workaround */
103static unsigned long piranha_bad_128k = 0;
104
105/* Looks nice and keeps the compiler happy */
106#define SBA_DEV(d) ((struct sba_device *) (d))
107
Kyle McMartin08a64362006-08-24 21:33:40 -0400108#ifdef CONFIG_AGP_PARISC
109#define SBA_AGP_SUPPORT
110#endif /*CONFIG_AGP_PARISC*/
111
Grant Grundler64908ad2005-10-21 22:37:20 -0400112#ifdef SBA_AGP_SUPPORT
Kyle McMartin08a64362006-08-24 21:33:40 -0400113static int sba_reserve_agpgart = 1;
Randy Dunlap29a1e1d2007-02-05 16:33:59 -0800114module_param(sba_reserve_agpgart, int, 0444);
Kyle McMartin08a64362006-08-24 21:33:40 -0400115MODULE_PARM_DESC(sba_reserve_agpgart, "Reserve half of IO pdir as AGPGART");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700116#endif
117
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118
119/************************************
120** SBA register read and write support
121**
122** BE WARNED: register writes are posted.
123** (ie follow writes which must reach HW with a read)
124**
125** Superdome (in particular, REO) allows only 64-bit CSR accesses.
126*/
Grant Grundler40d78de2006-05-11 00:31:31 -0600127#define READ_REG32(addr) readl(addr)
128#define READ_REG64(addr) readq(addr)
129#define WRITE_REG32(val, addr) writel((val), (addr))
130#define WRITE_REG64(val, addr) writeq((val), (addr))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131
Grant Grundler64908ad2005-10-21 22:37:20 -0400132#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700133#define READ_REG(addr) READ_REG64(addr)
134#define WRITE_REG(value, addr) WRITE_REG64(value, addr)
135#else
136#define READ_REG(addr) READ_REG32(addr)
137#define WRITE_REG(value, addr) WRITE_REG32(value, addr)
138#endif
139
140#ifdef DEBUG_SBA_INIT
141
Grant Grundler64908ad2005-10-21 22:37:20 -0400142/* NOTE: When CONFIG_64BIT isn't defined, READ_REG64() is two 32-bit reads */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700143
144/**
145 * sba_dump_ranges - debugging only - print ranges assigned to this IOA
146 * @hpa: base address of the sba
147 *
148 * Print the MMIO and IO Port address ranges forwarded by an Astro/Ike/RIO
149 * IO Adapter (aka Bus Converter).
150 */
151static void
152sba_dump_ranges(void __iomem *hpa)
153{
154 DBG_INIT("SBA at 0x%p\n", hpa);
155 DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE));
156 DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK));
157 DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE));
158 DBG_INIT("\n");
159 DBG_INIT("IOS_DIRECT_BASE : %Lx\n", READ_REG64(hpa+IOS_DIRECT_BASE));
160 DBG_INIT("IOS_DIRECT_MASK : %Lx\n", READ_REG64(hpa+IOS_DIRECT_MASK));
161 DBG_INIT("IOS_DIRECT_ROUTE: %Lx\n", READ_REG64(hpa+IOS_DIRECT_ROUTE));
162}
163
164/**
165 * sba_dump_tlb - debugging only - print IOMMU operating parameters
166 * @hpa: base address of the IOMMU
167 *
168 * Print the size/location of the IO MMU PDIR.
169 */
170static void sba_dump_tlb(void __iomem *hpa)
171{
172 DBG_INIT("IO TLB at 0x%p\n", hpa);
173 DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE));
174 DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK));
175 DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG));
176 DBG_INIT("IOC_PDIR_BASE: 0x%Lx\n", READ_REG64(hpa+IOC_PDIR_BASE));
177 DBG_INIT("\n");
178}
179#else
180#define sba_dump_ranges(x)
181#define sba_dump_tlb(x)
Grant Grundler64908ad2005-10-21 22:37:20 -0400182#endif /* DEBUG_SBA_INIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700183
184
185#ifdef ASSERT_PDIR_SANITY
186
187/**
188 * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry
189 * @ioc: IO MMU structure which owns the pdir we are interested in.
190 * @msg: text to print ont the output line.
191 * @pide: pdir index.
192 *
193 * Print one entry of the IO MMU PDIR in human readable form.
194 */
195static void
196sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide)
197{
198 /* start printing from lowest pde in rval */
199 u64 *ptr = &(ioc->pdir_base[pide & (~0U * BITS_PER_LONG)]);
200 unsigned long *rptr = (unsigned long *) &(ioc->res_map[(pide >>3) & ~(sizeof(unsigned long) - 1)]);
201 uint rcnt;
202
203 printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n",
204 msg,
205 rptr, pide & (BITS_PER_LONG - 1), *rptr);
206
207 rcnt = 0;
208 while (rcnt < BITS_PER_LONG) {
209 printk(KERN_DEBUG "%s %2d %p %016Lx\n",
210 (rcnt == (pide & (BITS_PER_LONG - 1)))
211 ? " -->" : " ",
212 rcnt, ptr, *ptr );
213 rcnt++;
214 ptr++;
215 }
216 printk(KERN_DEBUG "%s", msg);
217}
218
219
220/**
221 * sba_check_pdir - debugging only - consistency checker
222 * @ioc: IO MMU structure which owns the pdir we are interested in.
223 * @msg: text to print ont the output line.
224 *
225 * Verify the resource map and pdir state is consistent
226 */
227static int
228sba_check_pdir(struct ioc *ioc, char *msg)
229{
230 u32 *rptr_end = (u32 *) &(ioc->res_map[ioc->res_size]);
231 u32 *rptr = (u32 *) ioc->res_map; /* resource map ptr */
232 u64 *pptr = ioc->pdir_base; /* pdir ptr */
233 uint pide = 0;
234
235 while (rptr < rptr_end) {
236 u32 rval = *rptr;
237 int rcnt = 32; /* number of bits we might check */
238
239 while (rcnt) {
240 /* Get last byte and highest bit from that */
241 u32 pde = ((u32) (((char *)pptr)[7])) << 24;
242 if ((rval ^ pde) & 0x80000000)
243 {
244 /*
245 ** BUMMER! -- res_map != pdir --
246 ** Dump rval and matching pdir entries
247 */
248 sba_dump_pdir_entry(ioc, msg, pide);
249 return(1);
250 }
251 rcnt--;
252 rval <<= 1; /* try the next bit */
253 pptr++;
254 pide++;
255 }
256 rptr++; /* look at next word of res_map */
257 }
258 /* It'd be nice if we always got here :^) */
259 return 0;
260}
261
262
263/**
264 * sba_dump_sg - debugging only - print Scatter-Gather list
265 * @ioc: IO MMU structure which owns the pdir we are interested in.
266 * @startsg: head of the SG list
267 * @nents: number of entries in SG list
268 *
269 * print the SG list so we can verify it's correct by hand.
270 */
271static void
272sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
273{
274 while (nents-- > 0) {
275 printk(KERN_DEBUG " %d : %08lx/%05x %p/%05x\n",
276 nents,
277 (unsigned long) sg_dma_address(startsg),
278 sg_dma_len(startsg),
279 sg_virt_addr(startsg), startsg->length);
280 startsg++;
281 }
282}
283
284#endif /* ASSERT_PDIR_SANITY */
285
286
287
288
289/**************************************************************
290*
291* I/O Pdir Resource Management
292*
293* Bits set in the resource map are in use.
294* Each bit can represent a number of pages.
295* LSbs represent lower addresses (IOVA's).
296*
297***************************************************************/
298#define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */
299
300/* Convert from IOVP to IOVA and vice versa. */
301
302#ifdef ZX1_SUPPORT
303/* Pluto (aka ZX1) boxes need to set or clear the ibase bits appropriately */
304#define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset))
305#define SBA_IOVP(ioc,iova) ((iova) & (ioc)->iovp_mask)
306#else
307/* only support Astro and ancestors. Saves a few cycles in key places */
308#define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset))
309#define SBA_IOVP(ioc,iova) (iova)
310#endif
311
312#define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT)
313
314#define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n)))
315#define RESMAP_IDX_MASK (sizeof(unsigned long) - 1)
316
FUJITA Tomonori56ee0cf2008-03-10 20:43:24 +0900317static unsigned long ptr_to_pide(struct ioc *ioc, unsigned long *res_ptr,
318 unsigned int bitshiftcnt)
FUJITA Tomonori46663442008-03-04 14:29:28 -0800319{
320 return (((unsigned long)res_ptr - (unsigned long)ioc->res_map) << 3)
321 + bitshiftcnt;
322}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700323
324/**
325 * sba_search_bitmap - find free space in IO PDIR resource bitmap
326 * @ioc: IO MMU structure which owns the pdir we are interested in.
327 * @bits_wanted: number of entries we need.
328 *
329 * Find consecutive free bits in resource bitmap.
330 * Each bit represents one entry in the IO Pdir.
331 * Cool perf optimization: search for log2(size) bits at a time.
332 */
333static SBA_INLINE unsigned long
FUJITA Tomonori46663442008-03-04 14:29:28 -0800334sba_search_bitmap(struct ioc *ioc, struct device *dev,
335 unsigned long bits_wanted)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700336{
337 unsigned long *res_ptr = ioc->res_hint;
338 unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]);
FUJITA Tomonori46663442008-03-04 14:29:28 -0800339 unsigned long pide = ~0UL, tpide;
340 unsigned long boundary_size;
341 unsigned long shift;
342 int ret;
343
FUJITA Tomonori4a0d3f32008-03-05 17:09:30 +0900344 boundary_size = ALIGN((unsigned long long)dma_get_seg_boundary(dev) + 1,
345 1ULL << IOVP_SHIFT) >> IOVP_SHIFT;
FUJITA Tomonori46663442008-03-04 14:29:28 -0800346
347#if defined(ZX1_SUPPORT)
348 BUG_ON(ioc->ibase & ~IOVP_MASK);
349 shift = ioc->ibase >> IOVP_SHIFT;
350#else
351 shift = 0;
352#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700353
354 if (bits_wanted > (BITS_PER_LONG/2)) {
355 /* Search word at a time - no mask needed */
356 for(; res_ptr < res_end; ++res_ptr) {
FUJITA Tomonori46663442008-03-04 14:29:28 -0800357 tpide = ptr_to_pide(ioc, res_ptr, 0);
358 ret = iommu_is_span_boundary(tpide, bits_wanted,
359 shift,
360 boundary_size);
361 if ((*res_ptr == 0) && !ret) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700362 *res_ptr = RESMAP_MASK(bits_wanted);
FUJITA Tomonori46663442008-03-04 14:29:28 -0800363 pide = tpide;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700364 break;
365 }
366 }
367 /* point to the next word on next pass */
368 res_ptr++;
369 ioc->res_bitshift = 0;
370 } else {
371 /*
372 ** Search the resource bit map on well-aligned values.
373 ** "o" is the alignment.
374 ** We need the alignment to invalidate I/O TLB using
375 ** SBA HW features in the unmap path.
376 */
377 unsigned long o = 1 << get_order(bits_wanted << PAGE_SHIFT);
Milind Arun Choudhary3cb1d952007-03-06 02:44:13 -0800378 uint bitshiftcnt = ALIGN(ioc->res_bitshift, o);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700379 unsigned long mask;
380
381 if (bitshiftcnt >= BITS_PER_LONG) {
382 bitshiftcnt = 0;
383 res_ptr++;
384 }
385 mask = RESMAP_MASK(bits_wanted) >> bitshiftcnt;
386
387 DBG_RES("%s() o %ld %p", __FUNCTION__, o, res_ptr);
388 while(res_ptr < res_end)
389 {
390 DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr);
391 WARN_ON(mask == 0);
FUJITA Tomonori46663442008-03-04 14:29:28 -0800392 tpide = ptr_to_pide(ioc, res_ptr, bitshiftcnt);
393 ret = iommu_is_span_boundary(tpide, bits_wanted,
394 shift,
395 boundary_size);
396 if ((((*res_ptr) & mask) == 0) && !ret) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700397 *res_ptr |= mask; /* mark resources busy! */
FUJITA Tomonori46663442008-03-04 14:29:28 -0800398 pide = tpide;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700399 break;
400 }
401 mask >>= o;
402 bitshiftcnt += o;
403 if (mask == 0) {
404 mask = RESMAP_MASK(bits_wanted);
405 bitshiftcnt=0;
406 res_ptr++;
407 }
408 }
409 /* look in the same word on the next pass */
410 ioc->res_bitshift = bitshiftcnt + bits_wanted;
411 }
412
413 /* wrapped ? */
414 if (res_end <= res_ptr) {
415 ioc->res_hint = (unsigned long *) ioc->res_map;
416 ioc->res_bitshift = 0;
417 } else {
418 ioc->res_hint = res_ptr;
419 }
420 return (pide);
421}
422
423
424/**
425 * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap
426 * @ioc: IO MMU structure which owns the pdir we are interested in.
427 * @size: number of bytes to create a mapping for
428 *
429 * Given a size, find consecutive unmarked and then mark those bits in the
430 * resource bit map.
431 */
432static int
FUJITA Tomonori7c8cda62008-03-04 14:29:28 -0800433sba_alloc_range(struct ioc *ioc, struct device *dev, size_t size)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700434{
435 unsigned int pages_needed = size >> IOVP_SHIFT;
436#ifdef SBA_COLLECT_STATS
437 unsigned long cr_start = mfctl(16);
438#endif
439 unsigned long pide;
440
FUJITA Tomonori46663442008-03-04 14:29:28 -0800441 pide = sba_search_bitmap(ioc, dev, pages_needed);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700442 if (pide >= (ioc->res_size << 3)) {
FUJITA Tomonori46663442008-03-04 14:29:28 -0800443 pide = sba_search_bitmap(ioc, dev, pages_needed);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700444 if (pide >= (ioc->res_size << 3))
445 panic("%s: I/O MMU @ %p is out of mapping resources\n",
446 __FILE__, ioc->ioc_hpa);
447 }
448
449#ifdef ASSERT_PDIR_SANITY
450 /* verify the first enable bit is clear */
451 if(0x00 != ((u8 *) ioc->pdir_base)[pide*sizeof(u64) + 7]) {
452 sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide);
453 }
454#endif
455
456 DBG_RES("%s(%x) %d -> %lx hint %x/%x\n",
457 __FUNCTION__, size, pages_needed, pide,
458 (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map),
459 ioc->res_bitshift );
460
461#ifdef SBA_COLLECT_STATS
462 {
463 unsigned long cr_end = mfctl(16);
464 unsigned long tmp = cr_end - cr_start;
465 /* check for roll over */
466 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp);
467 }
468 ioc->avg_search[ioc->avg_idx++] = cr_start;
469 ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1;
470
471 ioc->used_pages += pages_needed;
472#endif
473
474 return (pide);
475}
476
477
478/**
479 * sba_free_range - unmark bits in IO PDIR resource bitmap
480 * @ioc: IO MMU structure which owns the pdir we are interested in.
481 * @iova: IO virtual address which was previously allocated.
482 * @size: number of bytes to create a mapping for
483 *
484 * clear bits in the ioc's resource map
485 */
486static SBA_INLINE void
487sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size)
488{
489 unsigned long iovp = SBA_IOVP(ioc, iova);
490 unsigned int pide = PDIR_INDEX(iovp);
491 unsigned int ridx = pide >> 3; /* convert bit to byte address */
492 unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]);
493
494 int bits_not_wanted = size >> IOVP_SHIFT;
495
496 /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */
497 unsigned long m = RESMAP_MASK(bits_not_wanted) >> (pide & (BITS_PER_LONG - 1));
498
499 DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n",
500 __FUNCTION__, (uint) iova, size,
501 bits_not_wanted, m, pide, res_ptr, *res_ptr);
502
503#ifdef SBA_COLLECT_STATS
504 ioc->used_pages -= bits_not_wanted;
505#endif
506
507 *res_ptr &= ~m;
508}
509
510
511/**************************************************************
512*
513* "Dynamic DMA Mapping" support (aka "Coherent I/O")
514*
515***************************************************************/
516
Grant Grundler64908ad2005-10-21 22:37:20 -0400517#ifdef SBA_HINT_SUPPORT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700518#define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir)
519#endif
520
521typedef unsigned long space_t;
522#define KERNEL_SPACE 0
523
524/**
525 * sba_io_pdir_entry - fill in one IO PDIR entry
526 * @pdir_ptr: pointer to IO PDIR entry
527 * @sid: process Space ID - currently only support KERNEL_SPACE
528 * @vba: Virtual CPU address of buffer to map
529 * @hint: DMA hint set to use for this mapping
530 *
531 * SBA Mapping Routine
532 *
533 * Given a virtual address (vba, arg2) and space id, (sid, arg1)
534 * sba_io_pdir_entry() loads the I/O PDIR entry pointed to by
535 * pdir_ptr (arg0).
536 * Using the bass-ackwards HP bit numbering, Each IO Pdir entry
537 * for Astro/Ike looks like:
538 *
539 *
540 * 0 19 51 55 63
541 * +-+---------------------+----------------------------------+----+--------+
542 * |V| U | PPN[43:12] | U | VI |
543 * +-+---------------------+----------------------------------+----+--------+
544 *
545 * Pluto is basically identical, supports fewer physical address bits:
546 *
547 * 0 23 51 55 63
548 * +-+------------------------+-------------------------------+----+--------+
549 * |V| U | PPN[39:12] | U | VI |
550 * +-+------------------------+-------------------------------+----+--------+
551 *
552 * V == Valid Bit (Most Significant Bit is bit 0)
553 * U == Unused
554 * PPN == Physical Page Number
555 * VI == Virtual Index (aka Coherent Index)
556 *
557 * LPA instruction output is put into PPN field.
558 * LCI (Load Coherence Index) instruction provides the "VI" bits.
559 *
560 * We pre-swap the bytes since PCX-W is Big Endian and the
561 * IOMMU uses little endian for the pdir.
562 */
563
564void SBA_INLINE
565sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
566 unsigned long hint)
567{
568 u64 pa; /* physical address */
569 register unsigned ci; /* coherent index */
570
571 pa = virt_to_phys(vba);
572 pa &= IOVP_MASK;
573
574 mtsp(sid,1);
575 asm("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba));
576 pa |= (ci >> 12) & 0xff; /* move CI (8 bits) into lowest byte */
577
Kyle McMartin983daee2006-08-25 12:28:24 -0400578 pa |= SBA_PDIR_VALID_BIT; /* set "valid" bit */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700579 *pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */
580
581 /*
582 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
583 * (bit #61, big endian), we have to flush and sync every time
584 * IO-PDIR is changed in Ike/Astro.
585 */
Grant Grundler64908ad2005-10-21 22:37:20 -0400586 if (ioc_needs_fdc)
587 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700588}
589
590
591/**
592 * sba_mark_invalid - invalidate one or more IO PDIR entries
593 * @ioc: IO MMU structure which owns the pdir we are interested in.
594 * @iova: IO Virtual Address mapped earlier
595 * @byte_cnt: number of bytes this mapping covers.
596 *
597 * Marking the IO PDIR entry(ies) as Invalid and invalidate
598 * corresponding IO TLB entry. The Ike PCOM (Purge Command Register)
599 * is to purge stale entries in the IO TLB when unmapping entries.
600 *
601 * The PCOM register supports purging of multiple pages, with a minium
602 * of 1 page and a maximum of 2GB. Hardware requires the address be
603 * aligned to the size of the range being purged. The size of the range
604 * must be a power of 2. The "Cool perf optimization" in the
605 * allocation routine helps keep that true.
606 */
607static SBA_INLINE void
608sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
609{
610 u32 iovp = (u32) SBA_IOVP(ioc,iova);
Grant Grundler64908ad2005-10-21 22:37:20 -0400611 u64 *pdir_ptr = &ioc->pdir_base[PDIR_INDEX(iovp)];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700612
613#ifdef ASSERT_PDIR_SANITY
Grant Grundler64908ad2005-10-21 22:37:20 -0400614 /* Assert first pdir entry is set.
615 **
616 ** Even though this is a big-endian machine, the entries
617 ** in the iopdir are little endian. That's why we look at
618 ** the byte at +7 instead of at +0.
619 */
620 if (0x80 != (((u8 *) pdir_ptr)[7])) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700621 sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp));
622 }
623#endif
624
Grant Grundler64908ad2005-10-21 22:37:20 -0400625 if (byte_cnt > IOVP_SIZE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700626 {
Grant Grundler64908ad2005-10-21 22:37:20 -0400627#if 0
628 unsigned long entries_per_cacheline = ioc_needs_fdc ?
629 L1_CACHE_ALIGN(((unsigned long) pdir_ptr))
630 - (unsigned long) pdir_ptr;
631 : 262144;
632#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700633
Grant Grundler64908ad2005-10-21 22:37:20 -0400634 /* set "size" field for PCOM */
635 iovp |= get_order(byte_cnt) + PAGE_SHIFT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700636
Linus Torvalds1da177e2005-04-16 15:20:36 -0700637 do {
638 /* clear I/O Pdir entry "valid" bit first */
Grant Grundler64908ad2005-10-21 22:37:20 -0400639 ((u8 *) pdir_ptr)[7] = 0;
640 if (ioc_needs_fdc) {
641 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
642#if 0
643 entries_per_cacheline = L1_CACHE_SHIFT - 3;
644#endif
645 }
646 pdir_ptr++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700647 byte_cnt -= IOVP_SIZE;
Grant Grundler64908ad2005-10-21 22:37:20 -0400648 } while (byte_cnt > IOVP_SIZE);
649 } else
650 iovp |= IOVP_SHIFT; /* set "size" field for PCOM */
651
652 /*
653 ** clear I/O PDIR entry "valid" bit.
654 ** We have to R/M/W the cacheline regardless how much of the
655 ** pdir entry that we clobber.
656 ** The rest of the entry would be useful for debugging if we
657 ** could dump core on HPMC.
658 */
659 ((u8 *) pdir_ptr)[7] = 0;
660 if (ioc_needs_fdc)
661 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700662
663 WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM);
664}
665
666/**
667 * sba_dma_supported - PCI driver can query DMA support
668 * @dev: instance of PCI owned by the driver that's asking
669 * @mask: number of address bits this PCI device can handle
670 *
671 * See Documentation/DMA-mapping.txt
672 */
673static int sba_dma_supported( struct device *dev, u64 mask)
674{
675 struct ioc *ioc;
Grant Grundler64908ad2005-10-21 22:37:20 -0400676
Linus Torvalds1da177e2005-04-16 15:20:36 -0700677 if (dev == NULL) {
678 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n");
679 BUG();
680 return(0);
681 }
682
Grant Grundler64908ad2005-10-21 22:37:20 -0400683 /* Documentation/DMA-mapping.txt tells drivers to try 64-bit first,
684 * then fall back to 32-bit if that fails.
685 * We are just "encouraging" 32-bit DMA masks here since we can
686 * never allow IOMMU bypass unless we add special support for ZX1.
687 */
688 if (mask > ~0U)
689 return 0;
690
Linus Torvalds1da177e2005-04-16 15:20:36 -0700691 ioc = GET_IOC(dev);
692
Grant Grundler64908ad2005-10-21 22:37:20 -0400693 /*
694 * check if mask is >= than the current max IO Virt Address
695 * The max IO Virt address will *always* < 30 bits.
696 */
697 return((int)(mask >= (ioc->ibase - 1 +
698 (ioc->pdir_size / sizeof(u64) * IOVP_SIZE) )));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700699}
700
701
702/**
703 * sba_map_single - map one buffer and return IOVA for DMA
704 * @dev: instance of PCI owned by the driver that's asking.
705 * @addr: driver buffer to map.
706 * @size: number of bytes to map in driver buffer.
707 * @direction: R/W or both.
708 *
709 * See Documentation/DMA-mapping.txt
710 */
711static dma_addr_t
712sba_map_single(struct device *dev, void *addr, size_t size,
713 enum dma_data_direction direction)
714{
715 struct ioc *ioc;
716 unsigned long flags;
717 dma_addr_t iovp;
718 dma_addr_t offset;
719 u64 *pdir_start;
720 int pide;
721
722 ioc = GET_IOC(dev);
723
724 /* save offset bits */
725 offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK;
726
727 /* round up to nearest IOVP_SIZE */
728 size = (size + offset + ~IOVP_MASK) & IOVP_MASK;
729
730 spin_lock_irqsave(&ioc->res_lock, flags);
731#ifdef ASSERT_PDIR_SANITY
732 sba_check_pdir(ioc,"Check before sba_map_single()");
733#endif
734
735#ifdef SBA_COLLECT_STATS
736 ioc->msingle_calls++;
737 ioc->msingle_pages += size >> IOVP_SHIFT;
738#endif
FUJITA Tomonori7c8cda62008-03-04 14:29:28 -0800739 pide = sba_alloc_range(ioc, dev, size);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700740 iovp = (dma_addr_t) pide << IOVP_SHIFT;
741
742 DBG_RUN("%s() 0x%p -> 0x%lx\n",
743 __FUNCTION__, addr, (long) iovp | offset);
744
745 pdir_start = &(ioc->pdir_base[pide]);
746
747 while (size > 0) {
748 sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0);
749
750 DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n",
751 pdir_start,
752 (u8) (((u8 *) pdir_start)[7]),
753 (u8) (((u8 *) pdir_start)[6]),
754 (u8) (((u8 *) pdir_start)[5]),
755 (u8) (((u8 *) pdir_start)[4]),
756 (u8) (((u8 *) pdir_start)[3]),
757 (u8) (((u8 *) pdir_start)[2]),
758 (u8) (((u8 *) pdir_start)[1]),
759 (u8) (((u8 *) pdir_start)[0])
760 );
761
762 addr += IOVP_SIZE;
763 size -= IOVP_SIZE;
764 pdir_start++;
765 }
Grant Grundler64908ad2005-10-21 22:37:20 -0400766
767 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
768 if (ioc_needs_fdc)
769 asm volatile("sync" : : );
770
Linus Torvalds1da177e2005-04-16 15:20:36 -0700771#ifdef ASSERT_PDIR_SANITY
772 sba_check_pdir(ioc,"Check after sba_map_single()");
773#endif
774 spin_unlock_irqrestore(&ioc->res_lock, flags);
Grant Grundler64908ad2005-10-21 22:37:20 -0400775
776 /* form complete address */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700777 return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG);
778}
779
780
781/**
782 * sba_unmap_single - unmap one IOVA and free resources
783 * @dev: instance of PCI owned by the driver that's asking.
784 * @iova: IOVA of driver buffer previously mapped.
785 * @size: number of bytes mapped in driver buffer.
786 * @direction: R/W or both.
787 *
788 * See Documentation/DMA-mapping.txt
789 */
790static void
791sba_unmap_single(struct device *dev, dma_addr_t iova, size_t size,
792 enum dma_data_direction direction)
793{
794 struct ioc *ioc;
795#if DELAYED_RESOURCE_CNT > 0
796 struct sba_dma_pair *d;
797#endif
798 unsigned long flags;
799 dma_addr_t offset;
800
801 DBG_RUN("%s() iovp 0x%lx/%x\n", __FUNCTION__, (long) iova, size);
802
803 ioc = GET_IOC(dev);
804 offset = iova & ~IOVP_MASK;
805 iova ^= offset; /* clear offset bits */
806 size += offset;
Milind Arun Choudhary3cb1d952007-03-06 02:44:13 -0800807 size = ALIGN(size, IOVP_SIZE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700808
809 spin_lock_irqsave(&ioc->res_lock, flags);
810
811#ifdef SBA_COLLECT_STATS
812 ioc->usingle_calls++;
813 ioc->usingle_pages += size >> IOVP_SHIFT;
814#endif
815
816 sba_mark_invalid(ioc, iova, size);
817
818#if DELAYED_RESOURCE_CNT > 0
819 /* Delaying when we re-use a IO Pdir entry reduces the number
820 * of MMIO reads needed to flush writes to the PCOM register.
821 */
822 d = &(ioc->saved[ioc->saved_cnt]);
823 d->iova = iova;
824 d->size = size;
825 if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) {
826 int cnt = ioc->saved_cnt;
827 while (cnt--) {
828 sba_free_range(ioc, d->iova, d->size);
829 d--;
830 }
831 ioc->saved_cnt = 0;
Grant Grundler64908ad2005-10-21 22:37:20 -0400832
Linus Torvalds1da177e2005-04-16 15:20:36 -0700833 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
834 }
835#else /* DELAYED_RESOURCE_CNT == 0 */
836 sba_free_range(ioc, iova, size);
Grant Grundler64908ad2005-10-21 22:37:20 -0400837
838 /* If fdc's were issued, force fdc's to be visible now */
839 if (ioc_needs_fdc)
840 asm volatile("sync" : : );
841
Linus Torvalds1da177e2005-04-16 15:20:36 -0700842 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
843#endif /* DELAYED_RESOURCE_CNT == 0 */
Grant Grundler64908ad2005-10-21 22:37:20 -0400844
Linus Torvalds1da177e2005-04-16 15:20:36 -0700845 spin_unlock_irqrestore(&ioc->res_lock, flags);
846
847 /* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support.
848 ** For Astro based systems this isn't a big deal WRT performance.
849 ** As long as 2.4 kernels copyin/copyout data from/to userspace,
850 ** we don't need the syncdma. The issue here is I/O MMU cachelines
851 ** are *not* coherent in all cases. May be hwrev dependent.
852 ** Need to investigate more.
853 asm volatile("syncdma");
854 */
855}
856
857
858/**
859 * sba_alloc_consistent - allocate/map shared mem for DMA
860 * @hwdev: instance of PCI owned by the driver that's asking.
861 * @size: number of bytes mapped in driver buffer.
862 * @dma_handle: IOVA of new buffer.
863 *
864 * See Documentation/DMA-mapping.txt
865 */
866static void *sba_alloc_consistent(struct device *hwdev, size_t size,
Al Viro5c1fb412005-10-21 03:21:28 -0400867 dma_addr_t *dma_handle, gfp_t gfp)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700868{
869 void *ret;
870
871 if (!hwdev) {
872 /* only support PCI */
873 *dma_handle = 0;
Matthew Wilcoxc2c47982006-10-26 10:06:07 -0600874 return NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700875 }
876
877 ret = (void *) __get_free_pages(gfp, get_order(size));
878
879 if (ret) {
880 memset(ret, 0, size);
881 *dma_handle = sba_map_single(hwdev, ret, size, 0);
882 }
883
884 return ret;
885}
886
887
888/**
889 * sba_free_consistent - free/unmap shared mem for DMA
890 * @hwdev: instance of PCI owned by the driver that's asking.
891 * @size: number of bytes mapped in driver buffer.
892 * @vaddr: virtual address IOVA of "consistent" buffer.
893 * @dma_handler: IO virtual address of "consistent" buffer.
894 *
895 * See Documentation/DMA-mapping.txt
896 */
897static void
898sba_free_consistent(struct device *hwdev, size_t size, void *vaddr,
899 dma_addr_t dma_handle)
900{
901 sba_unmap_single(hwdev, dma_handle, size, 0);
902 free_pages((unsigned long) vaddr, get_order(size));
903}
904
905
906/*
907** Since 0 is a valid pdir_base index value, can't use that
908** to determine if a value is valid or not. Use a flag to indicate
909** the SG list entry contains a valid pdir index.
910*/
911#define PIDE_FLAG 0x80000000UL
912
913#ifdef SBA_COLLECT_STATS
914#define IOMMU_MAP_STATS
915#endif
916#include "iommu-helpers.h"
917
918#ifdef DEBUG_LARGE_SG_ENTRIES
919int dump_run_sg = 0;
920#endif
921
922
923/**
924 * sba_map_sg - map Scatter/Gather list
925 * @dev: instance of PCI owned by the driver that's asking.
926 * @sglist: array of buffer/length pairs
927 * @nents: number of entries in list
928 * @direction: R/W or both.
929 *
930 * See Documentation/DMA-mapping.txt
931 */
932static int
933sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
934 enum dma_data_direction direction)
935{
936 struct ioc *ioc;
937 int coalesced, filled = 0;
938 unsigned long flags;
939
940 DBG_RUN_SG("%s() START %d entries\n", __FUNCTION__, nents);
941
942 ioc = GET_IOC(dev);
943
944 /* Fast path single entry scatterlists. */
945 if (nents == 1) {
946 sg_dma_address(sglist) = sba_map_single(dev,
947 (void *)sg_virt_addr(sglist),
948 sglist->length, direction);
949 sg_dma_len(sglist) = sglist->length;
950 return 1;
951 }
952
953 spin_lock_irqsave(&ioc->res_lock, flags);
954
955#ifdef ASSERT_PDIR_SANITY
956 if (sba_check_pdir(ioc,"Check before sba_map_sg()"))
957 {
958 sba_dump_sg(ioc, sglist, nents);
959 panic("Check before sba_map_sg()");
960 }
961#endif
962
963#ifdef SBA_COLLECT_STATS
964 ioc->msg_calls++;
965#endif
966
967 /*
968 ** First coalesce the chunks and allocate I/O pdir space
969 **
970 ** If this is one DMA stream, we can properly map using the
971 ** correct virtual address associated with each DMA page.
972 ** w/o this association, we wouldn't have coherent DMA!
973 ** Access to the virtual address is what forces a two pass algorithm.
974 */
FUJITA Tomonorid1b51632008-02-04 22:28:03 -0800975 coalesced = iommu_coalesce_chunks(ioc, dev, sglist, nents, sba_alloc_range);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700976
977 /*
978 ** Program the I/O Pdir
979 **
980 ** map the virtual addresses to the I/O Pdir
981 ** o dma_address will contain the pdir index
982 ** o dma_len will contain the number of bytes to map
983 ** o address contains the virtual address.
984 */
985 filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry);
986
Grant Grundler64908ad2005-10-21 22:37:20 -0400987 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
988 if (ioc_needs_fdc)
989 asm volatile("sync" : : );
990
Linus Torvalds1da177e2005-04-16 15:20:36 -0700991#ifdef ASSERT_PDIR_SANITY
992 if (sba_check_pdir(ioc,"Check after sba_map_sg()"))
993 {
994 sba_dump_sg(ioc, sglist, nents);
995 panic("Check after sba_map_sg()\n");
996 }
997#endif
998
999 spin_unlock_irqrestore(&ioc->res_lock, flags);
1000
1001 DBG_RUN_SG("%s() DONE %d mappings\n", __FUNCTION__, filled);
1002
1003 return filled;
1004}
1005
1006
1007/**
1008 * sba_unmap_sg - unmap Scatter/Gather list
1009 * @dev: instance of PCI owned by the driver that's asking.
1010 * @sglist: array of buffer/length pairs
1011 * @nents: number of entries in list
1012 * @direction: R/W or both.
1013 *
1014 * See Documentation/DMA-mapping.txt
1015 */
1016static void
1017sba_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents,
1018 enum dma_data_direction direction)
1019{
1020 struct ioc *ioc;
1021#ifdef ASSERT_PDIR_SANITY
1022 unsigned long flags;
1023#endif
1024
1025 DBG_RUN_SG("%s() START %d entries, %p,%x\n",
1026 __FUNCTION__, nents, sg_virt_addr(sglist), sglist->length);
1027
1028 ioc = GET_IOC(dev);
1029
1030#ifdef SBA_COLLECT_STATS
1031 ioc->usg_calls++;
1032#endif
1033
1034#ifdef ASSERT_PDIR_SANITY
1035 spin_lock_irqsave(&ioc->res_lock, flags);
1036 sba_check_pdir(ioc,"Check before sba_unmap_sg()");
1037 spin_unlock_irqrestore(&ioc->res_lock, flags);
1038#endif
1039
1040 while (sg_dma_len(sglist) && nents--) {
1041
1042 sba_unmap_single(dev, sg_dma_address(sglist), sg_dma_len(sglist), direction);
1043#ifdef SBA_COLLECT_STATS
1044 ioc->usg_pages += ((sg_dma_address(sglist) & ~IOVP_MASK) + sg_dma_len(sglist) + IOVP_SIZE - 1) >> PAGE_SHIFT;
1045 ioc->usingle_calls--; /* kluge since call is unmap_sg() */
1046#endif
1047 ++sglist;
1048 }
1049
1050 DBG_RUN_SG("%s() DONE (nents %d)\n", __FUNCTION__, nents);
1051
1052#ifdef ASSERT_PDIR_SANITY
1053 spin_lock_irqsave(&ioc->res_lock, flags);
1054 sba_check_pdir(ioc,"Check after sba_unmap_sg()");
1055 spin_unlock_irqrestore(&ioc->res_lock, flags);
1056#endif
1057
1058}
1059
1060static struct hppa_dma_ops sba_ops = {
1061 .dma_supported = sba_dma_supported,
1062 .alloc_consistent = sba_alloc_consistent,
1063 .alloc_noncoherent = sba_alloc_consistent,
1064 .free_consistent = sba_free_consistent,
1065 .map_single = sba_map_single,
1066 .unmap_single = sba_unmap_single,
1067 .map_sg = sba_map_sg,
1068 .unmap_sg = sba_unmap_sg,
1069 .dma_sync_single_for_cpu = NULL,
1070 .dma_sync_single_for_device = NULL,
1071 .dma_sync_sg_for_cpu = NULL,
1072 .dma_sync_sg_for_device = NULL,
1073};
1074
1075
1076/**************************************************************************
1077**
1078** SBA PAT PDC support
1079**
1080** o call pdc_pat_cell_module()
1081** o store ranges in PCI "resource" structures
1082**
1083**************************************************************************/
1084
1085static void
1086sba_get_pat_resources(struct sba_device *sba_dev)
1087{
1088#if 0
1089/*
1090** TODO/REVISIT/FIXME: support for directed ranges requires calls to
1091** PAT PDC to program the SBA/LBA directed range registers...this
1092** burden may fall on the LBA code since it directly supports the
1093** PCI subsystem. It's not clear yet. - ggg
1094*/
1095PAT_MOD(mod)->mod_info.mod_pages = PAT_GET_MOD_PAGES(temp);
1096 FIXME : ???
1097PAT_MOD(mod)->mod_info.dvi = PAT_GET_DVI(temp);
1098 Tells where the dvi bits are located in the address.
1099PAT_MOD(mod)->mod_info.ioc = PAT_GET_IOC(temp);
1100 FIXME : ???
1101#endif
1102}
1103
1104
1105/**************************************************************
1106*
1107* Initialization and claim
1108*
1109***************************************************************/
1110#define PIRANHA_ADDR_MASK 0x00160000UL /* bit 17,18,20 */
1111#define PIRANHA_ADDR_VAL 0x00060000UL /* bit 17,18 on */
1112static void *
1113sba_alloc_pdir(unsigned int pdir_size)
1114{
1115 unsigned long pdir_base;
1116 unsigned long pdir_order = get_order(pdir_size);
1117
1118 pdir_base = __get_free_pages(GFP_KERNEL, pdir_order);
Grant Grundler64908ad2005-10-21 22:37:20 -04001119 if (NULL == (void *) pdir_base) {
1120 panic("%s() could not allocate I/O Page Table\n",
1121 __FUNCTION__);
1122 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001123
1124 /* If this is not PA8700 (PCX-W2)
1125 ** OR newer than ver 2.2
1126 ** OR in a system that doesn't need VINDEX bits from SBA,
1127 **
1128 ** then we aren't exposed to the HW bug.
1129 */
1130 if ( ((boot_cpu_data.pdc.cpuid >> 5) & 0x7f) != 0x13
1131 || (boot_cpu_data.pdc.versions > 0x202)
1132 || (boot_cpu_data.pdc.capabilities & 0x08L) )
1133 return (void *) pdir_base;
1134
1135 /*
1136 * PA8700 (PCX-W2, aka piranha) silent data corruption fix
1137 *
1138 * An interaction between PA8700 CPU (Ver 2.2 or older) and
1139 * Ike/Astro can cause silent data corruption. This is only
1140 * a problem if the I/O PDIR is located in memory such that
1141 * (little-endian) bits 17 and 18 are on and bit 20 is off.
1142 *
1143 * Since the max IO Pdir size is 2MB, by cleverly allocating the
1144 * right physical address, we can either avoid (IOPDIR <= 1MB)
1145 * or minimize (2MB IO Pdir) the problem if we restrict the
1146 * IO Pdir to a maximum size of 2MB-128K (1902K).
1147 *
1148 * Because we always allocate 2^N sized IO pdirs, either of the
1149 * "bad" regions will be the last 128K if at all. That's easy
1150 * to test for.
1151 *
1152 */
1153 if (pdir_order <= (19-12)) {
1154 if (((virt_to_phys(pdir_base)+pdir_size-1) & PIRANHA_ADDR_MASK) == PIRANHA_ADDR_VAL) {
1155 /* allocate a new one on 512k alignment */
1156 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, (19-12));
1157 /* release original */
1158 free_pages(pdir_base, pdir_order);
1159
1160 pdir_base = new_pdir;
1161
1162 /* release excess */
1163 while (pdir_order < (19-12)) {
1164 new_pdir += pdir_size;
1165 free_pages(new_pdir, pdir_order);
1166 pdir_order +=1;
1167 pdir_size <<=1;
1168 }
1169 }
1170 } else {
1171 /*
1172 ** 1MB or 2MB Pdir
1173 ** Needs to be aligned on an "odd" 1MB boundary.
1174 */
1175 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, pdir_order+1); /* 2 or 4MB */
1176
1177 /* release original */
1178 free_pages( pdir_base, pdir_order);
1179
1180 /* release first 1MB */
1181 free_pages(new_pdir, 20-12);
1182
1183 pdir_base = new_pdir + 1024*1024;
1184
1185 if (pdir_order > (20-12)) {
1186 /*
1187 ** 2MB Pdir.
1188 **
1189 ** Flag tells init_bitmap() to mark bad 128k as used
1190 ** and to reduce the size by 128k.
1191 */
1192 piranha_bad_128k = 1;
1193
1194 new_pdir += 3*1024*1024;
1195 /* release last 1MB */
1196 free_pages(new_pdir, 20-12);
1197
1198 /* release unusable 128KB */
1199 free_pages(new_pdir - 128*1024 , 17-12);
1200
1201 pdir_size -= 128*1024;
1202 }
1203 }
1204
1205 memset((void *) pdir_base, 0, pdir_size);
1206 return (void *) pdir_base;
1207}
1208
Matthew Wilcox56583742005-10-21 22:33:38 -04001209static struct device *next_device(struct klist_iter *i)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001210{
Matthew Wilcox56583742005-10-21 22:33:38 -04001211 struct klist_node * n = klist_next(i);
1212 return n ? container_of(n, struct device, knode_parent) : NULL;
1213}
1214
1215/* setup Mercury or Elroy IBASE/IMASK registers. */
1216static void
1217setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1218{
1219 /* lba_set_iregs() is in drivers/parisc/lba_pci.c */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001220 extern void lba_set_iregs(struct parisc_device *, u32, u32);
1221 struct device *dev;
Matthew Wilcox56583742005-10-21 22:33:38 -04001222 struct klist_iter i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001223
Matthew Wilcox56583742005-10-21 22:33:38 -04001224 klist_iter_init(&sba->dev.klist_children, &i);
1225 while ((dev = next_device(&i))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001226 struct parisc_device *lba = to_parisc_device(dev);
Matthew Wilcox56583742005-10-21 22:33:38 -04001227 int rope_num = (lba->hpa.start >> 13) & 0xf;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001228 if (rope_num >> 3 == ioc_num)
1229 lba_set_iregs(lba, ioc->ibase, ioc->imask);
1230 }
Matthew Wilcox56583742005-10-21 22:33:38 -04001231 klist_iter_exit(&i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001232}
1233
1234static void
1235sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1236{
1237 u32 iova_space_mask;
1238 u32 iova_space_size;
1239 int iov_order, tcnfg;
Grant Grundler64908ad2005-10-21 22:37:20 -04001240#ifdef SBA_AGP_SUPPORT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001241 int agp_found = 0;
1242#endif
1243 /*
1244 ** Firmware programs the base and size of a "safe IOVA space"
1245 ** (one that doesn't overlap memory or LMMIO space) in the
1246 ** IBASE and IMASK registers.
1247 */
1248 ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE);
1249 iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1;
1250
1251 if ((ioc->ibase < 0xfed00000UL) && ((ioc->ibase + iova_space_size) > 0xfee00000UL)) {
1252 printk("WARNING: IOV space overlaps local config and interrupt message, truncating\n");
1253 iova_space_size /= 2;
1254 }
1255
1256 /*
1257 ** iov_order is always based on a 1GB IOVA space since we want to
1258 ** turn on the other half for AGP GART.
1259 */
1260 iov_order = get_order(iova_space_size >> (IOVP_SHIFT - PAGE_SHIFT));
1261 ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64);
1262
Grant Grundler40d78de2006-05-11 00:31:31 -06001263 DBG_INIT("%s() hpa 0x%p IOV %dMB (%d bits)\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001264 __FUNCTION__, ioc->ioc_hpa, iova_space_size >> 20,
1265 iov_order + PAGE_SHIFT);
1266
1267 ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL,
1268 get_order(ioc->pdir_size));
1269 if (!ioc->pdir_base)
1270 panic("Couldn't allocate I/O Page Table\n");
1271
1272 memset(ioc->pdir_base, 0, ioc->pdir_size);
1273
1274 DBG_INIT("%s() pdir %p size %x\n",
1275 __FUNCTION__, ioc->pdir_base, ioc->pdir_size);
1276
Grant Grundler64908ad2005-10-21 22:37:20 -04001277#ifdef SBA_HINT_SUPPORT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001278 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
1279 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
1280
1281 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
1282 ioc->hint_shift_pdir, ioc->hint_mask_pdir);
1283#endif
1284
1285 WARN_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base);
1286 WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1287
1288 /* build IMASK for IOC and Elroy */
1289 iova_space_mask = 0xffffffff;
1290 iova_space_mask <<= (iov_order + PAGE_SHIFT);
1291 ioc->imask = iova_space_mask;
1292#ifdef ZX1_SUPPORT
1293 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
1294#endif
1295 sba_dump_tlb(ioc->ioc_hpa);
1296
1297 setup_ibase_imask(sba, ioc, ioc_num);
1298
1299 WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK);
1300
Grant Grundler64908ad2005-10-21 22:37:20 -04001301#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001302 /*
1303 ** Setting the upper bits makes checking for bypass addresses
1304 ** a little faster later on.
1305 */
1306 ioc->imask |= 0xFFFFFFFF00000000UL;
1307#endif
1308
1309 /* Set I/O PDIR Page size to system page size */
1310 switch (PAGE_SHIFT) {
1311 case 12: tcnfg = 0; break; /* 4K */
1312 case 13: tcnfg = 1; break; /* 8K */
1313 case 14: tcnfg = 2; break; /* 16K */
1314 case 16: tcnfg = 3; break; /* 64K */
1315 default:
1316 panic(__FILE__ "Unsupported system page size %d",
1317 1 << PAGE_SHIFT);
1318 break;
1319 }
1320 WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG);
1321
1322 /*
1323 ** Program the IOC's ibase and enable IOVA translation
1324 ** Bit zero == enable bit.
1325 */
1326 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE);
1327
1328 /*
1329 ** Clear I/O TLB of any possible entries.
1330 ** (Yes. This is a bit paranoid...but so what)
1331 */
1332 WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM);
1333
Grant Grundler64908ad2005-10-21 22:37:20 -04001334#ifdef SBA_AGP_SUPPORT
Kyle McMartin08a64362006-08-24 21:33:40 -04001335{
1336 struct klist_iter i;
1337 struct device *dev = NULL;
1338
Linus Torvalds1da177e2005-04-16 15:20:36 -07001339 /*
1340 ** If an AGP device is present, only use half of the IOV space
1341 ** for PCI DMA. Unfortunately we can't know ahead of time
1342 ** whether GART support will actually be used, for now we
1343 ** can just key on any AGP device found in the system.
1344 ** We program the next pdir index after we stop w/ a key for
1345 ** the GART code to handshake on.
1346 */
Kyle McMartin08a64362006-08-24 21:33:40 -04001347 klist_iter_init(&sba->dev.klist_children, &i);
Matthew Wilcoxee9f4b52006-10-04 13:08:33 -06001348 while ((dev = next_device(&i))) {
Kyle McMartin08a64362006-08-24 21:33:40 -04001349 struct parisc_device *lba = to_parisc_device(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001350 if (IS_QUICKSILVER(lba))
Kyle McMartin08a64362006-08-24 21:33:40 -04001351 agp_found = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001352 }
Matthew Wilcoxee9f4b52006-10-04 13:08:33 -06001353 klist_iter_exit(&i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001354
Kyle McMartin08a64362006-08-24 21:33:40 -04001355 if (agp_found && sba_reserve_agpgart) {
1356 printk(KERN_INFO "%s: reserving %dMb of IOVA space for agpgart\n",
1357 __FUNCTION__, (iova_space_size/2) >> 20);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001358 ioc->pdir_size /= 2;
Kyle McMartin08a64362006-08-24 21:33:40 -04001359 ioc->pdir_base[PDIR_INDEX(iova_space_size/2)] = SBA_AGPGART_COOKIE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001360 }
Kyle McMartin08a64362006-08-24 21:33:40 -04001361}
1362#endif /*SBA_AGP_SUPPORT*/
Linus Torvalds1da177e2005-04-16 15:20:36 -07001363
1364}
1365
1366static void
1367sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1368{
1369 u32 iova_space_size, iova_space_mask;
1370 unsigned int pdir_size, iov_order;
1371
1372 /*
1373 ** Determine IOVA Space size from memory size.
1374 **
1375 ** Ideally, PCI drivers would register the maximum number
1376 ** of DMA they can have outstanding for each device they
1377 ** own. Next best thing would be to guess how much DMA
1378 ** can be outstanding based on PCI Class/sub-class. Both
1379 ** methods still require some "extra" to support PCI
1380 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD).
1381 **
1382 ** While we have 32-bits "IOVA" space, top two 2 bits are used
1383 ** for DMA hints - ergo only 30 bits max.
1384 */
1385
1386 iova_space_size = (u32) (num_physpages/global_ioc_cnt);
1387
1388 /* limit IOVA space size to 1MB-1GB */
1389 if (iova_space_size < (1 << (20 - PAGE_SHIFT))) {
1390 iova_space_size = 1 << (20 - PAGE_SHIFT);
1391 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001392 else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) {
1393 iova_space_size = 1 << (30 - PAGE_SHIFT);
1394 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001395
1396 /*
1397 ** iova space must be log2() in size.
1398 ** thus, pdir/res_map will also be log2().
1399 ** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced)
1400 */
1401 iov_order = get_order(iova_space_size << PAGE_SHIFT);
1402
1403 /* iova_space_size is now bytes, not pages */
1404 iova_space_size = 1 << (iov_order + PAGE_SHIFT);
1405
1406 ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64);
1407
1408 DBG_INIT("%s() hpa 0x%lx mem %ldMB IOV %dMB (%d bits)\n",
1409 __FUNCTION__,
1410 ioc->ioc_hpa,
1411 (unsigned long) num_physpages >> (20 - PAGE_SHIFT),
1412 iova_space_size>>20,
1413 iov_order + PAGE_SHIFT);
1414
1415 ioc->pdir_base = sba_alloc_pdir(pdir_size);
1416
1417 DBG_INIT("%s() pdir %p size %x\n",
1418 __FUNCTION__, ioc->pdir_base, pdir_size);
1419
Grant Grundler64908ad2005-10-21 22:37:20 -04001420#ifdef SBA_HINT_SUPPORT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001421 /* FIXME : DMA HINTs not used */
1422 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
1423 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
1424
1425 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
1426 ioc->hint_shift_pdir, ioc->hint_mask_pdir);
1427#endif
1428
1429 WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1430
1431 /* build IMASK for IOC and Elroy */
1432 iova_space_mask = 0xffffffff;
1433 iova_space_mask <<= (iov_order + PAGE_SHIFT);
1434
1435 /*
1436 ** On C3000 w/512MB mem, HP-UX 10.20 reports:
1437 ** ibase=0, imask=0xFE000000, size=0x2000000.
1438 */
1439 ioc->ibase = 0;
1440 ioc->imask = iova_space_mask; /* save it */
1441#ifdef ZX1_SUPPORT
1442 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
1443#endif
1444
1445 DBG_INIT("%s() IOV base 0x%lx mask 0x%0lx\n",
1446 __FUNCTION__, ioc->ibase, ioc->imask);
1447
1448 /*
1449 ** FIXME: Hint registers are programmed with default hint
1450 ** values during boot, so hints should be sane even if we
1451 ** can't reprogram them the way drivers want.
1452 */
1453
1454 setup_ibase_imask(sba, ioc, ioc_num);
1455
1456 /*
1457 ** Program the IOC's ibase and enable IOVA translation
1458 */
1459 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE);
1460 WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK);
1461
1462 /* Set I/O PDIR Page size to 4K */
1463 WRITE_REG(0, ioc->ioc_hpa+IOC_TCNFG);
1464
1465 /*
1466 ** Clear I/O TLB of any possible entries.
1467 ** (Yes. This is a bit paranoid...but so what)
1468 */
1469 WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM);
1470
1471 ioc->ibase = 0; /* used by SBA_IOVA and related macros */
1472
1473 DBG_INIT("%s() DONE\n", __FUNCTION__);
1474}
1475
1476
1477
1478/**************************************************************************
1479**
1480** SBA initialization code (HW and SW)
1481**
1482** o identify SBA chip itself
1483** o initialize SBA chip modes (HardFail)
1484** o initialize SBA chip modes (HardFail)
1485** o FIXME: initialize DMA hints for reasonable defaults
1486**
1487**************************************************************************/
1488
Helge Deller5076c152006-03-27 12:52:15 -07001489static void __iomem *ioc_remap(struct sba_device *sba_dev, unsigned int offset)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001490{
Helge Deller5076c152006-03-27 12:52:15 -07001491 return ioremap_nocache(sba_dev->dev->hpa.start + offset, SBA_FUNC_SIZE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001492}
1493
1494static void sba_hw_init(struct sba_device *sba_dev)
1495{
1496 int i;
1497 int num_ioc;
1498 u64 ioc_ctl;
1499
1500 if (!is_pdc_pat()) {
1501 /* Shutdown the USB controller on Astro-based workstations.
1502 ** Once we reprogram the IOMMU, the next DMA performed by
1503 ** USB will HPMC the box. USB is only enabled if a
1504 ** keyboard is present and found.
1505 **
1506 ** With serial console, j6k v5.0 firmware says:
1507 ** mem_kbd hpa 0xfee003f8 sba 0x0 pad 0x0 cl_class 0x7
1508 **
1509 ** FIXME: Using GFX+USB console at power up but direct
1510 ** linux to serial console is still broken.
1511 ** USB could generate DMA so we must reset USB.
1512 ** The proper sequence would be:
1513 ** o block console output
1514 ** o reset USB device
1515 ** o reprogram serial port
1516 ** o unblock console output
1517 */
1518 if (PAGE0->mem_kbd.cl_class == CL_KEYBD) {
1519 pdc_io_reset_devices();
1520 }
1521
1522 }
1523
1524
1525#if 0
1526printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa,
1527 PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class);
1528
1529 /*
1530 ** Need to deal with DMA from LAN.
1531 ** Maybe use page zero boot device as a handle to talk
1532 ** to PDC about which device to shutdown.
1533 **
1534 ** Netbooting, j6k v5.0 firmware says:
1535 ** mem_boot hpa 0xf4008000 sba 0x0 pad 0x0 cl_class 0x1002
1536 ** ARGH! invalid class.
1537 */
1538 if ((PAGE0->mem_boot.cl_class != CL_RANDOM)
1539 && (PAGE0->mem_boot.cl_class != CL_SEQU)) {
1540 pdc_io_reset();
1541 }
1542#endif
1543
Kyle McMartin1b240f42006-08-24 21:30:19 -04001544 if (!IS_PLUTO(sba_dev->dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001545 ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL);
1546 DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->",
1547 __FUNCTION__, sba_dev->sba_hpa, ioc_ctl);
1548 ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE);
1549 ioc_ctl |= IOC_CTRL_DD | IOC_CTRL_D4 | IOC_CTRL_TC;
1550 /* j6700 v1.6 firmware sets 0x294f */
1551 /* A500 firmware sets 0x4d */
1552
1553 WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL);
1554
1555#ifdef DEBUG_SBA_INIT
1556 ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL);
1557 DBG_INIT(" 0x%Lx\n", ioc_ctl);
1558#endif
1559 } /* if !PLUTO */
1560
Kyle McMartin1b240f42006-08-24 21:30:19 -04001561 if (IS_ASTRO(sba_dev->dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001562 int err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001563 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, ASTRO_IOC_OFFSET);
1564 num_ioc = 1;
1565
1566 sba_dev->chip_resv.name = "Astro Intr Ack";
1567 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfef00000UL;
1568 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff000000UL - 1) ;
1569 err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
Eric Sesterhennb7494552006-03-24 18:52:10 +01001570 BUG_ON(err < 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001571
Kyle McMartin1b240f42006-08-24 21:30:19 -04001572 } else if (IS_PLUTO(sba_dev->dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001573 int err;
1574
Linus Torvalds1da177e2005-04-16 15:20:36 -07001575 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, PLUTO_IOC_OFFSET);
1576 num_ioc = 1;
1577
1578 sba_dev->chip_resv.name = "Pluto Intr/PIOP/VGA";
1579 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfee00000UL;
1580 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff200000UL - 1);
1581 err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
1582 WARN_ON(err < 0);
1583
1584 sba_dev->iommu_resv.name = "IOVA Space";
1585 sba_dev->iommu_resv.start = 0x40000000UL;
1586 sba_dev->iommu_resv.end = 0x50000000UL - 1;
1587 err = request_resource(&iomem_resource, &(sba_dev->iommu_resv));
1588 WARN_ON(err < 0);
1589 } else {
Matthew Wilcox78860892006-09-12 05:19:15 -06001590 /* IKE, REO */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001591 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(0));
1592 sba_dev->ioc[1].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(1));
1593 num_ioc = 2;
1594
1595 /* TODO - LOOKUP Ike/Stretch chipset mem map */
1596 }
Matthew Wilcox78860892006-09-12 05:19:15 -06001597 /* XXX: What about Reo Grande? */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001598
1599 sba_dev->num_ioc = num_ioc;
1600 for (i = 0; i < num_ioc; i++) {
Grant Grundler40d78de2006-05-11 00:31:31 -06001601 void __iomem *ioc_hpa = sba_dev->ioc[i].ioc_hpa;
Grant Grundlerb312c332006-03-30 07:13:21 +00001602 unsigned int j;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001603
Grant Grundlerb312c332006-03-30 07:13:21 +00001604 for (j=0; j < sizeof(u64) * ROPES_PER_IOC; j+=sizeof(u64)) {
1605
1606 /*
1607 * Clear ROPE(N)_CONFIG AO bit.
1608 * Disables "NT Ordering" (~= !"Relaxed Ordering")
1609 * Overrides bit 1 in DMA Hint Sets.
1610 * Improves netperf UDP_STREAM by ~10% for bcm5701.
1611 */
Kyle McMartin1b240f42006-08-24 21:30:19 -04001612 if (IS_PLUTO(sba_dev->dev)) {
Grant Grundler40d78de2006-05-11 00:31:31 -06001613 void __iomem *rope_cfg;
1614 unsigned long cfg_val;
Grant Grundlerb312c332006-03-30 07:13:21 +00001615
1616 rope_cfg = ioc_hpa + IOC_ROPE0_CFG + j;
1617 cfg_val = READ_REG(rope_cfg);
1618 cfg_val &= ~IOC_ROPE_AO;
1619 WRITE_REG(cfg_val, rope_cfg);
1620 }
1621
1622 /*
1623 ** Make sure the box crashes on rope errors.
1624 */
1625 WRITE_REG(HF_ENABLE, ioc_hpa + ROPE0_CTL + j);
1626 }
1627
1628 /* flush out the last writes */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001629 READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
1630
1631 DBG_INIT(" ioc[%d] ROPE_CFG 0x%Lx ROPE_DBG 0x%Lx\n",
1632 i,
1633 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40),
1634 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50)
1635 );
1636 DBG_INIT(" STATUS_CONTROL 0x%Lx FLUSH_CTRL 0x%Lx\n",
1637 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108),
1638 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400)
1639 );
1640
Kyle McMartin1b240f42006-08-24 21:30:19 -04001641 if (IS_PLUTO(sba_dev->dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001642 sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i);
1643 } else {
1644 sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i);
1645 }
1646 }
1647}
1648
1649static void
1650sba_common_init(struct sba_device *sba_dev)
1651{
1652 int i;
1653
1654 /* add this one to the head of the list (order doesn't matter)
1655 ** This will be useful for debugging - especially if we get coredumps
1656 */
1657 sba_dev->next = sba_list;
1658 sba_list = sba_dev;
1659
1660 for(i=0; i< sba_dev->num_ioc; i++) {
1661 int res_size;
1662#ifdef DEBUG_DMB_TRAP
1663 extern void iterate_pages(unsigned long , unsigned long ,
1664 void (*)(pte_t * , unsigned long),
1665 unsigned long );
1666 void set_data_memory_break(pte_t * , unsigned long);
1667#endif
1668 /* resource map size dictated by pdir_size */
1669 res_size = sba_dev->ioc[i].pdir_size/sizeof(u64); /* entries */
1670
1671 /* Second part of PIRANHA BUG */
1672 if (piranha_bad_128k) {
1673 res_size -= (128*1024)/sizeof(u64);
1674 }
1675
1676 res_size >>= 3; /* convert bit count to byte count */
1677 DBG_INIT("%s() res_size 0x%x\n",
1678 __FUNCTION__, res_size);
1679
1680 sba_dev->ioc[i].res_size = res_size;
1681 sba_dev->ioc[i].res_map = (char *) __get_free_pages(GFP_KERNEL, get_order(res_size));
1682
1683#ifdef DEBUG_DMB_TRAP
1684 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1685 set_data_memory_break, 0);
1686#endif
1687
1688 if (NULL == sba_dev->ioc[i].res_map)
1689 {
1690 panic("%s:%s() could not allocate resource map\n",
1691 __FILE__, __FUNCTION__ );
1692 }
1693
1694 memset(sba_dev->ioc[i].res_map, 0, res_size);
1695 /* next available IOVP - circular search */
1696 sba_dev->ioc[i].res_hint = (unsigned long *)
1697 &(sba_dev->ioc[i].res_map[L1_CACHE_BYTES]);
1698
1699#ifdef ASSERT_PDIR_SANITY
1700 /* Mark first bit busy - ie no IOVA 0 */
1701 sba_dev->ioc[i].res_map[0] = 0x80;
1702 sba_dev->ioc[i].pdir_base[0] = 0xeeffc0addbba0080ULL;
1703#endif
1704
1705 /* Third (and last) part of PIRANHA BUG */
1706 if (piranha_bad_128k) {
1707 /* region from +1408K to +1536 is un-usable. */
1708
1709 int idx_start = (1408*1024/sizeof(u64)) >> 3;
1710 int idx_end = (1536*1024/sizeof(u64)) >> 3;
1711 long *p_start = (long *) &(sba_dev->ioc[i].res_map[idx_start]);
1712 long *p_end = (long *) &(sba_dev->ioc[i].res_map[idx_end]);
1713
1714 /* mark that part of the io pdir busy */
1715 while (p_start < p_end)
1716 *p_start++ = -1;
1717
1718 }
1719
1720#ifdef DEBUG_DMB_TRAP
1721 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1722 set_data_memory_break, 0);
1723 iterate_pages( sba_dev->ioc[i].pdir_base, sba_dev->ioc[i].pdir_size,
1724 set_data_memory_break, 0);
1725#endif
1726
1727 DBG_INIT("%s() %d res_map %x %p\n",
1728 __FUNCTION__, i, res_size, sba_dev->ioc[i].res_map);
1729 }
1730
1731 spin_lock_init(&sba_dev->sba_lock);
1732 ioc_needs_fdc = boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC;
1733
1734#ifdef DEBUG_SBA_INIT
1735 /*
1736 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
1737 * (bit #61, big endian), we have to flush and sync every time
1738 * IO-PDIR is changed in Ike/Astro.
1739 */
Kyle McMartin692086e2006-05-30 17:50:29 +00001740 if (ioc_needs_fdc) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001741 printk(KERN_INFO MODULE_NAME " FDC/SYNC required.\n");
1742 } else {
1743 printk(KERN_INFO MODULE_NAME " IOC has cache coherent PDIR.\n");
1744 }
1745#endif
1746}
1747
1748#ifdef CONFIG_PROC_FS
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001749static int sba_proc_info(struct seq_file *m, void *p)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001750{
1751 struct sba_device *sba_dev = sba_list;
1752 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
1753 int total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001754#ifdef SBA_COLLECT_STATS
1755 unsigned long avg = 0, min, max;
1756#endif
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001757 int i, len = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001758
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001759 len += seq_printf(m, "%s rev %d.%d\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001760 sba_dev->name,
1761 (sba_dev->hw_rev & 0x7) + 1,
1762 (sba_dev->hw_rev & 0x18) >> 3
1763 );
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001764 len += seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001765 (int) ((ioc->res_size << 3) * sizeof(u64)), /* 8 bits/byte */
1766 total_pages);
1767
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001768 len += seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n",
1769 ioc->res_size, ioc->res_size << 3); /* 8 bits per byte */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001770
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001771 len += seq_printf(m, "LMMIO_BASE/MASK/ROUTE %08x %08x %08x\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001772 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_BASE),
1773 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_MASK),
1774 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_ROUTE)
1775 );
1776
1777 for (i=0; i<4; i++)
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001778 len += seq_printf(m, "DIR%d_BASE/MASK/ROUTE %08x %08x %08x\n", i,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001779 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_BASE + i*0x18),
1780 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_MASK + i*0x18),
1781 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_ROUTE + i*0x18)
1782 );
1783
1784#ifdef SBA_COLLECT_STATS
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001785 len += seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001786 total_pages - ioc->used_pages, ioc->used_pages,
1787 (int) (ioc->used_pages * 100 / total_pages));
1788
1789 min = max = ioc->avg_search[0];
1790 for (i = 0; i < SBA_SEARCH_SAMPLE; i++) {
1791 avg += ioc->avg_search[i];
1792 if (ioc->avg_search[i] > max) max = ioc->avg_search[i];
1793 if (ioc->avg_search[i] < min) min = ioc->avg_search[i];
1794 }
1795 avg /= SBA_SEARCH_SAMPLE;
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001796 len += seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n",
1797 min, avg, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001798
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001799 len += seq_printf(m, "pci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n",
1800 ioc->msingle_calls, ioc->msingle_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001801 (int) ((ioc->msingle_pages * 1000)/ioc->msingle_calls));
1802
1803 /* KLUGE - unmap_sg calls unmap_single for each mapped page */
1804 min = ioc->usingle_calls;
1805 max = ioc->usingle_pages - ioc->usg_pages;
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001806 len += seq_printf(m, "pci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n",
1807 min, max, (int) ((max * 1000)/min));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001808
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001809 len += seq_printf(m, "pci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1810 ioc->msg_calls, ioc->msg_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001811 (int) ((ioc->msg_pages * 1000)/ioc->msg_calls));
1812
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001813 len += seq_printf(m, "pci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1814 ioc->usg_calls, ioc->usg_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001815 (int) ((ioc->usg_pages * 1000)/ioc->usg_calls));
1816#endif
1817
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001818 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001819}
1820
Linus Torvalds1da177e2005-04-16 15:20:36 -07001821static int
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001822sba_proc_open(struct inode *i, struct file *f)
1823{
1824 return single_open(f, &sba_proc_info, NULL);
1825}
1826
Arjan van de Vend54b1fd2007-02-12 00:55:34 -08001827static const struct file_operations sba_proc_fops = {
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001828 .owner = THIS_MODULE,
1829 .open = sba_proc_open,
1830 .read = seq_read,
1831 .llseek = seq_lseek,
1832 .release = single_release,
1833};
1834
1835static int
1836sba_proc_bitmap_info(struct seq_file *m, void *p)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001837{
1838 struct sba_device *sba_dev = sba_list;
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001839 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001840 unsigned int *res_ptr = (unsigned int *)ioc->res_map;
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001841 int i, len = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001842
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001843 for (i = 0; i < (ioc->res_size/sizeof(unsigned int)); ++i, ++res_ptr) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001844 if ((i & 7) == 0)
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001845 len += seq_printf(m, "\n ");
1846 len += seq_printf(m, " %08x", *res_ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001847 }
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001848 len += seq_printf(m, "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001849
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001850 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001851}
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001852
1853static int
1854sba_proc_bitmap_open(struct inode *i, struct file *f)
1855{
1856 return single_open(f, &sba_proc_bitmap_info, NULL);
1857}
1858
Arjan van de Vend54b1fd2007-02-12 00:55:34 -08001859static const struct file_operations sba_proc_bitmap_fops = {
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001860 .owner = THIS_MODULE,
1861 .open = sba_proc_bitmap_open,
1862 .read = seq_read,
1863 .llseek = seq_lseek,
1864 .release = single_release,
1865};
Linus Torvalds1da177e2005-04-16 15:20:36 -07001866#endif /* CONFIG_PROC_FS */
1867
1868static struct parisc_device_id sba_tbl[] = {
1869 { HPHW_IOA, HVERSION_REV_ANY_ID, ASTRO_RUNWAY_PORT, 0xb },
1870 { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc },
1871 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc },
1872 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc },
1873 { HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc },
1874 { 0, }
1875};
1876
1877int sba_driver_callback(struct parisc_device *);
1878
1879static struct parisc_driver sba_driver = {
1880 .name = MODULE_NAME,
1881 .id_table = sba_tbl,
1882 .probe = sba_driver_callback,
1883};
1884
1885/*
1886** Determine if sba should claim this chip (return 0) or not (return 1).
1887** If so, initialize the chip and tell other partners in crime they
1888** have work to do.
1889*/
1890int
1891sba_driver_callback(struct parisc_device *dev)
1892{
1893 struct sba_device *sba_dev;
1894 u32 func_class;
1895 int i;
1896 char *version;
Helge Deller5076c152006-03-27 12:52:15 -07001897 void __iomem *sba_addr = ioremap_nocache(dev->hpa.start, SBA_FUNC_SIZE);
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001898 struct proc_dir_entry *info_entry, *bitmap_entry, *root;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001899
1900 sba_dump_ranges(sba_addr);
1901
1902 /* Read HW Rev First */
1903 func_class = READ_REG(sba_addr + SBA_FCLASS);
1904
Kyle McMartin1b240f42006-08-24 21:30:19 -04001905 if (IS_ASTRO(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001906 unsigned long fclass;
1907 static char astro_rev[]="Astro ?.?";
1908
1909 /* Astro is broken...Read HW Rev First */
1910 fclass = READ_REG(sba_addr);
1911
1912 astro_rev[6] = '1' + (char) (fclass & 0x7);
1913 astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3);
1914 version = astro_rev;
1915
Kyle McMartin1b240f42006-08-24 21:30:19 -04001916 } else if (IS_IKE(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001917 static char ike_rev[] = "Ike rev ?";
1918 ike_rev[8] = '0' + (char) (func_class & 0xff);
1919 version = ike_rev;
Kyle McMartin1b240f42006-08-24 21:30:19 -04001920 } else if (IS_PLUTO(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001921 static char pluto_rev[]="Pluto ?.?";
1922 pluto_rev[6] = '0' + (char) ((func_class & 0xf0) >> 4);
1923 pluto_rev[8] = '0' + (char) (func_class & 0x0f);
1924 version = pluto_rev;
1925 } else {
1926 static char reo_rev[] = "REO rev ?";
1927 reo_rev[8] = '0' + (char) (func_class & 0xff);
1928 version = reo_rev;
1929 }
1930
1931 if (!global_ioc_cnt) {
1932 global_ioc_cnt = count_parisc_driver(&sba_driver);
1933
1934 /* Astro and Pluto have one IOC per SBA */
Kyle McMartin1b240f42006-08-24 21:30:19 -04001935 if ((!IS_ASTRO(dev)) || (!IS_PLUTO(dev)))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001936 global_ioc_cnt *= 2;
1937 }
1938
Kyle McMartine9a03992007-10-18 00:04:00 -07001939 printk(KERN_INFO "%s found %s at 0x%llx\n",
1940 MODULE_NAME, version, (unsigned long long)dev->hpa.start);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001941
Helge Dellercb6fc182006-01-17 12:40:40 -07001942 sba_dev = kzalloc(sizeof(struct sba_device), GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001943 if (!sba_dev) {
1944 printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n");
1945 return -ENOMEM;
1946 }
1947
1948 parisc_set_drvdata(dev, sba_dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001949
1950 for(i=0; i<MAX_IOC; i++)
1951 spin_lock_init(&(sba_dev->ioc[i].res_lock));
1952
1953 sba_dev->dev = dev;
1954 sba_dev->hw_rev = func_class;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001955 sba_dev->name = dev->name;
1956 sba_dev->sba_hpa = sba_addr;
1957
1958 sba_get_pat_resources(sba_dev);
1959 sba_hw_init(sba_dev);
1960 sba_common_init(sba_dev);
1961
1962 hppa_dma_ops = &sba_ops;
1963
1964#ifdef CONFIG_PROC_FS
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001965 switch (dev->id.hversion) {
1966 case PLUTO_MCKINLEY_PORT:
1967 root = proc_mckinley_root;
1968 break;
1969 case ASTRO_RUNWAY_PORT:
1970 case IKE_MERCED_PORT:
1971 default:
1972 root = proc_runway_root;
1973 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001974 }
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001975
1976 info_entry = create_proc_entry("sba_iommu", 0, root);
1977 bitmap_entry = create_proc_entry("sba_iommu-bitmap", 0, root);
1978
1979 if (info_entry)
1980 info_entry->proc_fops = &sba_proc_fops;
1981
1982 if (bitmap_entry)
1983 bitmap_entry->proc_fops = &sba_proc_bitmap_fops;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001984#endif
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001985
Linus Torvalds1da177e2005-04-16 15:20:36 -07001986 parisc_vmerge_boundary = IOVP_SIZE;
1987 parisc_vmerge_max_size = IOVP_SIZE * BITS_PER_LONG;
1988 parisc_has_iommu();
1989 return 0;
1990}
1991
1992/*
1993** One time initialization to let the world know the SBA was found.
1994** This is the only routine which is NOT static.
1995** Must be called exactly once before pci_init().
1996*/
1997void __init sba_init(void)
1998{
1999 register_parisc_driver(&sba_driver);
2000}
2001
2002
2003/**
2004 * sba_get_iommu - Assign the iommu pointer for the pci bus controller.
2005 * @dev: The parisc device.
2006 *
2007 * Returns the appropriate IOMMU data for the given parisc PCI controller.
2008 * This is cached and used later for PCI DMA Mapping.
2009 */
2010void * sba_get_iommu(struct parisc_device *pci_hba)
2011{
2012 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2013 struct sba_device *sba = sba_dev->dev.driver_data;
2014 char t = sba_dev->id.hw_type;
2015 int iocnum = (pci_hba->hw_path >> 3); /* rope # */
2016
2017 WARN_ON((t != HPHW_IOA) && (t != HPHW_BCPORT));
2018
2019 return &(sba->ioc[iocnum]);
2020}
2021
2022
2023/**
2024 * sba_directed_lmmio - return first directed LMMIO range routed to rope
2025 * @pa_dev: The parisc device.
2026 * @r: resource PCI host controller wants start/end fields assigned.
2027 *
2028 * For the given parisc PCI controller, determine if any direct ranges
2029 * are routed down the corresponding rope.
2030 */
2031void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r)
2032{
2033 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2034 struct sba_device *sba = sba_dev->dev.driver_data;
2035 char t = sba_dev->id.hw_type;
2036 int i;
2037 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
2038
Eric Sesterhennb7494552006-03-24 18:52:10 +01002039 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002040
2041 r->start = r->end = 0;
2042
2043 /* Astro has 4 directed ranges. Not sure about Ike/Pluto/et al */
2044 for (i=0; i<4; i++) {
2045 int base, size;
2046 void __iomem *reg = sba->sba_hpa + i*0x18;
2047
2048 base = READ_REG32(reg + LMMIO_DIRECT0_BASE);
2049 if ((base & 1) == 0)
2050 continue; /* not enabled */
2051
2052 size = READ_REG32(reg + LMMIO_DIRECT0_ROUTE);
2053
2054 if ((size & (ROPES_PER_IOC-1)) != rope)
2055 continue; /* directed down different rope */
2056
2057 r->start = (base & ~1UL) | PCI_F_EXTEND;
2058 size = ~ READ_REG32(reg + LMMIO_DIRECT0_MASK);
2059 r->end = r->start + size;
2060 }
2061}
2062
2063
2064/**
2065 * sba_distributed_lmmio - return portion of distributed LMMIO range
2066 * @pa_dev: The parisc device.
2067 * @r: resource PCI host controller wants start/end fields assigned.
2068 *
2069 * For the given parisc PCI controller, return portion of distributed LMMIO
2070 * range. The distributed LMMIO is always present and it's just a question
2071 * of the base address and size of the range.
2072 */
2073void sba_distributed_lmmio(struct parisc_device *pci_hba, struct resource *r )
2074{
2075 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2076 struct sba_device *sba = sba_dev->dev.driver_data;
2077 char t = sba_dev->id.hw_type;
2078 int base, size;
2079 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
2080
Eric Sesterhennb7494552006-03-24 18:52:10 +01002081 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002082
2083 r->start = r->end = 0;
2084
2085 base = READ_REG32(sba->sba_hpa + LMMIO_DIST_BASE);
2086 if ((base & 1) == 0) {
2087 BUG(); /* Gah! Distr Range wasn't enabled! */
2088 return;
2089 }
2090
2091 r->start = (base & ~1UL) | PCI_F_EXTEND;
2092
2093 size = (~READ_REG32(sba->sba_hpa + LMMIO_DIST_MASK)) / ROPES_PER_IOC;
2094 r->start += rope * (size + 1); /* adjust base for this rope */
2095 r->end = r->start + size;
2096}