Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 1 | /* |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 2 | * Copyright 2012 Red Hat Inc. |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
| 24 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 25 | #include <core/client.h> |
| 26 | #include <core/handle.h> |
| 27 | #include <core/namedb.h> |
| 28 | #include <core/gpuobj.h> |
| 29 | #include <core/engctx.h> |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 30 | #include <core/event.h> |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 31 | #include <core/class.h> |
| 32 | #include <core/math.h> |
| 33 | #include <core/enum.h> |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 34 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 35 | #include <subdev/timer.h> |
| 36 | #include <subdev/bar.h> |
| 37 | #include <subdev/vm.h> |
| 38 | |
| 39 | #include <engine/dmaobj.h> |
Ben Skeggs | 02a841d | 2012-07-04 23:44:54 +1000 | [diff] [blame] | 40 | #include <engine/fifo.h> |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 41 | |
Martin Peres | 507ceb1 | 2012-11-27 00:30:32 +0100 | [diff] [blame] | 42 | #define _(a,b) { (a), ((1ULL << (a)) | (b)) } |
Ben Skeggs | dbff2de | 2012-08-06 18:16:37 +1000 | [diff] [blame] | 43 | static const struct { |
Martin Peres | 507ceb1 | 2012-11-27 00:30:32 +0100 | [diff] [blame] | 44 | u64 subdev; |
| 45 | u64 mask; |
Ben Skeggs | dbff2de | 2012-08-06 18:16:37 +1000 | [diff] [blame] | 46 | } fifo_engine[] = { |
Ben Skeggs | 48506d1 | 2013-04-29 09:36:42 +1000 | [diff] [blame] | 47 | _(NVDEV_ENGINE_GR , (1ULL << NVDEV_ENGINE_SW) | |
| 48 | (1ULL << NVDEV_ENGINE_COPY2)), |
Ben Skeggs | dbff2de | 2012-08-06 18:16:37 +1000 | [diff] [blame] | 49 | _(NVDEV_ENGINE_VP , 0), |
| 50 | _(NVDEV_ENGINE_PPP , 0), |
| 51 | _(NVDEV_ENGINE_BSP , 0), |
| 52 | _(NVDEV_ENGINE_COPY0 , 0), |
| 53 | _(NVDEV_ENGINE_COPY1 , 0), |
| 54 | _(NVDEV_ENGINE_VENC , 0), |
| 55 | }; |
| 56 | #undef _ |
| 57 | #define FIFO_ENGINE_NR ARRAY_SIZE(fifo_engine) |
| 58 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 59 | struct nve0_fifo_engn { |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 60 | struct nouveau_gpuobj *playlist[2]; |
| 61 | int cur_playlist; |
| 62 | }; |
| 63 | |
| 64 | struct nve0_fifo_priv { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 65 | struct nouveau_fifo base; |
Ben Skeggs | dbff2de | 2012-08-06 18:16:37 +1000 | [diff] [blame] | 66 | struct nve0_fifo_engn engine[FIFO_ENGINE_NR]; |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 67 | struct { |
| 68 | struct nouveau_gpuobj *mem; |
| 69 | struct nouveau_vma bar; |
| 70 | } user; |
| 71 | int spoon_nr; |
| 72 | }; |
| 73 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 74 | struct nve0_fifo_base { |
| 75 | struct nouveau_fifo_base base; |
| 76 | struct nouveau_gpuobj *pgd; |
| 77 | struct nouveau_vm *vm; |
| 78 | }; |
| 79 | |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 80 | struct nve0_fifo_chan { |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 81 | struct nouveau_fifo_chan base; |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 82 | u32 engine; |
| 83 | }; |
| 84 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 85 | /******************************************************************************* |
| 86 | * FIFO channel objects |
| 87 | ******************************************************************************/ |
| 88 | |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 89 | static void |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 90 | nve0_fifo_playlist_update(struct nve0_fifo_priv *priv, u32 engine) |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 91 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 92 | struct nouveau_bar *bar = nouveau_bar(priv); |
| 93 | struct nve0_fifo_engn *engn = &priv->engine[engine]; |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 94 | struct nouveau_gpuobj *cur; |
| 95 | u32 match = (engine << 16) | 0x00000001; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 96 | int i, p; |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 97 | |
Ben Skeggs | c2e3259 | 2013-05-06 13:54:50 +1000 | [diff] [blame] | 98 | mutex_lock(&nv_subdev(priv)->mutex); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 99 | cur = engn->playlist[engn->cur_playlist]; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 100 | engn->cur_playlist = !engn->cur_playlist; |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 101 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 102 | for (i = 0, p = 0; i < priv->base.max; i++) { |
| 103 | u32 ctrl = nv_rd32(priv, 0x800004 + (i * 8)) & 0x001f0001; |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 104 | if (ctrl != match) |
| 105 | continue; |
| 106 | nv_wo32(cur, p + 0, i); |
| 107 | nv_wo32(cur, p + 4, 0x00000000); |
| 108 | p += 8; |
| 109 | } |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 110 | bar->flush(bar); |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 111 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 112 | nv_wr32(priv, 0x002270, cur->addr >> 12); |
| 113 | nv_wr32(priv, 0x002274, (engine << 20) | (p >> 3)); |
| 114 | if (!nv_wait(priv, 0x002284 + (engine * 4), 0x00100000, 0x00000000)) |
| 115 | nv_error(priv, "playlist %d update timeout\n", engine); |
Ben Skeggs | c2e3259 | 2013-05-06 13:54:50 +1000 | [diff] [blame] | 116 | mutex_unlock(&nv_subdev(priv)->mutex); |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 117 | } |
| 118 | |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 119 | static int |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 120 | nve0_fifo_context_attach(struct nouveau_object *parent, |
| 121 | struct nouveau_object *object) |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 122 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 123 | struct nouveau_bar *bar = nouveau_bar(parent); |
| 124 | struct nve0_fifo_base *base = (void *)parent->parent; |
| 125 | struct nouveau_engctx *ectx = (void *)object; |
| 126 | u32 addr; |
| 127 | int ret; |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 128 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 129 | switch (nv_engidx(object->engine)) { |
Ben Skeggs | 01672ef | 2013-04-29 09:35:28 +1000 | [diff] [blame] | 130 | case NVDEV_ENGINE_SW : |
Ben Skeggs | dbff2de | 2012-08-06 18:16:37 +1000 | [diff] [blame] | 131 | case NVDEV_ENGINE_COPY0: |
Ben Skeggs | 01672ef | 2013-04-29 09:35:28 +1000 | [diff] [blame] | 132 | case NVDEV_ENGINE_COPY1: |
| 133 | case NVDEV_ENGINE_COPY2: |
| 134 | return 0; |
| 135 | case NVDEV_ENGINE_GR : addr = 0x0210; break; |
Ben Skeggs | b2f04fc | 2012-11-22 15:42:23 +1000 | [diff] [blame] | 136 | case NVDEV_ENGINE_BSP : addr = 0x0270; break; |
Ben Skeggs | a7416d0 | 2012-11-22 15:48:41 +1000 | [diff] [blame] | 137 | case NVDEV_ENGINE_VP : addr = 0x0250; break; |
Ben Skeggs | f3295b3 | 2012-11-22 15:54:46 +1000 | [diff] [blame] | 138 | case NVDEV_ENGINE_PPP : addr = 0x0260; break; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 139 | default: |
| 140 | return -EINVAL; |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 141 | } |
| 142 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 143 | if (!ectx->vma.node) { |
| 144 | ret = nouveau_gpuobj_map_vm(nv_gpuobj(ectx), base->vm, |
| 145 | NV_MEM_ACCESS_RW, &ectx->vma); |
| 146 | if (ret) |
| 147 | return ret; |
Ben Skeggs | 4c2d422 | 2012-08-10 15:10:34 +1000 | [diff] [blame] | 148 | |
| 149 | nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 150 | } |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 151 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 152 | nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4); |
| 153 | nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset)); |
| 154 | bar->flush(bar); |
| 155 | return 0; |
| 156 | } |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 157 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 158 | static int |
| 159 | nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend, |
| 160 | struct nouveau_object *object) |
| 161 | { |
| 162 | struct nouveau_bar *bar = nouveau_bar(parent); |
| 163 | struct nve0_fifo_priv *priv = (void *)parent->engine; |
| 164 | struct nve0_fifo_base *base = (void *)parent->parent; |
| 165 | struct nve0_fifo_chan *chan = (void *)parent; |
| 166 | u32 addr; |
| 167 | |
| 168 | switch (nv_engidx(object->engine)) { |
| 169 | case NVDEV_ENGINE_SW : return 0; |
Ben Skeggs | dbff2de | 2012-08-06 18:16:37 +1000 | [diff] [blame] | 170 | case NVDEV_ENGINE_COPY0: |
Ben Skeggs | 01672ef | 2013-04-29 09:35:28 +1000 | [diff] [blame] | 171 | case NVDEV_ENGINE_COPY1: |
| 172 | case NVDEV_ENGINE_COPY2: addr = 0x0000; break; |
| 173 | case NVDEV_ENGINE_GR : addr = 0x0210; break; |
Ben Skeggs | b2f04fc | 2012-11-22 15:42:23 +1000 | [diff] [blame] | 174 | case NVDEV_ENGINE_BSP : addr = 0x0270; break; |
Ben Skeggs | a7416d0 | 2012-11-22 15:48:41 +1000 | [diff] [blame] | 175 | case NVDEV_ENGINE_VP : addr = 0x0250; break; |
Ben Skeggs | f3295b3 | 2012-11-22 15:54:46 +1000 | [diff] [blame] | 176 | case NVDEV_ENGINE_PPP : addr = 0x0260; break; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 177 | default: |
| 178 | return -EINVAL; |
| 179 | } |
| 180 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 181 | nv_wr32(priv, 0x002634, chan->base.chid); |
| 182 | if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) { |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 183 | nv_error(priv, "channel %d [%s] kick timeout\n", |
| 184 | chan->base.chid, nouveau_client_name(chan)); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 185 | if (suspend) |
| 186 | return -EBUSY; |
| 187 | } |
| 188 | |
Ben Skeggs | 01672ef | 2013-04-29 09:35:28 +1000 | [diff] [blame] | 189 | if (addr) { |
| 190 | nv_wo32(base, addr + 0x00, 0x00000000); |
| 191 | nv_wo32(base, addr + 0x04, 0x00000000); |
| 192 | bar->flush(bar); |
| 193 | } |
| 194 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 195 | return 0; |
| 196 | } |
| 197 | |
| 198 | static int |
| 199 | nve0_fifo_chan_ctor(struct nouveau_object *parent, |
| 200 | struct nouveau_object *engine, |
| 201 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 202 | struct nouveau_object **pobject) |
| 203 | { |
| 204 | struct nouveau_bar *bar = nouveau_bar(parent); |
| 205 | struct nve0_fifo_priv *priv = (void *)engine; |
| 206 | struct nve0_fifo_base *base = (void *)parent; |
| 207 | struct nve0_fifo_chan *chan; |
Ben Skeggs | dbff2de | 2012-08-06 18:16:37 +1000 | [diff] [blame] | 208 | struct nve0_channel_ind_class *args = data; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 209 | u64 usermem, ioffset, ilength; |
| 210 | int ret, i; |
| 211 | |
| 212 | if (size < sizeof(*args)) |
| 213 | return -EINVAL; |
| 214 | |
Ben Skeggs | dbff2de | 2012-08-06 18:16:37 +1000 | [diff] [blame] | 215 | for (i = 0; i < FIFO_ENGINE_NR; i++) { |
| 216 | if (args->engine & (1 << i)) { |
| 217 | if (nouveau_engine(parent, fifo_engine[i].subdev)) { |
| 218 | args->engine = (1 << i); |
| 219 | break; |
| 220 | } |
| 221 | } |
| 222 | } |
| 223 | |
Ben Skeggs | 56fbd2b | 2013-05-02 12:37:38 +1000 | [diff] [blame^] | 224 | if (i == FIFO_ENGINE_NR) { |
| 225 | nv_error(priv, "unsupported engines 0x%08x\n", args->engine); |
Ben Skeggs | dbff2de | 2012-08-06 18:16:37 +1000 | [diff] [blame] | 226 | return -ENODEV; |
Ben Skeggs | 56fbd2b | 2013-05-02 12:37:38 +1000 | [diff] [blame^] | 227 | } |
Ben Skeggs | dbff2de | 2012-08-06 18:16:37 +1000 | [diff] [blame] | 228 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 229 | ret = nouveau_fifo_channel_create(parent, engine, oclass, 1, |
| 230 | priv->user.bar.offset, 0x200, |
| 231 | args->pushbuf, |
Ben Skeggs | dbff2de | 2012-08-06 18:16:37 +1000 | [diff] [blame] | 232 | fifo_engine[i].mask, &chan); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 233 | *pobject = nv_object(chan); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 234 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 235 | return ret; |
| 236 | |
| 237 | nv_parent(chan)->context_attach = nve0_fifo_context_attach; |
| 238 | nv_parent(chan)->context_detach = nve0_fifo_context_detach; |
Ben Skeggs | dbff2de | 2012-08-06 18:16:37 +1000 | [diff] [blame] | 239 | chan->engine = i; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 240 | |
| 241 | usermem = chan->base.chid * 0x200; |
| 242 | ioffset = args->ioffset; |
| 243 | ilength = log2i(args->ilength / 8); |
| 244 | |
| 245 | for (i = 0; i < 0x200; i += 4) |
| 246 | nv_wo32(priv->user.mem, usermem + i, 0x00000000); |
| 247 | |
| 248 | nv_wo32(base, 0x08, lower_32_bits(priv->user.mem->addr + usermem)); |
| 249 | nv_wo32(base, 0x0c, upper_32_bits(priv->user.mem->addr + usermem)); |
| 250 | nv_wo32(base, 0x10, 0x0000face); |
| 251 | nv_wo32(base, 0x30, 0xfffff902); |
| 252 | nv_wo32(base, 0x48, lower_32_bits(ioffset)); |
| 253 | nv_wo32(base, 0x4c, upper_32_bits(ioffset) | (ilength << 16)); |
| 254 | nv_wo32(base, 0x84, 0x20400000); |
| 255 | nv_wo32(base, 0x94, 0x30000001); |
| 256 | nv_wo32(base, 0x9c, 0x00000100); |
| 257 | nv_wo32(base, 0xac, 0x0000001f); |
| 258 | nv_wo32(base, 0xe8, chan->base.chid); |
| 259 | nv_wo32(base, 0xb8, 0xf8000000); |
| 260 | nv_wo32(base, 0xf8, 0x10003080); /* 0x002310 */ |
| 261 | nv_wo32(base, 0xfc, 0x10000010); /* 0x002350 */ |
| 262 | bar->flush(bar); |
| 263 | return 0; |
| 264 | } |
| 265 | |
| 266 | static int |
| 267 | nve0_fifo_chan_init(struct nouveau_object *object) |
| 268 | { |
| 269 | struct nouveau_gpuobj *base = nv_gpuobj(object->parent); |
| 270 | struct nve0_fifo_priv *priv = (void *)object->engine; |
| 271 | struct nve0_fifo_chan *chan = (void *)object; |
| 272 | u32 chid = chan->base.chid; |
| 273 | int ret; |
| 274 | |
| 275 | ret = nouveau_fifo_channel_init(&chan->base); |
| 276 | if (ret) |
| 277 | return ret; |
| 278 | |
Ben Skeggs | dbff2de | 2012-08-06 18:16:37 +1000 | [diff] [blame] | 279 | nv_mask(priv, 0x800004 + (chid * 8), 0x000f0000, chan->engine << 16); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 280 | nv_wr32(priv, 0x800000 + (chid * 8), 0x80000000 | base->addr >> 12); |
| 281 | nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400); |
| 282 | nve0_fifo_playlist_update(priv, chan->engine); |
| 283 | nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400); |
| 284 | return 0; |
| 285 | } |
| 286 | |
| 287 | static int |
| 288 | nve0_fifo_chan_fini(struct nouveau_object *object, bool suspend) |
| 289 | { |
| 290 | struct nve0_fifo_priv *priv = (void *)object->engine; |
| 291 | struct nve0_fifo_chan *chan = (void *)object; |
| 292 | u32 chid = chan->base.chid; |
| 293 | |
| 294 | nv_mask(priv, 0x800004 + (chid * 8), 0x00000800, 0x00000800); |
| 295 | nve0_fifo_playlist_update(priv, chan->engine); |
| 296 | nv_wr32(priv, 0x800000 + (chid * 8), 0x00000000); |
| 297 | |
| 298 | return nouveau_fifo_channel_fini(&chan->base, suspend); |
| 299 | } |
| 300 | |
| 301 | static struct nouveau_ofuncs |
| 302 | nve0_fifo_ofuncs = { |
| 303 | .ctor = nve0_fifo_chan_ctor, |
| 304 | .dtor = _nouveau_fifo_channel_dtor, |
| 305 | .init = nve0_fifo_chan_init, |
| 306 | .fini = nve0_fifo_chan_fini, |
| 307 | .rd32 = _nouveau_fifo_channel_rd32, |
| 308 | .wr32 = _nouveau_fifo_channel_wr32, |
| 309 | }; |
| 310 | |
| 311 | static struct nouveau_oclass |
| 312 | nve0_fifo_sclass[] = { |
Ben Skeggs | c97f8c9 | 2012-08-19 16:03:00 +1000 | [diff] [blame] | 313 | { NVE0_CHANNEL_IND_CLASS, &nve0_fifo_ofuncs }, |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 314 | {} |
| 315 | }; |
| 316 | |
| 317 | /******************************************************************************* |
| 318 | * FIFO context - instmem heap and vm setup |
| 319 | ******************************************************************************/ |
| 320 | |
| 321 | static int |
| 322 | nve0_fifo_context_ctor(struct nouveau_object *parent, |
| 323 | struct nouveau_object *engine, |
| 324 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 325 | struct nouveau_object **pobject) |
| 326 | { |
| 327 | struct nve0_fifo_base *base; |
| 328 | int ret; |
| 329 | |
| 330 | ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000, |
| 331 | 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base); |
| 332 | *pobject = nv_object(base); |
| 333 | if (ret) |
| 334 | return ret; |
| 335 | |
Ben Skeggs | f50c805 | 2013-04-24 18:02:35 +1000 | [diff] [blame] | 336 | ret = nouveau_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0, |
| 337 | &base->pgd); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 338 | if (ret) |
| 339 | return ret; |
| 340 | |
| 341 | nv_wo32(base, 0x0200, lower_32_bits(base->pgd->addr)); |
| 342 | nv_wo32(base, 0x0204, upper_32_bits(base->pgd->addr)); |
| 343 | nv_wo32(base, 0x0208, 0xffffffff); |
| 344 | nv_wo32(base, 0x020c, 0x000000ff); |
| 345 | |
| 346 | ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd); |
| 347 | if (ret) |
| 348 | return ret; |
| 349 | |
| 350 | return 0; |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 351 | } |
| 352 | |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 353 | static void |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 354 | nve0_fifo_context_dtor(struct nouveau_object *object) |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 355 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 356 | struct nve0_fifo_base *base = (void *)object; |
| 357 | nouveau_vm_ref(NULL, &base->vm, base->pgd); |
| 358 | nouveau_gpuobj_ref(NULL, &base->pgd); |
| 359 | nouveau_fifo_context_destroy(&base->base); |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 360 | } |
| 361 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 362 | static struct nouveau_oclass |
| 363 | nve0_fifo_cclass = { |
| 364 | .handle = NV_ENGCTX(FIFO, 0xe0), |
| 365 | .ofuncs = &(struct nouveau_ofuncs) { |
| 366 | .ctor = nve0_fifo_context_ctor, |
| 367 | .dtor = nve0_fifo_context_dtor, |
| 368 | .init = _nouveau_fifo_context_init, |
| 369 | .fini = _nouveau_fifo_context_fini, |
| 370 | .rd32 = _nouveau_fifo_context_rd32, |
| 371 | .wr32 = _nouveau_fifo_context_wr32, |
| 372 | }, |
| 373 | }; |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 374 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 375 | /******************************************************************************* |
| 376 | * PFIFO engine |
| 377 | ******************************************************************************/ |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 378 | |
Marcin Slusarz | e662625 | 2012-08-19 22:59:59 +0200 | [diff] [blame] | 379 | static const struct nouveau_enum nve0_fifo_fault_unit[] = { |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 380 | {} |
| 381 | }; |
| 382 | |
Marcin Slusarz | e662625 | 2012-08-19 22:59:59 +0200 | [diff] [blame] | 383 | static const struct nouveau_enum nve0_fifo_fault_reason[] = { |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 384 | { 0x00, "PT_NOT_PRESENT" }, |
| 385 | { 0x01, "PT_TOO_SHORT" }, |
| 386 | { 0x02, "PAGE_NOT_PRESENT" }, |
| 387 | { 0x03, "VM_LIMIT_EXCEEDED" }, |
| 388 | { 0x04, "NO_CHANNEL" }, |
| 389 | { 0x05, "PAGE_SYSTEM_ONLY" }, |
| 390 | { 0x06, "PAGE_READ_ONLY" }, |
| 391 | { 0x0a, "COMPRESSED_SYSRAM" }, |
| 392 | { 0x0c, "INVALID_STORAGE_TYPE" }, |
| 393 | {} |
| 394 | }; |
| 395 | |
Marcin Slusarz | e662625 | 2012-08-19 22:59:59 +0200 | [diff] [blame] | 396 | static const struct nouveau_enum nve0_fifo_fault_hubclient[] = { |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 397 | {} |
| 398 | }; |
| 399 | |
Marcin Slusarz | e662625 | 2012-08-19 22:59:59 +0200 | [diff] [blame] | 400 | static const struct nouveau_enum nve0_fifo_fault_gpcclient[] = { |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 401 | {} |
| 402 | }; |
| 403 | |
Marcin Slusarz | e662625 | 2012-08-19 22:59:59 +0200 | [diff] [blame] | 404 | static const struct nouveau_bitfield nve0_fifo_subfifo_intr[] = { |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 405 | { 0x00200000, "ILLEGAL_MTHD" }, |
| 406 | { 0x00800000, "EMPTY_SUBC" }, |
| 407 | {} |
| 408 | }; |
| 409 | |
| 410 | static void |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 411 | nve0_fifo_isr_vm_fault(struct nve0_fifo_priv *priv, int unit) |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 412 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 413 | u32 inst = nv_rd32(priv, 0x2800 + (unit * 0x10)); |
| 414 | u32 valo = nv_rd32(priv, 0x2804 + (unit * 0x10)); |
| 415 | u32 vahi = nv_rd32(priv, 0x2808 + (unit * 0x10)); |
| 416 | u32 stat = nv_rd32(priv, 0x280c + (unit * 0x10)); |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 417 | u32 client = (stat & 0x00001f00) >> 8; |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 418 | const struct nouveau_enum *en; |
| 419 | struct nouveau_engine *engine; |
| 420 | struct nouveau_object *engctx = NULL; |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 421 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 422 | nv_error(priv, "PFIFO: %s fault at 0x%010llx [", (stat & 0x00000080) ? |
| 423 | "write" : "read", (u64)vahi << 32 | valo); |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 424 | nouveau_enum_print(nve0_fifo_fault_reason, stat & 0x0000000f); |
Marcin Slusarz | f533da1 | 2012-12-09 15:45:20 +0100 | [diff] [blame] | 425 | pr_cont("] from "); |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 426 | en = nouveau_enum_print(nve0_fifo_fault_unit, unit); |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 427 | if (stat & 0x00000040) { |
Marcin Slusarz | f533da1 | 2012-12-09 15:45:20 +0100 | [diff] [blame] | 428 | pr_cont("/"); |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 429 | nouveau_enum_print(nve0_fifo_fault_hubclient, client); |
| 430 | } else { |
Marcin Slusarz | f533da1 | 2012-12-09 15:45:20 +0100 | [diff] [blame] | 431 | pr_cont("/GPC%d/", (stat & 0x1f000000) >> 24); |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 432 | nouveau_enum_print(nve0_fifo_fault_gpcclient, client); |
| 433 | } |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 434 | |
| 435 | if (en && en->data2) { |
| 436 | engine = nouveau_engine(priv, en->data2); |
| 437 | if (engine) |
| 438 | engctx = nouveau_engctx_get(engine, inst); |
| 439 | |
| 440 | } |
| 441 | |
| 442 | pr_cont(" on channel 0x%010llx [%s]\n", (u64)inst << 12, |
| 443 | nouveau_client_name(engctx)); |
| 444 | |
| 445 | nouveau_engctx_put(engctx); |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 446 | } |
| 447 | |
Ben Skeggs | e2b34fa | 2012-07-27 07:53:02 +1000 | [diff] [blame] | 448 | static int |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 449 | nve0_fifo_swmthd(struct nve0_fifo_priv *priv, u32 chid, u32 mthd, u32 data) |
Ben Skeggs | e2b34fa | 2012-07-27 07:53:02 +1000 | [diff] [blame] | 450 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 451 | struct nve0_fifo_chan *chan = NULL; |
| 452 | struct nouveau_handle *bind; |
Ben Skeggs | e2b34fa | 2012-07-27 07:53:02 +1000 | [diff] [blame] | 453 | unsigned long flags; |
| 454 | int ret = -EINVAL; |
| 455 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 456 | spin_lock_irqsave(&priv->base.lock, flags); |
| 457 | if (likely(chid >= priv->base.min && chid <= priv->base.max)) |
| 458 | chan = (void *)priv->base.channel[chid]; |
| 459 | if (unlikely(!chan)) |
| 460 | goto out; |
| 461 | |
| 462 | bind = nouveau_namedb_get_class(nv_namedb(chan), 0x906e); |
| 463 | if (likely(bind)) { |
| 464 | if (!mthd || !nv_call(bind->object, mthd, data)) |
| 465 | ret = 0; |
| 466 | nouveau_namedb_put(bind); |
Ben Skeggs | e2b34fa | 2012-07-27 07:53:02 +1000 | [diff] [blame] | 467 | } |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 468 | |
| 469 | out: |
| 470 | spin_unlock_irqrestore(&priv->base.lock, flags); |
Ben Skeggs | e2b34fa | 2012-07-27 07:53:02 +1000 | [diff] [blame] | 471 | return ret; |
| 472 | } |
| 473 | |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 474 | static void |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 475 | nve0_fifo_isr_subfifo_intr(struct nve0_fifo_priv *priv, int unit) |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 476 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 477 | u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000)); |
| 478 | u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000)); |
| 479 | u32 data = nv_rd32(priv, 0x0400c4 + (unit * 0x2000)); |
| 480 | u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0xfff; |
| 481 | u32 subc = (addr & 0x00070000) >> 16; |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 482 | u32 mthd = (addr & 0x00003ffc); |
Ben Skeggs | e2b34fa | 2012-07-27 07:53:02 +1000 | [diff] [blame] | 483 | u32 show = stat; |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 484 | |
Ben Skeggs | e2b34fa | 2012-07-27 07:53:02 +1000 | [diff] [blame] | 485 | if (stat & 0x00200000) { |
| 486 | if (mthd == 0x0054) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 487 | if (!nve0_fifo_swmthd(priv, chid, 0x0500, 0x00000000)) |
Ben Skeggs | e2b34fa | 2012-07-27 07:53:02 +1000 | [diff] [blame] | 488 | show &= ~0x00200000; |
| 489 | } |
| 490 | } |
| 491 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 492 | if (stat & 0x00800000) { |
| 493 | if (!nve0_fifo_swmthd(priv, chid, mthd, data)) |
| 494 | show &= ~0x00800000; |
Ben Skeggs | e2b34fa | 2012-07-27 07:53:02 +1000 | [diff] [blame] | 495 | } |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 496 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 497 | if (show) { |
| 498 | nv_error(priv, "SUBFIFO%d:", unit); |
| 499 | nouveau_bitfield_print(nve0_fifo_subfifo_intr, show); |
Marcin Slusarz | f533da1 | 2012-12-09 15:45:20 +0100 | [diff] [blame] | 500 | pr_cont("\n"); |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 501 | nv_error(priv, |
| 502 | "SUBFIFO%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n", |
| 503 | unit, chid, |
| 504 | nouveau_client_name_for_fifo_chid(&priv->base, chid), |
| 505 | subc, mthd, data); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 506 | } |
| 507 | |
| 508 | nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008); |
| 509 | nv_wr32(priv, 0x040108 + (unit * 0x2000), stat); |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 510 | } |
| 511 | |
| 512 | static void |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 513 | nve0_fifo_intr(struct nouveau_subdev *subdev) |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 514 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 515 | struct nve0_fifo_priv *priv = (void *)subdev; |
| 516 | u32 mask = nv_rd32(priv, 0x002140); |
| 517 | u32 stat = nv_rd32(priv, 0x002100) & mask; |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 518 | |
| 519 | if (stat & 0x00000100) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 520 | nv_warn(priv, "unknown status 0x00000100\n"); |
| 521 | nv_wr32(priv, 0x002100, 0x00000100); |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 522 | stat &= ~0x00000100; |
| 523 | } |
| 524 | |
| 525 | if (stat & 0x10000000) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 526 | u32 units = nv_rd32(priv, 0x00259c); |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 527 | u32 u = units; |
| 528 | |
| 529 | while (u) { |
| 530 | int i = ffs(u) - 1; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 531 | nve0_fifo_isr_vm_fault(priv, i); |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 532 | u &= ~(1 << i); |
| 533 | } |
| 534 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 535 | nv_wr32(priv, 0x00259c, units); |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 536 | stat &= ~0x10000000; |
| 537 | } |
| 538 | |
| 539 | if (stat & 0x20000000) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 540 | u32 units = nv_rd32(priv, 0x0025a0); |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 541 | u32 u = units; |
| 542 | |
| 543 | while (u) { |
| 544 | int i = ffs(u) - 1; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 545 | nve0_fifo_isr_subfifo_intr(priv, i); |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 546 | u &= ~(1 << i); |
| 547 | } |
| 548 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 549 | nv_wr32(priv, 0x0025a0, units); |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 550 | stat &= ~0x20000000; |
| 551 | } |
| 552 | |
| 553 | if (stat & 0x40000000) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 554 | nv_warn(priv, "unknown status 0x40000000\n"); |
| 555 | nv_mask(priv, 0x002a00, 0x00000000, 0x00000000); |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 556 | stat &= ~0x40000000; |
| 557 | } |
| 558 | |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 559 | if (stat & 0x80000000) { |
| 560 | nouveau_event_trigger(priv->base.uevent, 0); |
| 561 | nv_wr32(priv, 0x002100, 0x80000000); |
| 562 | stat &= ~0x80000000; |
| 563 | } |
| 564 | |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 565 | if (stat) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 566 | nv_fatal(priv, "unhandled status 0x%08x\n", stat); |
| 567 | nv_wr32(priv, 0x002100, stat); |
| 568 | nv_wr32(priv, 0x002140, 0); |
Ben Skeggs | 5132f37 | 2012-03-08 10:41:45 +1000 | [diff] [blame] | 569 | } |
| 570 | } |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 571 | |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 572 | static void |
| 573 | nve0_fifo_uevent_enable(struct nouveau_event *event, int index) |
| 574 | { |
| 575 | struct nve0_fifo_priv *priv = event->priv; |
| 576 | nv_mask(priv, 0x002140, 0x80000000, 0x80000000); |
| 577 | } |
| 578 | |
| 579 | static void |
| 580 | nve0_fifo_uevent_disable(struct nouveau_event *event, int index) |
| 581 | { |
| 582 | struct nve0_fifo_priv *priv = event->priv; |
| 583 | nv_mask(priv, 0x002140, 0x80000000, 0x00000000); |
| 584 | } |
| 585 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 586 | static int |
| 587 | nve0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
| 588 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 589 | struct nouveau_object **pobject) |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 590 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 591 | struct nve0_fifo_priv *priv; |
Ben Skeggs | 8d6f585 | 2013-05-07 09:09:46 +1000 | [diff] [blame] | 592 | int ret, i; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 593 | |
| 594 | ret = nouveau_fifo_create(parent, engine, oclass, 0, 4095, &priv); |
| 595 | *pobject = nv_object(priv); |
| 596 | if (ret) |
| 597 | return ret; |
| 598 | |
Ben Skeggs | 8d6f585 | 2013-05-07 09:09:46 +1000 | [diff] [blame] | 599 | for (i = 0; i < FIFO_ENGINE_NR; i++) { |
| 600 | ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000, |
| 601 | 0, &priv->engine[i].playlist[0]); |
| 602 | if (ret) |
| 603 | return ret; |
| 604 | |
| 605 | ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000, |
| 606 | 0, &priv->engine[i].playlist[1]); |
| 607 | if (ret) |
| 608 | return ret; |
| 609 | } |
| 610 | |
Ben Skeggs | f50c805 | 2013-04-24 18:02:35 +1000 | [diff] [blame] | 611 | ret = nouveau_gpuobj_new(nv_object(priv), NULL, 4096 * 0x200, 0x1000, |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 612 | NVOBJ_FLAG_ZERO_ALLOC, &priv->user.mem); |
| 613 | if (ret) |
| 614 | return ret; |
| 615 | |
| 616 | ret = nouveau_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW, |
| 617 | &priv->user.bar); |
| 618 | if (ret) |
| 619 | return ret; |
| 620 | |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 621 | priv->base.uevent->enable = nve0_fifo_uevent_enable; |
| 622 | priv->base.uevent->disable = nve0_fifo_uevent_disable; |
| 623 | priv->base.uevent->priv = priv; |
| 624 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 625 | nv_subdev(priv)->unit = 0x00000100; |
| 626 | nv_subdev(priv)->intr = nve0_fifo_intr; |
| 627 | nv_engine(priv)->cclass = &nve0_fifo_cclass; |
| 628 | nv_engine(priv)->sclass = nve0_fifo_sclass; |
| 629 | return 0; |
| 630 | } |
| 631 | |
| 632 | static void |
| 633 | nve0_fifo_dtor(struct nouveau_object *object) |
| 634 | { |
| 635 | struct nve0_fifo_priv *priv = (void *)object; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 636 | int i; |
| 637 | |
Ben Skeggs | 18c9b95 | 2012-07-13 17:05:35 +1000 | [diff] [blame] | 638 | nouveau_gpuobj_unmap(&priv->user.bar); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 639 | nouveau_gpuobj_ref(NULL, &priv->user.mem); |
| 640 | |
Ben Skeggs | 8d6f585 | 2013-05-07 09:09:46 +1000 | [diff] [blame] | 641 | for (i = 0; i < FIFO_ENGINE_NR; i++) { |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 642 | nouveau_gpuobj_ref(NULL, &priv->engine[i].playlist[1]); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 643 | nouveau_gpuobj_ref(NULL, &priv->engine[i].playlist[0]); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 644 | } |
| 645 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 646 | nouveau_fifo_destroy(&priv->base); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 647 | } |
| 648 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 649 | static int |
| 650 | nve0_fifo_init(struct nouveau_object *object) |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 651 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 652 | struct nve0_fifo_priv *priv = (void *)object; |
| 653 | int ret, i; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 654 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 655 | ret = nouveau_fifo_init(&priv->base); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 656 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 657 | return ret; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 658 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 659 | /* enable all available PSUBFIFOs */ |
| 660 | nv_wr32(priv, 0x000204, 0xffffffff); |
| 661 | priv->spoon_nr = hweight32(nv_rd32(priv, 0x000204)); |
| 662 | nv_debug(priv, "%d subfifo(s)\n", priv->spoon_nr); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 663 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 664 | /* PSUBFIFO[n] */ |
| 665 | for (i = 0; i < priv->spoon_nr; i++) { |
| 666 | nv_mask(priv, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000); |
| 667 | nv_wr32(priv, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */ |
| 668 | nv_wr32(priv, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */ |
| 669 | } |
| 670 | |
| 671 | nv_wr32(priv, 0x002254, 0x10000000 | priv->user.bar.offset >> 12); |
| 672 | |
| 673 | nv_wr32(priv, 0x002a00, 0xffffffff); |
| 674 | nv_wr32(priv, 0x002100, 0xffffffff); |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 675 | nv_wr32(priv, 0x002140, 0x3fffffff); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 676 | return 0; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 677 | } |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 678 | |
| 679 | struct nouveau_oclass |
| 680 | nve0_fifo_oclass = { |
| 681 | .handle = NV_ENGINE(FIFO, 0xe0), |
| 682 | .ofuncs = &(struct nouveau_ofuncs) { |
| 683 | .ctor = nve0_fifo_ctor, |
| 684 | .dtor = nve0_fifo_dtor, |
| 685 | .init = nve0_fifo_init, |
| 686 | .fini = _nouveau_fifo_fini, |
| 687 | }, |
| 688 | }; |