Soren Brinkmann | 812283c | 2014-10-02 09:13:35 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Xilinx 'Clocking Wizard' driver |
| 3 | * |
| 4 | * Copyright (C) 2013 - 2014 Xilinx |
| 5 | * |
| 6 | * Sören Brinkmann <soren.brinkmann@xilinx.com> |
| 7 | * |
| 8 | * This program is free software: you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License v2 as published by |
| 10 | * the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #include <linux/platform_device.h> |
| 22 | #include <linux/clk-provider.h> |
| 23 | #include <linux/slab.h> |
| 24 | #include <linux/io.h> |
| 25 | #include <linux/of.h> |
| 26 | #include <linux/module.h> |
| 27 | #include <linux/err.h> |
| 28 | |
| 29 | #define WZRD_NUM_OUTPUTS 7 |
| 30 | #define WZRD_ACLK_MAX_FREQ 250000000UL |
| 31 | |
Soren Brinkmann | 4baa70f | 2014-10-20 13:20:08 -0700 | [diff] [blame] | 32 | #define WZRD_CLK_CFG_REG(n) (0x200 + 4 * (n)) |
Soren Brinkmann | 812283c | 2014-10-02 09:13:35 -0700 | [diff] [blame] | 33 | |
| 34 | #define WZRD_CLkOUT0_FRAC_EN BIT(18) |
| 35 | #define WZRD_CLkFBOUT_FRAC_EN BIT(26) |
| 36 | |
| 37 | #define WZRD_CLKFBOUT_MULT_SHIFT 8 |
| 38 | #define WZRD_CLKFBOUT_MULT_MASK (0xff << WZRD_CLKFBOUT_MULT_SHIFT) |
| 39 | #define WZRD_DIVCLK_DIVIDE_SHIFT 0 |
| 40 | #define WZRD_DIVCLK_DIVIDE_MASK (0xff << WZRD_DIVCLK_DIVIDE_SHIFT) |
| 41 | #define WZRD_CLKOUT_DIVIDE_SHIFT 0 |
| 42 | #define WZRD_CLKOUT_DIVIDE_MASK (0xff << WZRD_DIVCLK_DIVIDE_SHIFT) |
| 43 | |
| 44 | enum clk_wzrd_int_clks { |
| 45 | wzrd_clk_mul, |
| 46 | wzrd_clk_mul_div, |
| 47 | wzrd_clk_int_max |
| 48 | }; |
| 49 | |
| 50 | /** |
| 51 | * struct clk_wzrd: |
| 52 | * @clk_data: Clock data |
| 53 | * @nb: Notifier block |
| 54 | * @base: Memory base |
| 55 | * @clk_in1: Handle to input clock 'clk_in1' |
| 56 | * @axi_clk: Handle to input clock 's_axi_aclk' |
| 57 | * @clks_internal: Internal clocks |
| 58 | * @clkout: Output clocks |
| 59 | * @speed_grade: Speed grade of the device |
| 60 | * @suspended: Flag indicating power state of the device |
| 61 | */ |
| 62 | struct clk_wzrd { |
| 63 | struct clk_onecell_data clk_data; |
| 64 | struct notifier_block nb; |
| 65 | void __iomem *base; |
| 66 | struct clk *clk_in1; |
| 67 | struct clk *axi_clk; |
| 68 | struct clk *clks_internal[wzrd_clk_int_max]; |
| 69 | struct clk *clkout[WZRD_NUM_OUTPUTS]; |
| 70 | int speed_grade; |
| 71 | bool suspended; |
| 72 | }; |
| 73 | #define to_clk_wzrd(_nb) container_of(_nb, struct clk_wzrd, nb) |
| 74 | |
| 75 | /* maximum frequencies for input/output clocks per speed grade */ |
| 76 | static const unsigned long clk_wzrd_max_freq[] = { |
| 77 | 800000000UL, |
| 78 | 933000000UL, |
| 79 | 1066000000UL |
| 80 | }; |
| 81 | |
| 82 | static int clk_wzrd_clk_notifier(struct notifier_block *nb, unsigned long event, |
| 83 | void *data) |
| 84 | { |
| 85 | unsigned long max; |
| 86 | struct clk_notifier_data *ndata = data; |
| 87 | struct clk_wzrd *clk_wzrd = to_clk_wzrd(nb); |
| 88 | |
| 89 | if (clk_wzrd->suspended) |
| 90 | return NOTIFY_OK; |
| 91 | |
| 92 | if (ndata->clk == clk_wzrd->clk_in1) |
| 93 | max = clk_wzrd_max_freq[clk_wzrd->speed_grade - 1]; |
| 94 | if (ndata->clk == clk_wzrd->axi_clk) |
| 95 | max = WZRD_ACLK_MAX_FREQ; |
| 96 | |
| 97 | switch (event) { |
| 98 | case PRE_RATE_CHANGE: |
| 99 | if (ndata->new_rate > max) |
| 100 | return NOTIFY_BAD; |
| 101 | return NOTIFY_OK; |
| 102 | case POST_RATE_CHANGE: |
| 103 | case ABORT_RATE_CHANGE: |
| 104 | default: |
| 105 | return NOTIFY_DONE; |
| 106 | } |
| 107 | } |
| 108 | |
| 109 | static int __maybe_unused clk_wzrd_suspend(struct device *dev) |
| 110 | { |
| 111 | struct clk_wzrd *clk_wzrd = dev_get_drvdata(dev); |
| 112 | |
| 113 | clk_disable_unprepare(clk_wzrd->axi_clk); |
| 114 | clk_wzrd->suspended = true; |
| 115 | |
| 116 | return 0; |
| 117 | } |
| 118 | |
| 119 | static int __maybe_unused clk_wzrd_resume(struct device *dev) |
| 120 | { |
| 121 | int ret; |
| 122 | struct clk_wzrd *clk_wzrd = dev_get_drvdata(dev); |
| 123 | |
| 124 | ret = clk_prepare_enable(clk_wzrd->axi_clk); |
| 125 | if (ret) { |
| 126 | dev_err(dev, "unable to enable s_axi_aclk\n"); |
| 127 | return ret; |
| 128 | } |
| 129 | |
| 130 | clk_wzrd->suspended = false; |
| 131 | |
| 132 | return 0; |
| 133 | } |
| 134 | |
| 135 | static SIMPLE_DEV_PM_OPS(clk_wzrd_dev_pm_ops, clk_wzrd_suspend, |
| 136 | clk_wzrd_resume); |
| 137 | |
| 138 | static int clk_wzrd_probe(struct platform_device *pdev) |
| 139 | { |
| 140 | int i, ret; |
| 141 | u32 reg; |
| 142 | unsigned long rate; |
| 143 | const char *clk_name; |
| 144 | struct clk_wzrd *clk_wzrd; |
| 145 | struct resource *mem; |
| 146 | struct device_node *np = pdev->dev.of_node; |
| 147 | |
| 148 | clk_wzrd = devm_kzalloc(&pdev->dev, sizeof(*clk_wzrd), GFP_KERNEL); |
| 149 | if (!clk_wzrd) |
| 150 | return -ENOMEM; |
| 151 | platform_set_drvdata(pdev, clk_wzrd); |
| 152 | |
| 153 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 154 | clk_wzrd->base = devm_ioremap_resource(&pdev->dev, mem); |
| 155 | if (IS_ERR(clk_wzrd->base)) |
| 156 | return PTR_ERR(clk_wzrd->base); |
| 157 | |
| 158 | ret = of_property_read_u32(np, "speed-grade", &clk_wzrd->speed_grade); |
| 159 | if (!ret) { |
| 160 | if (clk_wzrd->speed_grade < 1 || clk_wzrd->speed_grade > 3) { |
| 161 | dev_warn(&pdev->dev, "invalid speed grade '%d'\n", |
| 162 | clk_wzrd->speed_grade); |
| 163 | clk_wzrd->speed_grade = 0; |
| 164 | } |
| 165 | } |
| 166 | |
| 167 | clk_wzrd->clk_in1 = devm_clk_get(&pdev->dev, "clk_in1"); |
| 168 | if (IS_ERR(clk_wzrd->clk_in1)) { |
| 169 | if (clk_wzrd->clk_in1 != ERR_PTR(-EPROBE_DEFER)) |
| 170 | dev_err(&pdev->dev, "clk_in1 not found\n"); |
| 171 | return PTR_ERR(clk_wzrd->clk_in1); |
| 172 | } |
| 173 | |
| 174 | clk_wzrd->axi_clk = devm_clk_get(&pdev->dev, "s_axi_aclk"); |
| 175 | if (IS_ERR(clk_wzrd->axi_clk)) { |
| 176 | if (clk_wzrd->axi_clk != ERR_PTR(-EPROBE_DEFER)) |
| 177 | dev_err(&pdev->dev, "s_axi_aclk not found\n"); |
| 178 | return PTR_ERR(clk_wzrd->axi_clk); |
| 179 | } |
| 180 | ret = clk_prepare_enable(clk_wzrd->axi_clk); |
| 181 | if (ret) { |
| 182 | dev_err(&pdev->dev, "enabling s_axi_aclk failed\n"); |
| 183 | return ret; |
| 184 | } |
| 185 | rate = clk_get_rate(clk_wzrd->axi_clk); |
| 186 | if (rate > WZRD_ACLK_MAX_FREQ) { |
| 187 | dev_err(&pdev->dev, "s_axi_aclk frequency (%lu) too high\n", |
| 188 | rate); |
| 189 | ret = -EINVAL; |
| 190 | goto err_disable_clk; |
| 191 | } |
| 192 | |
| 193 | /* we don't support fractional div/mul yet */ |
| 194 | reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) & |
| 195 | WZRD_CLkFBOUT_FRAC_EN; |
| 196 | reg |= readl(clk_wzrd->base + WZRD_CLK_CFG_REG(2)) & |
| 197 | WZRD_CLkOUT0_FRAC_EN; |
| 198 | if (reg) |
| 199 | dev_warn(&pdev->dev, "fractional div/mul not supported\n"); |
| 200 | |
| 201 | /* register multiplier */ |
| 202 | reg = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) & |
| 203 | WZRD_CLKFBOUT_MULT_MASK) >> WZRD_CLKFBOUT_MULT_SHIFT; |
| 204 | clk_name = kasprintf(GFP_KERNEL, "%s_mul", dev_name(&pdev->dev)); |
| 205 | if (!clk_name) { |
| 206 | ret = -ENOMEM; |
| 207 | goto err_disable_clk; |
| 208 | } |
| 209 | clk_wzrd->clks_internal[wzrd_clk_mul] = clk_register_fixed_factor( |
| 210 | &pdev->dev, clk_name, |
| 211 | __clk_get_name(clk_wzrd->clk_in1), |
| 212 | 0, reg, 1); |
| 213 | kfree(clk_name); |
| 214 | if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul])) { |
| 215 | dev_err(&pdev->dev, "unable to register fixed-factor clock\n"); |
| 216 | ret = PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul]); |
| 217 | goto err_disable_clk; |
| 218 | } |
| 219 | |
| 220 | /* register div */ |
| 221 | reg = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) & |
| 222 | WZRD_DIVCLK_DIVIDE_MASK) >> WZRD_DIVCLK_DIVIDE_SHIFT; |
| 223 | clk_name = kasprintf(GFP_KERNEL, "%s_mul_div", dev_name(&pdev->dev)); |
Devendra Naga | 5f18611 | 2014-11-29 17:48:34 -0500 | [diff] [blame] | 224 | if (!clk_name) { |
| 225 | ret = -ENOMEM; |
| 226 | goto err_rm_int_clk; |
| 227 | } |
| 228 | |
Soren Brinkmann | 812283c | 2014-10-02 09:13:35 -0700 | [diff] [blame] | 229 | clk_wzrd->clks_internal[wzrd_clk_mul_div] = clk_register_fixed_factor( |
| 230 | &pdev->dev, clk_name, |
| 231 | __clk_get_name(clk_wzrd->clks_internal[wzrd_clk_mul]), |
| 232 | 0, 1, reg); |
| 233 | if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div])) { |
| 234 | dev_err(&pdev->dev, "unable to register divider clock\n"); |
| 235 | ret = PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div]); |
| 236 | goto err_rm_int_clk; |
| 237 | } |
| 238 | |
| 239 | /* register div per output */ |
| 240 | for (i = WZRD_NUM_OUTPUTS - 1; i >= 0 ; i--) { |
| 241 | const char *clkout_name; |
| 242 | if (of_property_read_string_index(np, "clock-output-names", i, |
| 243 | &clkout_name)) { |
| 244 | dev_err(&pdev->dev, |
| 245 | "clock output name not specified\n"); |
| 246 | ret = -EINVAL; |
| 247 | goto err_rm_int_clks; |
| 248 | } |
| 249 | reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(2) + i * 12); |
| 250 | reg &= WZRD_CLKOUT_DIVIDE_MASK; |
| 251 | reg >>= WZRD_CLKOUT_DIVIDE_SHIFT; |
| 252 | clk_wzrd->clkout[i] = clk_register_fixed_factor(&pdev->dev, |
| 253 | clkout_name, clk_name, 0, 1, reg); |
| 254 | if (IS_ERR(clk_wzrd->clkout[i])) { |
| 255 | int j; |
Athira Sharikkal | e66f7a2 | 2014-11-30 14:16:05 +0530 | [diff] [blame] | 256 | |
Soren Brinkmann | 812283c | 2014-10-02 09:13:35 -0700 | [diff] [blame] | 257 | for (j = i + 1; j < WZRD_NUM_OUTPUTS; j++) |
| 258 | clk_unregister(clk_wzrd->clkout[j]); |
| 259 | dev_err(&pdev->dev, |
| 260 | "unable to register divider clock\n"); |
| 261 | ret = PTR_ERR(clk_wzrd->clkout[i]); |
| 262 | goto err_rm_int_clks; |
| 263 | } |
| 264 | } |
| 265 | |
| 266 | kfree(clk_name); |
| 267 | |
| 268 | clk_wzrd->clk_data.clks = clk_wzrd->clkout; |
| 269 | clk_wzrd->clk_data.clk_num = ARRAY_SIZE(clk_wzrd->clkout); |
| 270 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_wzrd->clk_data); |
| 271 | |
| 272 | if (clk_wzrd->speed_grade) { |
| 273 | clk_wzrd->nb.notifier_call = clk_wzrd_clk_notifier; |
| 274 | |
| 275 | ret = clk_notifier_register(clk_wzrd->clk_in1, |
| 276 | &clk_wzrd->nb); |
| 277 | if (ret) |
| 278 | dev_warn(&pdev->dev, |
| 279 | "unable to register clock notifier\n"); |
| 280 | |
| 281 | ret = clk_notifier_register(clk_wzrd->axi_clk, &clk_wzrd->nb); |
| 282 | if (ret) |
| 283 | dev_warn(&pdev->dev, |
| 284 | "unable to register clock notifier\n"); |
| 285 | } |
| 286 | |
| 287 | return 0; |
| 288 | |
| 289 | err_rm_int_clks: |
| 290 | clk_unregister(clk_wzrd->clks_internal[1]); |
| 291 | err_rm_int_clk: |
| 292 | kfree(clk_name); |
| 293 | clk_unregister(clk_wzrd->clks_internal[0]); |
| 294 | err_disable_clk: |
| 295 | clk_disable_unprepare(clk_wzrd->axi_clk); |
| 296 | |
| 297 | return ret; |
| 298 | } |
| 299 | |
| 300 | static int clk_wzrd_remove(struct platform_device *pdev) |
| 301 | { |
| 302 | int i; |
| 303 | struct clk_wzrd *clk_wzrd = platform_get_drvdata(pdev); |
| 304 | |
| 305 | of_clk_del_provider(pdev->dev.of_node); |
| 306 | |
| 307 | for (i = 0; i < WZRD_NUM_OUTPUTS; i++) |
| 308 | clk_unregister(clk_wzrd->clkout[i]); |
| 309 | for (i = 0; i < wzrd_clk_int_max; i++) |
| 310 | clk_unregister(clk_wzrd->clks_internal[i]); |
| 311 | |
| 312 | if (clk_wzrd->speed_grade) { |
| 313 | clk_notifier_unregister(clk_wzrd->axi_clk, &clk_wzrd->nb); |
| 314 | clk_notifier_unregister(clk_wzrd->clk_in1, &clk_wzrd->nb); |
| 315 | } |
| 316 | |
| 317 | clk_disable_unprepare(clk_wzrd->axi_clk); |
| 318 | |
| 319 | return 0; |
| 320 | } |
| 321 | |
| 322 | static const struct of_device_id clk_wzrd_ids[] = { |
| 323 | { .compatible = "xlnx,clocking-wizard" }, |
| 324 | { }, |
| 325 | }; |
| 326 | MODULE_DEVICE_TABLE(of, clk_wzrd_ids); |
| 327 | |
| 328 | static struct platform_driver clk_wzrd_driver = { |
| 329 | .driver = { |
| 330 | .name = "clk-wizard", |
| 331 | .of_match_table = clk_wzrd_ids, |
| 332 | .pm = &clk_wzrd_dev_pm_ops, |
| 333 | }, |
| 334 | .probe = clk_wzrd_probe, |
| 335 | .remove = clk_wzrd_remove, |
| 336 | }; |
| 337 | module_platform_driver(clk_wzrd_driver); |
| 338 | |
| 339 | MODULE_LICENSE("GPL"); |
| 340 | MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com"); |
| 341 | MODULE_DESCRIPTION("Driver for the Xilinx Clocking Wizard IP core"); |