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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 */
Kumar Gala5f7c6902005-09-09 15:02:25 -05004#ifndef _ASM_POWERPC_PPC_ASM_H
5#define _ASM_POWERPC_PPC_ASM_H
6
Tim Abbott9203fc92009-04-27 14:02:24 -04007#include <linux/init.h>
Paul Mackerras40ef8cb2005-10-10 22:50:37 +10008#include <linux/stringify.h>
David Gibson3ddfbcf2005-11-10 12:56:55 +11009#include <asm/asm-compat.h>
Michael Neuling9c75a312008-06-26 17:07:48 +100010#include <asm/processor.h>
Kumar Gala16c57b32009-02-10 20:10:44 +000011#include <asm/ppc-opcode.h>
Paul Mackerras40ef8cb2005-10-10 22:50:37 +100012
David Gibson3ddfbcf2005-11-10 12:56:55 +110013#ifndef __ASSEMBLY__
14#error __FILE__ should only be used in assembler files
15#else
16
17#define SZL (BITS_PER_LONG/8)
Linus Torvalds1da177e2005-04-16 15:20:36 -070018
19/*
Paul Mackerrasc6622f62006-02-24 10:06:59 +110020 * Stuff for accurate CPU time accounting.
21 * These macros handle transitions between user and system state
22 * in exception entry and exit and accumulate time to the
23 * user_time and system_time fields in the paca.
24 */
25
26#ifndef CONFIG_VIRT_CPU_ACCOUNTING
27#define ACCOUNT_CPU_USER_ENTRY(ra, rb)
28#define ACCOUNT_CPU_USER_EXIT(ra, rb)
29#else
30#define ACCOUNT_CPU_USER_ENTRY(ra, rb) \
31 beq 2f; /* if from kernel mode */ \
32BEGIN_FTR_SECTION; \
33 mfspr ra,SPRN_PURR; /* get processor util. reg */ \
34END_FTR_SECTION_IFSET(CPU_FTR_PURR); \
35BEGIN_FTR_SECTION; \
Benjamin Herrenschmidt859deea2006-10-20 14:37:05 +100036 MFTB(ra); /* or get TB if no PURR */ \
Paul Mackerrasc6622f62006-02-24 10:06:59 +110037END_FTR_SECTION_IFCLR(CPU_FTR_PURR); \
Benjamin Herrenschmidt859deea2006-10-20 14:37:05 +100038 ld rb,PACA_STARTPURR(r13); \
Paul Mackerrasc6622f62006-02-24 10:06:59 +110039 std ra,PACA_STARTPURR(r13); \
40 subf rb,rb,ra; /* subtract start value */ \
41 ld ra,PACA_USER_TIME(r13); \
42 add ra,ra,rb; /* add on to user time */ \
43 std ra,PACA_USER_TIME(r13); \
442:
45
46#define ACCOUNT_CPU_USER_EXIT(ra, rb) \
47BEGIN_FTR_SECTION; \
48 mfspr ra,SPRN_PURR; /* get processor util. reg */ \
49END_FTR_SECTION_IFSET(CPU_FTR_PURR); \
50BEGIN_FTR_SECTION; \
Benjamin Herrenschmidt859deea2006-10-20 14:37:05 +100051 MFTB(ra); /* or get TB if no PURR */ \
Paul Mackerrasc6622f62006-02-24 10:06:59 +110052END_FTR_SECTION_IFCLR(CPU_FTR_PURR); \
Benjamin Herrenschmidt859deea2006-10-20 14:37:05 +100053 ld rb,PACA_STARTPURR(r13); \
Paul Mackerrasc6622f62006-02-24 10:06:59 +110054 std ra,PACA_STARTPURR(r13); \
55 subf rb,rb,ra; /* subtract start value */ \
56 ld ra,PACA_SYSTEM_TIME(r13); \
57 add ra,ra,rb; /* add on to user time */ \
58 std ra,PACA_SYSTEM_TIME(r13);
59#endif
60
61/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070062 * Macros for storing registers into and loading registers from
63 * exception frames.
64 */
Kumar Gala5f7c6902005-09-09 15:02:25 -050065#ifdef __powerpc64__
66#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
67#define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
68#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
69#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
70#else
Linus Torvalds1da177e2005-04-16 15:20:36 -070071#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
Linus Torvalds1da177e2005-04-16 15:20:36 -070072#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
Linus Torvalds1da177e2005-04-16 15:20:36 -070073#define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
74 SAVE_10GPRS(22, base)
75#define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
76 REST_10GPRS(22, base)
Kumar Gala5f7c6902005-09-09 15:02:25 -050077#endif
78
Kumar Gala5f7c6902005-09-09 15:02:25 -050079#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
80#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
81#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
82#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
83#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
84#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
85#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
86#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
Linus Torvalds1da177e2005-04-16 15:20:36 -070087
Michael Neuling9c75a312008-06-26 17:07:48 +100088#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
Linus Torvalds1da177e2005-04-16 15:20:36 -070089#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
90#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
91#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
92#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
93#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
Michael Neuling9c75a312008-06-26 17:07:48 +100094#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
Linus Torvalds1da177e2005-04-16 15:20:36 -070095#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
96#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
97#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
98#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
99#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
100
101#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
Kumar Gala5f7c6902005-09-09 15:02:25 -0500102#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
103#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
104#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
105#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
106#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
Kumar Gala5f7c6902005-09-09 15:02:25 -0500108#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
109#define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
110#define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
111#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
112#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700113
Michael Neuling72ffff52008-06-25 14:07:18 +1000114/* Save the lower 32 VSRs in the thread VSR region */
115#define SAVE_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); STXVD2X(n,b,base)
116#define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
117#define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
118#define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
119#define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
120#define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
121#define REST_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); LXVD2X(n,b,base)
122#define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base)
123#define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
124#define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
125#define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
126#define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
127/* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */
128#define SAVE_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); STXVD2X(n+32,b,base)
129#define SAVE_2VSRSU(n,b,base) SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base)
130#define SAVE_4VSRSU(n,b,base) SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base)
131#define SAVE_8VSRSU(n,b,base) SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base)
132#define SAVE_16VSRSU(n,b,base) SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base)
133#define SAVE_32VSRSU(n,b,base) SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+16,b,base)
134#define REST_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,b,base)
135#define REST_2VSRSU(n,b,base) REST_VSRU(n,b,base); REST_VSRU(n+1,b,base)
136#define REST_4VSRSU(n,b,base) REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base)
137#define REST_8VSRSU(n,b,base) REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base)
138#define REST_16VSRSU(n,b,base) REST_8VSRSU(n,b,base); REST_8VSRSU(n+8,b,base)
139#define REST_32VSRSU(n,b,base) REST_16VSRSU(n,b,base); REST_16VSRSU(n+16,b,base)
140
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141#define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
Kumar Gala5f7c6902005-09-09 15:02:25 -0500142#define SAVE_2EVRS(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
143#define SAVE_4EVRS(n,s,base) SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)
144#define SAVE_8EVRS(n,s,base) SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base)
145#define SAVE_16EVRS(n,s,base) SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base)
146#define SAVE_32EVRS(n,s,base) SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147#define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
Kumar Gala5f7c6902005-09-09 15:02:25 -0500148#define REST_2EVRS(n,s,base) REST_EVR(n,s,base); REST_EVR(n+1,s,base)
149#define REST_4EVRS(n,s,base) REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base)
150#define REST_8EVRS(n,s,base) REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base)
151#define REST_16EVRS(n,s,base) REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
152#define REST_32EVRS(n,s,base) REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700153
Michael Ellerman8c716322005-10-24 15:07:27 +1000154/* Macros to adjust thread priority for hardware multithreading */
155#define HMT_VERY_LOW or 31,31,31 # very low priority
156#define HMT_LOW or 1,1,1
157#define HMT_MEDIUM_LOW or 6,6,6 # medium low priority
158#define HMT_MEDIUM or 2,2,2
159#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
160#define HMT_HIGH or 3,3,3
Kumar Gala5f7c6902005-09-09 15:02:25 -0500161
Arnd Bergmann88ced032005-12-16 22:43:46 +0100162#ifdef __KERNEL__
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000163#ifdef CONFIG_PPC64
164
165#define XGLUE(a,b) a##b
166#define GLUE(a,b) XGLUE(a,b)
167
168#define _GLOBAL(name) \
169 .section ".text"; \
170 .align 2 ; \
171 .globl name; \
172 .globl GLUE(.,name); \
173 .section ".opd","aw"; \
174name: \
175 .quad GLUE(.,name); \
176 .quad .TOC.@tocbase; \
177 .quad 0; \
178 .previous; \
179 .type GLUE(.,name),@function; \
180GLUE(.,name):
181
Stephen Rothwellfc68e862007-08-22 13:44:58 +1000182#define _INIT_GLOBAL(name) \
Tim Abbott9203fc92009-04-27 14:02:24 -0400183 __REF; \
Stephen Rothwellfc68e862007-08-22 13:44:58 +1000184 .align 2 ; \
185 .globl name; \
186 .globl GLUE(.,name); \
187 .section ".opd","aw"; \
188name: \
189 .quad GLUE(.,name); \
190 .quad .TOC.@tocbase; \
191 .quad 0; \
192 .previous; \
193 .type GLUE(.,name),@function; \
194GLUE(.,name):
195
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000196#define _KPROBE(name) \
197 .section ".kprobes.text","a"; \
198 .align 2 ; \
199 .globl name; \
200 .globl GLUE(.,name); \
201 .section ".opd","aw"; \
202name: \
203 .quad GLUE(.,name); \
204 .quad .TOC.@tocbase; \
205 .quad 0; \
206 .previous; \
207 .type GLUE(.,name),@function; \
208GLUE(.,name):
209
210#define _STATIC(name) \
211 .section ".text"; \
212 .align 2 ; \
213 .section ".opd","aw"; \
214name: \
215 .quad GLUE(.,name); \
216 .quad .TOC.@tocbase; \
217 .quad 0; \
218 .previous; \
219 .type GLUE(.,name),@function; \
220GLUE(.,name):
221
Stephen Rothwellc40b91b2007-07-25 09:27:35 +1000222#define _INIT_STATIC(name) \
Tim Abbott9203fc92009-04-27 14:02:24 -0400223 __REF; \
Stephen Rothwellc40b91b2007-07-25 09:27:35 +1000224 .align 2 ; \
225 .section ".opd","aw"; \
226name: \
227 .quad GLUE(.,name); \
228 .quad .TOC.@tocbase; \
229 .quad 0; \
230 .previous; \
231 .type GLUE(.,name),@function; \
232GLUE(.,name):
233
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000234#else /* 32-bit */
235
Kumar Gala748a7682007-09-13 15:42:35 -0500236#define _ENTRY(n) \
237 .globl n; \
238n:
239
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000240#define _GLOBAL(n) \
241 .text; \
242 .stabs __stringify(n:F-1),N_FUN,0,0,n;\
243 .globl n; \
244n:
245
246#define _KPROBE(n) \
247 .section ".kprobes.text","a"; \
248 .globl n; \
249n:
250
251#endif
252
Kumar Gala5f7c6902005-09-09 15:02:25 -0500253/*
David Gibsone58c3492006-01-13 14:56:25 +1100254 * LOAD_REG_IMMEDIATE(rn, expr)
255 * Loads the value of the constant expression 'expr' into register 'rn'
256 * using immediate instructions only. Use this when it's important not
257 * to reference other data (i.e. on ppc64 when the TOC pointer is not
Paul Mackerrase31aa452008-08-30 11:41:12 +1000258 * valid) and when 'expr' is a constant or absolute address.
Kumar Gala5f7c6902005-09-09 15:02:25 -0500259 *
David Gibsone58c3492006-01-13 14:56:25 +1100260 * LOAD_REG_ADDR(rn, name)
261 * Loads the address of label 'name' into register 'rn'. Use this when
262 * you don't particularly need immediate instructions only, but you need
263 * the whole address in one register (e.g. it's a structure address and
264 * you want to access various offsets within it). On ppc32 this is
265 * identical to LOAD_REG_IMMEDIATE.
266 *
267 * LOAD_REG_ADDRBASE(rn, name)
268 * ADDROFF(name)
269 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into
270 * register 'rn'. ADDROFF(name) returns the remainder of the address as
271 * a constant expression. ADDROFF(name) is a signed expression < 16 bits
272 * in size, so is suitable for use directly as an offset in load and store
273 * instructions. Use this when loading/storing a single word or less as:
274 * LOAD_REG_ADDRBASE(rX, name)
275 * ld rY,ADDROFF(name)(rX)
Kumar Gala5f7c6902005-09-09 15:02:25 -0500276 */
277#ifdef __powerpc64__
David Gibsone58c3492006-01-13 14:56:25 +1100278#define LOAD_REG_IMMEDIATE(reg,expr) \
279 lis (reg),(expr)@highest; \
280 ori (reg),(reg),(expr)@higher; \
281 rldicr (reg),(reg),32,31; \
282 oris (reg),(reg),(expr)@h; \
283 ori (reg),(reg),(expr)@l;
Kumar Gala5f7c6902005-09-09 15:02:25 -0500284
David Gibsone58c3492006-01-13 14:56:25 +1100285#define LOAD_REG_ADDR(reg,name) \
286 ld (reg),name@got(r2)
Kumar Gala5f7c6902005-09-09 15:02:25 -0500287
David Gibsone58c3492006-01-13 14:56:25 +1100288#define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name)
289#define ADDROFF(name) 0
Paul Mackerrasb85a0462005-10-06 10:59:19 +1000290
Paul Mackerrasf78541d2005-10-28 22:53:37 +1000291/* offsets for stack frame layout */
292#define LRSAVE 16
Paul Mackerrasb85a0462005-10-06 10:59:19 +1000293
294#else /* 32-bit */
Stephen Rothwell70620182005-10-12 17:44:55 +1000295
David Gibsone58c3492006-01-13 14:56:25 +1100296#define LOAD_REG_IMMEDIATE(reg,expr) \
297 lis (reg),(expr)@ha; \
298 addi (reg),(reg),(expr)@l;
Paul Mackerrasb85a0462005-10-06 10:59:19 +1000299
David Gibsone58c3492006-01-13 14:56:25 +1100300#define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name)
301
302#define LOAD_REG_ADDRBASE(reg, name) lis (reg),name@ha
303#define ADDROFF(name) name@l
Paul Mackerrasb85a0462005-10-06 10:59:19 +1000304
Paul Mackerrasf78541d2005-10-28 22:53:37 +1000305/* offsets for stack frame layout */
306#define LRSAVE 4
Paul Mackerrasb85a0462005-10-06 10:59:19 +1000307
Kumar Gala5f7c6902005-09-09 15:02:25 -0500308#endif
309
310/* various errata or part fixups */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700311#ifdef CONFIG_PPC601_SYNC_FIX
312#define SYNC \
313BEGIN_FTR_SECTION \
314 sync; \
315 isync; \
316END_FTR_SECTION_IFSET(CPU_FTR_601)
317#define SYNC_601 \
318BEGIN_FTR_SECTION \
319 sync; \
320END_FTR_SECTION_IFSET(CPU_FTR_601)
321#define ISYNC_601 \
322BEGIN_FTR_SECTION \
323 isync; \
324END_FTR_SECTION_IFSET(CPU_FTR_601)
325#else
326#define SYNC
327#define SYNC_601
328#define ISYNC_601
329#endif
330
Benjamin Herrenschmidt859deea2006-10-20 14:37:05 +1000331#ifdef CONFIG_PPC_CELL
332#define MFTB(dest) \
33390: mftb dest; \
334BEGIN_FTR_SECTION_NESTED(96); \
335 cmpwi dest,0; \
336 beq- 90b; \
337END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
338#else
339#define MFTB(dest) mftb dest
340#endif
Kumar Gala5f7c6902005-09-09 15:02:25 -0500341
Linus Torvalds1da177e2005-04-16 15:20:36 -0700342#ifndef CONFIG_SMP
343#define TLBSYNC
344#else /* CONFIG_SMP */
345/* tlbsync is not implemented on 601 */
346#define TLBSYNC \
347BEGIN_FTR_SECTION \
348 tlbsync; \
349 sync; \
350END_FTR_SECTION_IFCLR(CPU_FTR_601)
351#endif
352
Kumar Gala5f7c6902005-09-09 15:02:25 -0500353
Linus Torvalds1da177e2005-04-16 15:20:36 -0700354/*
355 * This instruction is not implemented on the PPC 603 or 601; however, on
356 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
357 * All of these instructions exist in the 8xx, they have magical powers,
358 * and they must be used.
359 */
360
361#if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
362#define tlbia \
363 li r4,1024; \
364 mtctr r4; \
365 lis r4,KERNELBASE@h; \
3660: tlbie r4; \
367 addi r4,r4,0x1000; \
368 bdnz 0b
369#endif
370
Kumar Gala5f7c6902005-09-09 15:02:25 -0500371
Kumar Gala5f7c6902005-09-09 15:02:25 -0500372#ifdef CONFIG_IBM440EP_ERR42
373#define PPC440EP_ERR42 isync
374#else
375#define PPC440EP_ERR42
376#endif
377
378
379#if defined(CONFIG_BOOKE)
Paul Mackerras63162222005-10-27 22:44:39 +1000380#define toreal(rd)
381#define fromreal(rd)
382
Roland McGrath2ca76332008-05-11 10:40:47 +1000383/*
384 * We use addis to ensure compatibility with the "classic" ppc versions of
385 * these macros, which use rs = 0 to get the tophys offset in rd, rather than
386 * converting the address in r0, and so this version has to do that too
387 * (i.e. set register rd to 0 when rs == 0).
388 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700389#define tophys(rd,rs) \
390 addis rd,rs,0
391
392#define tovirt(rd,rs) \
393 addis rd,rs,0
394
Kumar Gala5f7c6902005-09-09 15:02:25 -0500395#elif defined(CONFIG_PPC64)
Paul Mackerras63162222005-10-27 22:44:39 +1000396#define toreal(rd) /* we can access c000... in real mode */
397#define fromreal(rd)
398
Kumar Gala5f7c6902005-09-09 15:02:25 -0500399#define tophys(rd,rs) \
Paul Mackerras63162222005-10-27 22:44:39 +1000400 clrldi rd,rs,2
Kumar Gala5f7c6902005-09-09 15:02:25 -0500401
402#define tovirt(rd,rs) \
Paul Mackerras63162222005-10-27 22:44:39 +1000403 rotldi rd,rs,16; \
404 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\
405 rotldi rd,rd,48
Kumar Gala5f7c6902005-09-09 15:02:25 -0500406#else
Linus Torvalds1da177e2005-04-16 15:20:36 -0700407/*
408 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
409 * physical base address of RAM at compile time.
410 */
Paul Mackerras63162222005-10-27 22:44:39 +1000411#define toreal(rd) tophys(rd,rd)
412#define fromreal(rd) tovirt(rd,rd)
413
Linus Torvalds1da177e2005-04-16 15:20:36 -0700414#define tophys(rd,rs) \
Dale Farnsworthccdcef72008-12-17 10:09:13 +00004150: addis rd,rs,-PAGE_OFFSET@h; \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700416 .section ".vtop_fixup","aw"; \
417 .align 1; \
418 .long 0b; \
419 .previous
420
421#define tovirt(rd,rs) \
Dale Farnsworthccdcef72008-12-17 10:09:13 +00004220: addis rd,rs,PAGE_OFFSET@h; \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700423 .section ".ptov_fixup","aw"; \
424 .align 1; \
425 .long 0b; \
426 .previous
Kumar Gala5f7c6902005-09-09 15:02:25 -0500427#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700428
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000429#ifdef CONFIG_PPC64
430#define RFI rfid
431#define MTMSRD(r) mtmsrd r
Linus Torvalds1da177e2005-04-16 15:20:36 -0700432
433#else
434#define FIX_SRR1(ra, rb)
435#ifndef CONFIG_40x
436#define RFI rfi
437#else
438#define RFI rfi; b . /* Prevent prefetch past rfi */
439#endif
440#define MTMSRD(r) mtmsr r
441#define CLR_TOP32(r)
Matt Porterc9cf73a2005-07-31 22:34:52 -0700442#endif
443
Arnd Bergmann88ced032005-12-16 22:43:46 +0100444#endif /* __KERNEL__ */
445
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446/* The boring bits... */
447
448/* Condition Register Bit Fields */
449
450#define cr0 0
451#define cr1 1
452#define cr2 2
453#define cr3 3
454#define cr4 4
455#define cr5 5
456#define cr6 6
457#define cr7 7
458
459
460/* General Purpose Registers (GPRs) */
461
462#define r0 0
463#define r1 1
464#define r2 2
465#define r3 3
466#define r4 4
467#define r5 5
468#define r6 6
469#define r7 7
470#define r8 8
471#define r9 9
472#define r10 10
473#define r11 11
474#define r12 12
475#define r13 13
476#define r14 14
477#define r15 15
478#define r16 16
479#define r17 17
480#define r18 18
481#define r19 19
482#define r20 20
483#define r21 21
484#define r22 22
485#define r23 23
486#define r24 24
487#define r25 25
488#define r26 26
489#define r27 27
490#define r28 28
491#define r29 29
492#define r30 30
493#define r31 31
494
495
496/* Floating Point Registers (FPRs) */
497
498#define fr0 0
499#define fr1 1
500#define fr2 2
501#define fr3 3
502#define fr4 4
503#define fr5 5
504#define fr6 6
505#define fr7 7
506#define fr8 8
507#define fr9 9
508#define fr10 10
509#define fr11 11
510#define fr12 12
511#define fr13 13
512#define fr14 14
513#define fr15 15
514#define fr16 16
515#define fr17 17
516#define fr18 18
517#define fr19 19
518#define fr20 20
519#define fr21 21
520#define fr22 22
521#define fr23 23
522#define fr24 24
523#define fr25 25
524#define fr26 26
525#define fr27 27
526#define fr28 28
527#define fr29 29
528#define fr30 30
529#define fr31 31
530
Kumar Gala5f7c6902005-09-09 15:02:25 -0500531/* AltiVec Registers (VPRs) */
532
Linus Torvalds1da177e2005-04-16 15:20:36 -0700533#define vr0 0
534#define vr1 1
535#define vr2 2
536#define vr3 3
537#define vr4 4
538#define vr5 5
539#define vr6 6
540#define vr7 7
541#define vr8 8
542#define vr9 9
543#define vr10 10
544#define vr11 11
545#define vr12 12
546#define vr13 13
547#define vr14 14
548#define vr15 15
549#define vr16 16
550#define vr17 17
551#define vr18 18
552#define vr19 19
553#define vr20 20
554#define vr21 21
555#define vr22 22
556#define vr23 23
557#define vr24 24
558#define vr25 25
559#define vr26 26
560#define vr27 27
561#define vr28 28
562#define vr29 29
563#define vr30 30
564#define vr31 31
565
Michael Neuling72ffff52008-06-25 14:07:18 +1000566/* VSX Registers (VSRs) */
567
568#define vsr0 0
569#define vsr1 1
570#define vsr2 2
571#define vsr3 3
572#define vsr4 4
573#define vsr5 5
574#define vsr6 6
575#define vsr7 7
576#define vsr8 8
577#define vsr9 9
578#define vsr10 10
579#define vsr11 11
580#define vsr12 12
581#define vsr13 13
582#define vsr14 14
583#define vsr15 15
584#define vsr16 16
585#define vsr17 17
586#define vsr18 18
587#define vsr19 19
588#define vsr20 20
589#define vsr21 21
590#define vsr22 22
591#define vsr23 23
592#define vsr24 24
593#define vsr25 25
594#define vsr26 26
595#define vsr27 27
596#define vsr28 28
597#define vsr29 29
598#define vsr30 30
599#define vsr31 31
600#define vsr32 32
601#define vsr33 33
602#define vsr34 34
603#define vsr35 35
604#define vsr36 36
605#define vsr37 37
606#define vsr38 38
607#define vsr39 39
608#define vsr40 40
609#define vsr41 41
610#define vsr42 42
611#define vsr43 43
612#define vsr44 44
613#define vsr45 45
614#define vsr46 46
615#define vsr47 47
616#define vsr48 48
617#define vsr49 49
618#define vsr50 50
619#define vsr51 51
620#define vsr52 52
621#define vsr53 53
622#define vsr54 54
623#define vsr55 55
624#define vsr56 56
625#define vsr57 57
626#define vsr58 58
627#define vsr59 59
628#define vsr60 60
629#define vsr61 61
630#define vsr62 62
631#define vsr63 63
632
Kumar Gala5f7c6902005-09-09 15:02:25 -0500633/* SPE Registers (EVPRs) */
634
Linus Torvalds1da177e2005-04-16 15:20:36 -0700635#define evr0 0
636#define evr1 1
637#define evr2 2
638#define evr3 3
639#define evr4 4
640#define evr5 5
641#define evr6 6
642#define evr7 7
643#define evr8 8
644#define evr9 9
645#define evr10 10
646#define evr11 11
647#define evr12 12
648#define evr13 13
649#define evr14 14
650#define evr15 15
651#define evr16 16
652#define evr17 17
653#define evr18 18
654#define evr19 19
655#define evr20 20
656#define evr21 21
657#define evr22 22
658#define evr23 23
659#define evr24 24
660#define evr25 25
661#define evr26 26
662#define evr27 27
663#define evr28 28
664#define evr29 29
665#define evr30 30
666#define evr31 31
667
668/* some stab codes */
669#define N_FUN 36
670#define N_RSYM 64
671#define N_SLINE 68
672#define N_SO 100
Kumar Gala5f7c6902005-09-09 15:02:25 -0500673
Kumar Gala5f7c6902005-09-09 15:02:25 -0500674#endif /* __ASSEMBLY__ */
675
676#endif /* _ASM_POWERPC_PPC_ASM_H */