Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1 | /* |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 2 | * linux/arch/arm/mach-omap2/clock2420_data.c |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 3 | * |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. |
Paul Walmsley | 93340a2 | 2010-02-22 22:09:12 -0700 | [diff] [blame] | 5 | * Copyright (C) 2004-2010 Nokia Corporation |
Tony Lindgren | a16e970 | 2008-03-18 11:56:39 +0200 | [diff] [blame] | 6 | * |
| 7 | * Contacts: |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 8 | * Richard Woodruff <r-woodruff2@ti.com> |
Tony Lindgren | a16e970 | 2008-03-18 11:56:39 +0200 | [diff] [blame] | 9 | * Paul Walmsley |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License version 2 as |
| 13 | * published by the Free Software Foundation. |
| 14 | */ |
| 15 | |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 16 | #include <linux/kernel.h> |
| 17 | #include <linux/clk.h> |
Paul Walmsley | 93340a2 | 2010-02-22 22:09:12 -0700 | [diff] [blame] | 18 | #include <linux/list.h> |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 19 | |
| 20 | #include <plat/clkdev_omap.h> |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 21 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 22 | #include "clock.h" |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 23 | #include "clock2xxx.h" |
| 24 | #include "opp2xxx.h" |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 25 | #include "prm.h" |
| 26 | #include "cm.h" |
| 27 | #include "prm-regbits-24xx.h" |
| 28 | #include "cm-regbits-24xx.h" |
| 29 | #include "sdrc.h" |
| 30 | |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 31 | #define OMAP_CM_REGADDR OMAP2420_CM_REGADDR |
| 32 | |
| 33 | /* |
| 34 | * 2420 clock tree. |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 35 | * |
| 36 | * NOTE:In many cases here we are assigning a 'default' parent. In many |
| 37 | * cases the parent is selectable. The get/set parent calls will also |
| 38 | * switch sources. |
| 39 | * |
| 40 | * Many some clocks say always_enabled, but they can be auto idled for |
| 41 | * power savings. They will always be available upon clock request. |
| 42 | * |
| 43 | * Several sources are given initial rates which may be wrong, this will |
| 44 | * be fixed up in the init func. |
| 45 | * |
| 46 | * Things are broadly separated below by clock domains. It is |
| 47 | * noteworthy that most periferals have dependencies on multiple clock |
| 48 | * domains. Many get their interface clocks from the L4 domain, but get |
| 49 | * functional clocks from fixed sources or other core domain derived |
| 50 | * clocks. |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 51 | */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 52 | |
| 53 | /* Base external input clocks */ |
| 54 | static struct clk func_32k_ck = { |
| 55 | .name = "func_32k_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 56 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 57 | .rate = 32000, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 58 | .clkdm_name = "wkup_clkdm", |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 59 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 60 | |
Paul Walmsley | f248076 | 2009-04-23 21:11:10 -0600 | [diff] [blame] | 61 | static struct clk secure_32k_ck = { |
| 62 | .name = "secure_32k_ck", |
| 63 | .ops = &clkops_null, |
| 64 | .rate = 32768, |
Paul Walmsley | f248076 | 2009-04-23 21:11:10 -0600 | [diff] [blame] | 65 | .clkdm_name = "wkup_clkdm", |
| 66 | }; |
| 67 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 68 | /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ |
| 69 | static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ |
| 70 | .name = "osc_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 71 | .ops = &clkops_oscck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 72 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 73 | .recalc = &omap2_osc_clk_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 74 | }; |
| 75 | |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 76 | /* Without modem likely 12MHz, with modem likely 13MHz */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 77 | static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ |
| 78 | .name = "sys_ck", /* ~ ref_clk also */ |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 79 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 80 | .parent = &osc_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 81 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 44da0a5 | 2010-01-26 20:13:08 -0700 | [diff] [blame] | 82 | .recalc = &omap2xxx_sys_clk_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 83 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 84 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 85 | static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ |
| 86 | .name = "alt_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 87 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 88 | .rate = 54000000, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 89 | .clkdm_name = "wkup_clkdm", |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 90 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 91 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 92 | /* |
| 93 | * Analog domain root source clocks |
| 94 | */ |
| 95 | |
| 96 | /* dpll_ck, is broken out in to special cases through clksel */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 97 | /* REVISIT: Rate changes on dpll_ck trigger a full set change. ... |
| 98 | * deal with this |
| 99 | */ |
| 100 | |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 101 | static struct dpll_data dpll_dd = { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 102 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 103 | .mult_mask = OMAP24XX_DPLL_MULT_MASK, |
| 104 | .div1_mask = OMAP24XX_DPLL_DIV_MASK, |
Russell King | c0bf313 | 2009-02-19 13:29:22 +0000 | [diff] [blame] | 105 | .clk_bypass = &sys_ck, |
| 106 | .clk_ref = &sys_ck, |
| 107 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 108 | .enable_mask = OMAP24XX_EN_DPLL_MASK, |
Paul Walmsley | 93340a2 | 2010-02-22 22:09:12 -0700 | [diff] [blame] | 109 | .max_multiplier = 1023, |
Paul Walmsley | 95f538a | 2009-01-28 12:08:44 -0700 | [diff] [blame] | 110 | .min_divider = 1, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 111 | .max_divider = 16, |
| 112 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 113 | }; |
| 114 | |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 115 | /* |
| 116 | * XXX Cannot add round_rate here yet, as this is still a composite clock, |
| 117 | * not just a DPLL |
| 118 | */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 119 | static struct clk dpll_ck = { |
| 120 | .name = "dpll_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 121 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 122 | .parent = &sys_ck, /* Can be func_32k also */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 123 | .dpll_data = &dpll_dd, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 124 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 125 | .recalc = &omap2_dpllcore_recalc, |
| 126 | .set_rate = &omap2_reprogram_dpllcore, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 127 | }; |
| 128 | |
| 129 | static struct clk apll96_ck = { |
| 130 | .name = "apll96_ck", |
Paul Walmsley | 06b1693 | 2009-12-08 16:18:46 -0700 | [diff] [blame] | 131 | .ops = &clkops_apll96, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 132 | .parent = &sys_ck, |
| 133 | .rate = 96000000, |
Paul Walmsley | 51c1954 | 2010-02-22 22:09:26 -0700 | [diff] [blame] | 134 | .flags = ENABLE_ON_INIT, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 135 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 136 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 137 | .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 138 | }; |
| 139 | |
| 140 | static struct clk apll54_ck = { |
| 141 | .name = "apll54_ck", |
Paul Walmsley | 06b1693 | 2009-12-08 16:18:46 -0700 | [diff] [blame] | 142 | .ops = &clkops_apll54, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 143 | .parent = &sys_ck, |
| 144 | .rate = 54000000, |
Paul Walmsley | 51c1954 | 2010-02-22 22:09:26 -0700 | [diff] [blame] | 145 | .flags = ENABLE_ON_INIT, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 146 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 147 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 148 | .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 149 | }; |
| 150 | |
| 151 | /* |
| 152 | * PRCM digital base sources |
| 153 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 154 | |
| 155 | /* func_54m_ck */ |
| 156 | |
| 157 | static const struct clksel_rate func_54m_apll54_rates[] = { |
| 158 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 159 | { .div = 0 }, |
| 160 | }; |
| 161 | |
| 162 | static const struct clksel_rate func_54m_alt_rates[] = { |
| 163 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 164 | { .div = 0 }, |
| 165 | }; |
| 166 | |
| 167 | static const struct clksel func_54m_clksel[] = { |
| 168 | { .parent = &apll54_ck, .rates = func_54m_apll54_rates, }, |
| 169 | { .parent = &alt_ck, .rates = func_54m_alt_rates, }, |
| 170 | { .parent = NULL }, |
| 171 | }; |
| 172 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 173 | static struct clk func_54m_ck = { |
| 174 | .name = "func_54m_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 175 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 176 | .parent = &apll54_ck, /* can also be alt_clk */ |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 177 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 178 | .init = &omap2_init_clksel_parent, |
| 179 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 180 | .clksel_mask = OMAP24XX_54M_SOURCE, |
| 181 | .clksel = func_54m_clksel, |
| 182 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 183 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 184 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 185 | static struct clk core_ck = { |
| 186 | .name = "core_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 187 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 188 | .parent = &dpll_ck, /* can also be 32k */ |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 189 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 190 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 191 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 192 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 193 | static struct clk func_96m_ck = { |
| 194 | .name = "func_96m_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 195 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 196 | .parent = &apll96_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 197 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 198 | .recalc = &followparent_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 199 | }; |
| 200 | |
| 201 | /* func_48m_ck */ |
| 202 | |
| 203 | static const struct clksel_rate func_48m_apll96_rates[] = { |
| 204 | { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 205 | { .div = 0 }, |
| 206 | }; |
| 207 | |
| 208 | static const struct clksel_rate func_48m_alt_rates[] = { |
| 209 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 210 | { .div = 0 }, |
| 211 | }; |
| 212 | |
| 213 | static const struct clksel func_48m_clksel[] = { |
| 214 | { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, |
| 215 | { .parent = &alt_ck, .rates = func_48m_alt_rates }, |
| 216 | { .parent = NULL } |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 217 | }; |
| 218 | |
| 219 | static struct clk func_48m_ck = { |
| 220 | .name = "func_48m_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 221 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 222 | .parent = &apll96_ck, /* 96M or Alt */ |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 223 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 224 | .init = &omap2_init_clksel_parent, |
| 225 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 226 | .clksel_mask = OMAP24XX_48M_SOURCE, |
| 227 | .clksel = func_48m_clksel, |
| 228 | .recalc = &omap2_clksel_recalc, |
| 229 | .round_rate = &omap2_clksel_round_rate, |
| 230 | .set_rate = &omap2_clksel_set_rate |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 231 | }; |
| 232 | |
| 233 | static struct clk func_12m_ck = { |
| 234 | .name = "func_12m_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 235 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 236 | .parent = &func_48m_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 237 | .fixed_div = 4, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 238 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e9b98f6 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 239 | .recalc = &omap_fixed_divisor_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 240 | }; |
| 241 | |
| 242 | /* Secure timer, only available in secure mode */ |
| 243 | static struct clk wdt1_osc_ck = { |
| 244 | .name = "ck_wdt1_osc", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 245 | .ops = &clkops_null, /* RMK: missing? */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 246 | .parent = &osc_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 247 | .recalc = &followparent_recalc, |
| 248 | }; |
| 249 | |
| 250 | /* |
| 251 | * The common_clkout* clksel_rate structs are common to |
| 252 | * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src. |
| 253 | * sys_clkout2_* are 2420-only, so the |
| 254 | * clksel_rate flags fields are inaccurate for those clocks. This is |
| 255 | * harmless since access to those clocks are gated by the struct clk |
| 256 | * flags fields, which mark them as 2420-only. |
| 257 | */ |
| 258 | static const struct clksel_rate common_clkout_src_core_rates[] = { |
| 259 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 260 | { .div = 0 } |
| 261 | }; |
| 262 | |
| 263 | static const struct clksel_rate common_clkout_src_sys_rates[] = { |
| 264 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 265 | { .div = 0 } |
| 266 | }; |
| 267 | |
| 268 | static const struct clksel_rate common_clkout_src_96m_rates[] = { |
| 269 | { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 270 | { .div = 0 } |
| 271 | }; |
| 272 | |
| 273 | static const struct clksel_rate common_clkout_src_54m_rates[] = { |
| 274 | { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 275 | { .div = 0 } |
| 276 | }; |
| 277 | |
| 278 | static const struct clksel common_clkout_src_clksel[] = { |
| 279 | { .parent = &core_ck, .rates = common_clkout_src_core_rates }, |
| 280 | { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, |
| 281 | { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, |
| 282 | { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, |
| 283 | { .parent = NULL } |
| 284 | }; |
| 285 | |
| 286 | static struct clk sys_clkout_src = { |
| 287 | .name = "sys_clkout_src", |
Russell King | c1168dc | 2008-11-04 21:24:00 +0000 | [diff] [blame] | 288 | .ops = &clkops_omap2_dflt, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 289 | .parent = &func_54m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 290 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 291 | .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 292 | .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, |
| 293 | .init = &omap2_init_clksel_parent, |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 294 | .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 295 | .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK, |
| 296 | .clksel = common_clkout_src_clksel, |
| 297 | .recalc = &omap2_clksel_recalc, |
| 298 | .round_rate = &omap2_clksel_round_rate, |
| 299 | .set_rate = &omap2_clksel_set_rate |
| 300 | }; |
| 301 | |
| 302 | static const struct clksel_rate common_clkout_rates[] = { |
| 303 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 304 | { .div = 2, .val = 1, .flags = RATE_IN_24XX }, |
| 305 | { .div = 4, .val = 2, .flags = RATE_IN_24XX }, |
| 306 | { .div = 8, .val = 3, .flags = RATE_IN_24XX }, |
| 307 | { .div = 16, .val = 4, .flags = RATE_IN_24XX }, |
| 308 | { .div = 0 }, |
| 309 | }; |
| 310 | |
| 311 | static const struct clksel sys_clkout_clksel[] = { |
| 312 | { .parent = &sys_clkout_src, .rates = common_clkout_rates }, |
| 313 | { .parent = NULL } |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 314 | }; |
| 315 | |
| 316 | static struct clk sys_clkout = { |
| 317 | .name = "sys_clkout", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 318 | .ops = &clkops_null, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 319 | .parent = &sys_clkout_src, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 320 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 321 | .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 322 | .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, |
| 323 | .clksel = sys_clkout_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 324 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 325 | .round_rate = &omap2_clksel_round_rate, |
| 326 | .set_rate = &omap2_clksel_set_rate |
| 327 | }; |
| 328 | |
| 329 | /* In 2430, new in 2420 ES2 */ |
| 330 | static struct clk sys_clkout2_src = { |
| 331 | .name = "sys_clkout2_src", |
Russell King | c1168dc | 2008-11-04 21:24:00 +0000 | [diff] [blame] | 332 | .ops = &clkops_omap2_dflt, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 333 | .parent = &func_54m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 334 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 335 | .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 336 | .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, |
| 337 | .init = &omap2_init_clksel_parent, |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 338 | .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 339 | .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK, |
| 340 | .clksel = common_clkout_src_clksel, |
| 341 | .recalc = &omap2_clksel_recalc, |
| 342 | .round_rate = &omap2_clksel_round_rate, |
| 343 | .set_rate = &omap2_clksel_set_rate |
| 344 | }; |
| 345 | |
| 346 | static const struct clksel sys_clkout2_clksel[] = { |
| 347 | { .parent = &sys_clkout2_src, .rates = common_clkout_rates }, |
| 348 | { .parent = NULL } |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 349 | }; |
| 350 | |
| 351 | /* In 2430, new in 2420 ES2 */ |
| 352 | static struct clk sys_clkout2 = { |
| 353 | .name = "sys_clkout2", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 354 | .ops = &clkops_null, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 355 | .parent = &sys_clkout2_src, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 356 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 357 | .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 358 | .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, |
| 359 | .clksel = sys_clkout2_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 360 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 361 | .round_rate = &omap2_clksel_round_rate, |
| 362 | .set_rate = &omap2_clksel_set_rate |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 363 | }; |
| 364 | |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 365 | static struct clk emul_ck = { |
| 366 | .name = "emul_ck", |
Russell King | c1168dc | 2008-11-04 21:24:00 +0000 | [diff] [blame] | 367 | .ops = &clkops_omap2_dflt, |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 368 | .parent = &func_54m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 369 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 370 | .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 371 | .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, |
| 372 | .recalc = &followparent_recalc, |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 373 | |
| 374 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 375 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 376 | /* |
| 377 | * MPU clock domain |
| 378 | * Clocks: |
| 379 | * MPU_FCLK, MPU_ICLK |
| 380 | * INT_M_FCLK, INT_M_I_CLK |
| 381 | * |
| 382 | * - Individual clocks are hardware managed. |
| 383 | * - Base divider comes from: CM_CLKSEL_MPU |
| 384 | * |
| 385 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 386 | static const struct clksel_rate mpu_core_rates[] = { |
| 387 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 388 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
| 389 | { .div = 4, .val = 4, .flags = RATE_IN_242X }, |
| 390 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, |
| 391 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, |
| 392 | { .div = 0 }, |
| 393 | }; |
| 394 | |
| 395 | static const struct clksel mpu_clksel[] = { |
| 396 | { .parent = &core_ck, .rates = mpu_core_rates }, |
| 397 | { .parent = NULL } |
| 398 | }; |
| 399 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 400 | static struct clk mpu_ck = { /* Control cpu */ |
| 401 | .name = "mpu_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 402 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 403 | .parent = &core_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 404 | .clkdm_name = "mpu_clkdm", |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 405 | .init = &omap2_init_clksel_parent, |
| 406 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), |
| 407 | .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 408 | .clksel = mpu_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 409 | .recalc = &omap2_clksel_recalc, |
| 410 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 411 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 412 | /* |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 413 | * DSP (2420-UMA+IVA1) clock domain |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 414 | * Clocks: |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 415 | * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 416 | * |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 417 | * Won't be too specific here. The core clock comes into this block |
| 418 | * it is divided then tee'ed. One branch goes directly to xyz enable |
| 419 | * controls. The other branch gets further divided by 2 then possibly |
| 420 | * routed into a synchronizer and out of clocks abc. |
| 421 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 422 | static const struct clksel_rate dsp_fck_core_rates[] = { |
| 423 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 424 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
| 425 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, |
| 426 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, |
| 427 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, |
| 428 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, |
| 429 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, |
| 430 | { .div = 0 }, |
| 431 | }; |
| 432 | |
| 433 | static const struct clksel dsp_fck_clksel[] = { |
| 434 | { .parent = &core_ck, .rates = dsp_fck_core_rates }, |
| 435 | { .parent = NULL } |
| 436 | }; |
| 437 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 438 | static struct clk dsp_fck = { |
| 439 | .name = "dsp_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 440 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 441 | .parent = &core_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 442 | .clkdm_name = "dsp_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 443 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
| 444 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, |
| 445 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), |
| 446 | .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK, |
| 447 | .clksel = dsp_fck_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 448 | .recalc = &omap2_clksel_recalc, |
| 449 | }; |
| 450 | |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 451 | /* DSP interface clock */ |
| 452 | static const struct clksel_rate dsp_irate_ick_rates[] = { |
| 453 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 454 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 455 | { .div = 0 }, |
| 456 | }; |
| 457 | |
| 458 | static const struct clksel dsp_irate_ick_clksel[] = { |
| 459 | { .parent = &dsp_fck, .rates = dsp_irate_ick_rates }, |
| 460 | { .parent = NULL } |
| 461 | }; |
| 462 | |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 463 | /* This clock does not exist as such in the TRM. */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 464 | static struct clk dsp_irate_ick = { |
| 465 | .name = "dsp_irate_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 466 | .ops = &clkops_null, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 467 | .parent = &dsp_fck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 468 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), |
| 469 | .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, |
| 470 | .clksel = dsp_irate_ick_clksel, |
| 471 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 472 | }; |
| 473 | |
| 474 | /* 2420 only */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 475 | static struct clk dsp_ick = { |
| 476 | .name = "dsp_ick", /* apparently ipi and isp */ |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 477 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 478 | .parent = &dsp_irate_ick, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 479 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), |
| 480 | .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */ |
| 481 | }; |
| 482 | |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 483 | /* |
| 484 | * The IVA1 is an ARM7 core on the 2420 that has nothing to do with |
| 485 | * the C54x, but which is contained in the DSP powerdomain. Does not |
| 486 | * exist on later OMAPs. |
| 487 | */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 488 | static struct clk iva1_ifck = { |
| 489 | .name = "iva1_ifck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 490 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 491 | .parent = &core_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 492 | .clkdm_name = "iva1_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 493 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
| 494 | .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, |
| 495 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), |
| 496 | .clksel_mask = OMAP2420_CLKSEL_IVA_MASK, |
| 497 | .clksel = dsp_fck_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 498 | .recalc = &omap2_clksel_recalc, |
| 499 | }; |
| 500 | |
| 501 | /* IVA1 mpu/int/i/f clocks are /2 of parent */ |
| 502 | static struct clk iva1_mpu_int_ifck = { |
| 503 | .name = "iva1_mpu_int_ifck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 504 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 505 | .parent = &iva1_ifck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 506 | .clkdm_name = "iva1_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 507 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
| 508 | .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, |
| 509 | .fixed_div = 2, |
Paul Walmsley | e9b98f6 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 510 | .recalc = &omap_fixed_divisor_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 511 | }; |
| 512 | |
| 513 | /* |
| 514 | * L3 clock domain |
| 515 | * L3 clocks are used for both interface and functional clocks to |
| 516 | * multiple entities. Some of these clocks are completely managed |
| 517 | * by hardware, and some others allow software control. Hardware |
| 518 | * managed ones general are based on directly CLK_REQ signals and |
| 519 | * various auto idle settings. The functional spec sets many of these |
| 520 | * as 'tie-high' for their enables. |
| 521 | * |
| 522 | * I-CLOCKS: |
| 523 | * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA |
| 524 | * CAM, HS-USB. |
| 525 | * F-CLOCK |
| 526 | * SSI. |
| 527 | * |
| 528 | * GPMC memories and SDRC have timing and clock sensitive registers which |
| 529 | * may very well need notification when the clock changes. Currently for low |
| 530 | * operating points, these are taken care of in sleep.S. |
| 531 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 532 | static const struct clksel_rate core_l3_core_rates[] = { |
| 533 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
| 534 | { .div = 2, .val = 2, .flags = RATE_IN_242X }, |
| 535 | { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 536 | { .div = 6, .val = 6, .flags = RATE_IN_24XX }, |
| 537 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, |
| 538 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, |
| 539 | { .div = 16, .val = 16, .flags = RATE_IN_242X }, |
| 540 | { .div = 0 } |
| 541 | }; |
| 542 | |
| 543 | static const struct clksel core_l3_clksel[] = { |
| 544 | { .parent = &core_ck, .rates = core_l3_core_rates }, |
| 545 | { .parent = NULL } |
| 546 | }; |
| 547 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 548 | static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ |
| 549 | .name = "core_l3_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 550 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 551 | .parent = &core_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 552 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 553 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 554 | .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, |
| 555 | .clksel = core_l3_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 556 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 557 | }; |
| 558 | |
| 559 | /* usb_l4_ick */ |
| 560 | static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { |
| 561 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
| 562 | { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 563 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, |
| 564 | { .div = 0 } |
| 565 | }; |
| 566 | |
| 567 | static const struct clksel usb_l4_ick_clksel[] = { |
| 568 | { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, |
| 569 | { .parent = NULL }, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 570 | }; |
| 571 | |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 572 | /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 573 | static struct clk usb_l4_ick = { /* FS-USB interface clock */ |
| 574 | .name = "usb_l4_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 575 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | fde0fd4 | 2006-01-17 15:31:18 -0800 | [diff] [blame] | 576 | .parent = &core_l3_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 577 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 578 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 579 | .enable_bit = OMAP24XX_EN_USB_SHIFT, |
| 580 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 581 | .clksel_mask = OMAP24XX_CLKSEL_USB_MASK, |
| 582 | .clksel = usb_l4_ick_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 583 | .recalc = &omap2_clksel_recalc, |
| 584 | }; |
| 585 | |
| 586 | /* |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 587 | * L4 clock management domain |
| 588 | * |
| 589 | * This domain contains lots of interface clocks from the L4 interface, some |
| 590 | * functional clocks. Fixed APLL functional source clocks are managed in |
| 591 | * this domain. |
| 592 | */ |
| 593 | static const struct clksel_rate l4_core_l3_rates[] = { |
| 594 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 595 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
| 596 | { .div = 0 } |
| 597 | }; |
| 598 | |
| 599 | static const struct clksel l4_clksel[] = { |
| 600 | { .parent = &core_l3_ck, .rates = l4_core_l3_rates }, |
| 601 | { .parent = NULL } |
| 602 | }; |
| 603 | |
| 604 | static struct clk l4_ck = { /* used both as an ick and fck */ |
| 605 | .name = "l4_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 606 | .ops = &clkops_null, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 607 | .parent = &core_l3_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 608 | .clkdm_name = "core_l4_clkdm", |
| 609 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 610 | .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, |
| 611 | .clksel = l4_clksel, |
| 612 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 613 | }; |
| 614 | |
| 615 | /* |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 616 | * SSI is in L3 management domain, its direct parent is core not l3, |
| 617 | * many core power domain entities are grouped into the L3 clock |
| 618 | * domain. |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 619 | * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 620 | * |
| 621 | * ssr = core/1/2/3/4/5, sst = 1/2 ssr. |
| 622 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 623 | static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { |
| 624 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
| 625 | { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 626 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, |
| 627 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 628 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, |
| 629 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, |
| 630 | { .div = 0 } |
| 631 | }; |
| 632 | |
| 633 | static const struct clksel ssi_ssr_sst_fck_clksel[] = { |
| 634 | { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, |
| 635 | { .parent = NULL } |
| 636 | }; |
| 637 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 638 | static struct clk ssi_ssr_sst_fck = { |
| 639 | .name = "ssi_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 640 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 641 | .parent = &core_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 642 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 643 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 644 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, |
| 645 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 646 | .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK, |
| 647 | .clksel = ssi_ssr_sst_fck_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 648 | .recalc = &omap2_clksel_recalc, |
| 649 | }; |
| 650 | |
Paul Walmsley | 9299fd8 | 2009-01-27 19:12:54 -0700 | [diff] [blame] | 651 | /* |
| 652 | * Presumably this is the same as SSI_ICLK. |
| 653 | * TRM contradicts itself on what clockdomain SSI_ICLK is in |
| 654 | */ |
| 655 | static struct clk ssi_l4_ick = { |
| 656 | .name = "ssi_l4_ick", |
| 657 | .ops = &clkops_omap2_dflt_wait, |
| 658 | .parent = &l4_ck, |
| 659 | .clkdm_name = "core_l4_clkdm", |
| 660 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 661 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, |
| 662 | .recalc = &followparent_recalc, |
| 663 | }; |
| 664 | |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 665 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 666 | /* |
| 667 | * GFX clock domain |
| 668 | * Clocks: |
| 669 | * GFX_FCLK, GFX_ICLK |
| 670 | * GFX_CG1(2d), GFX_CG2(3d) |
| 671 | * |
| 672 | * GFX_FCLK runs from L3, and is divided by (1,2,3,4) |
| 673 | * The 2d and 3d clocks run at a hardware determined |
| 674 | * divided value of fclk. |
| 675 | * |
| 676 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 677 | |
| 678 | /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */ |
| 679 | static const struct clksel gfx_fck_clksel[] = { |
| 680 | { .parent = &core_l3_ck, .rates = gfx_l3_rates }, |
| 681 | { .parent = NULL }, |
| 682 | }; |
| 683 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 684 | static struct clk gfx_3d_fck = { |
| 685 | .name = "gfx_3d_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 686 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 687 | .parent = &core_l3_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 688 | .clkdm_name = "gfx_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 689 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
| 690 | .enable_bit = OMAP24XX_EN_3D_SHIFT, |
| 691 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), |
| 692 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, |
| 693 | .clksel = gfx_fck_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 694 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 695 | .round_rate = &omap2_clksel_round_rate, |
| 696 | .set_rate = &omap2_clksel_set_rate |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 697 | }; |
| 698 | |
| 699 | static struct clk gfx_2d_fck = { |
| 700 | .name = "gfx_2d_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 701 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 702 | .parent = &core_l3_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 703 | .clkdm_name = "gfx_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 704 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
| 705 | .enable_bit = OMAP24XX_EN_2D_SHIFT, |
| 706 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), |
| 707 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, |
| 708 | .clksel = gfx_fck_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 709 | .recalc = &omap2_clksel_recalc, |
| 710 | }; |
| 711 | |
| 712 | static struct clk gfx_ick = { |
| 713 | .name = "gfx_ick", /* From l3 */ |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 714 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 715 | .parent = &core_l3_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 716 | .clkdm_name = "gfx_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 717 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), |
| 718 | .enable_bit = OMAP_EN_GFX_SHIFT, |
| 719 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 720 | }; |
| 721 | |
| 722 | /* |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 723 | * DSS clock domain |
| 724 | * CLOCKs: |
| 725 | * DSS_L4_ICLK, DSS_L3_ICLK, |
| 726 | * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK |
| 727 | * |
| 728 | * DSS is both initiator and target. |
| 729 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 730 | /* XXX Add RATE_NOT_VALIDATED */ |
| 731 | |
| 732 | static const struct clksel_rate dss1_fck_sys_rates[] = { |
| 733 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 734 | { .div = 0 } |
| 735 | }; |
| 736 | |
| 737 | static const struct clksel_rate dss1_fck_core_rates[] = { |
| 738 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
| 739 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
| 740 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, |
| 741 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, |
| 742 | { .div = 5, .val = 5, .flags = RATE_IN_24XX }, |
| 743 | { .div = 6, .val = 6, .flags = RATE_IN_24XX }, |
| 744 | { .div = 8, .val = 8, .flags = RATE_IN_24XX }, |
| 745 | { .div = 9, .val = 9, .flags = RATE_IN_24XX }, |
| 746 | { .div = 12, .val = 12, .flags = RATE_IN_24XX }, |
| 747 | { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 748 | { .div = 0 } |
| 749 | }; |
| 750 | |
| 751 | static const struct clksel dss1_fck_clksel[] = { |
| 752 | { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, |
| 753 | { .parent = &core_ck, .rates = dss1_fck_core_rates }, |
| 754 | { .parent = NULL }, |
| 755 | }; |
| 756 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 757 | static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ |
| 758 | .name = "dss_ick", |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 759 | .ops = &clkops_omap2_dflt, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 760 | .parent = &l4_ck, /* really both l3 and l4 */ |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 761 | .clkdm_name = "dss_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 762 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 763 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, |
| 764 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 765 | }; |
| 766 | |
| 767 | static struct clk dss1_fck = { |
| 768 | .name = "dss1_fck", |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 769 | .ops = &clkops_omap2_dflt, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 770 | .parent = &core_ck, /* Core or sys */ |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 771 | .clkdm_name = "dss_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 772 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 773 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, |
| 774 | .init = &omap2_init_clksel_parent, |
| 775 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 776 | .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK, |
| 777 | .clksel = dss1_fck_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 778 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 779 | }; |
| 780 | |
| 781 | static const struct clksel_rate dss2_fck_sys_rates[] = { |
| 782 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 783 | { .div = 0 } |
| 784 | }; |
| 785 | |
| 786 | static const struct clksel_rate dss2_fck_48m_rates[] = { |
| 787 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 788 | { .div = 0 } |
| 789 | }; |
| 790 | |
| 791 | static const struct clksel dss2_fck_clksel[] = { |
| 792 | { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, |
| 793 | { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, |
| 794 | { .parent = NULL } |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 795 | }; |
| 796 | |
| 797 | static struct clk dss2_fck = { /* Alt clk used in power management */ |
| 798 | .name = "dss2_fck", |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 799 | .ops = &clkops_omap2_dflt, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 800 | .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 801 | .clkdm_name = "dss_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 802 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 803 | .enable_bit = OMAP24XX_EN_DSS2_SHIFT, |
| 804 | .init = &omap2_init_clksel_parent, |
| 805 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 806 | .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK, |
| 807 | .clksel = dss2_fck_clksel, |
| 808 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 809 | }; |
| 810 | |
| 811 | static struct clk dss_54m_fck = { /* Alt clk used in power management */ |
| 812 | .name = "dss_54m_fck", /* 54m tv clk */ |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 813 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 814 | .parent = &func_54m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 815 | .clkdm_name = "dss_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 816 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 817 | .enable_bit = OMAP24XX_EN_TV_SHIFT, |
| 818 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 819 | }; |
| 820 | |
| 821 | /* |
| 822 | * CORE power domain ICLK & FCLK defines. |
| 823 | * Many of the these can have more than one possible parent. Entries |
| 824 | * here will likely have an L4 interface parent, and may have multiple |
| 825 | * functional clock parents. |
| 826 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 827 | static const struct clksel_rate gpt_alt_rates[] = { |
| 828 | { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 829 | { .div = 0 } |
| 830 | }; |
| 831 | |
| 832 | static const struct clksel omap24xx_gpt_clksel[] = { |
| 833 | { .parent = &func_32k_ck, .rates = gpt_32k_rates }, |
| 834 | { .parent = &sys_ck, .rates = gpt_sys_rates }, |
| 835 | { .parent = &alt_ck, .rates = gpt_alt_rates }, |
| 836 | { .parent = NULL }, |
| 837 | }; |
| 838 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 839 | static struct clk gpt1_ick = { |
| 840 | .name = "gpt1_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 841 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 842 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 843 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 844 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 845 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, |
| 846 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 847 | }; |
| 848 | |
| 849 | static struct clk gpt1_fck = { |
| 850 | .name = "gpt1_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 851 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 852 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 853 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 854 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 855 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, |
| 856 | .init = &omap2_init_clksel_parent, |
| 857 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), |
| 858 | .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK, |
| 859 | .clksel = omap24xx_gpt_clksel, |
| 860 | .recalc = &omap2_clksel_recalc, |
| 861 | .round_rate = &omap2_clksel_round_rate, |
| 862 | .set_rate = &omap2_clksel_set_rate |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 863 | }; |
| 864 | |
| 865 | static struct clk gpt2_ick = { |
| 866 | .name = "gpt2_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 867 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 868 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 869 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 870 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 871 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, |
| 872 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 873 | }; |
| 874 | |
| 875 | static struct clk gpt2_fck = { |
| 876 | .name = "gpt2_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 877 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 878 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 879 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 880 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 881 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, |
| 882 | .init = &omap2_init_clksel_parent, |
| 883 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 884 | .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK, |
| 885 | .clksel = omap24xx_gpt_clksel, |
| 886 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 887 | }; |
| 888 | |
| 889 | static struct clk gpt3_ick = { |
| 890 | .name = "gpt3_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 891 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 892 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 893 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 894 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 895 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, |
| 896 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 897 | }; |
| 898 | |
| 899 | static struct clk gpt3_fck = { |
| 900 | .name = "gpt3_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 901 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 902 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 903 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 904 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 905 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, |
| 906 | .init = &omap2_init_clksel_parent, |
| 907 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 908 | .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK, |
| 909 | .clksel = omap24xx_gpt_clksel, |
| 910 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 911 | }; |
| 912 | |
| 913 | static struct clk gpt4_ick = { |
| 914 | .name = "gpt4_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 915 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 916 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 917 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 918 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 919 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, |
| 920 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 921 | }; |
| 922 | |
| 923 | static struct clk gpt4_fck = { |
| 924 | .name = "gpt4_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 925 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 926 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 927 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 928 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 929 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, |
| 930 | .init = &omap2_init_clksel_parent, |
| 931 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 932 | .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK, |
| 933 | .clksel = omap24xx_gpt_clksel, |
| 934 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 935 | }; |
| 936 | |
| 937 | static struct clk gpt5_ick = { |
| 938 | .name = "gpt5_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 939 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 940 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 941 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 942 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 943 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, |
| 944 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 945 | }; |
| 946 | |
| 947 | static struct clk gpt5_fck = { |
| 948 | .name = "gpt5_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 949 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 950 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 951 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 952 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 953 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, |
| 954 | .init = &omap2_init_clksel_parent, |
| 955 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 956 | .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK, |
| 957 | .clksel = omap24xx_gpt_clksel, |
| 958 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 959 | }; |
| 960 | |
| 961 | static struct clk gpt6_ick = { |
| 962 | .name = "gpt6_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 963 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 964 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 965 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 966 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 967 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, |
| 968 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 969 | }; |
| 970 | |
| 971 | static struct clk gpt6_fck = { |
| 972 | .name = "gpt6_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 973 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 974 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 975 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 976 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 977 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, |
| 978 | .init = &omap2_init_clksel_parent, |
| 979 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 980 | .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK, |
| 981 | .clksel = omap24xx_gpt_clksel, |
| 982 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 983 | }; |
| 984 | |
| 985 | static struct clk gpt7_ick = { |
| 986 | .name = "gpt7_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 987 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 988 | .parent = &l4_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 989 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 990 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, |
| 991 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 992 | }; |
| 993 | |
| 994 | static struct clk gpt7_fck = { |
| 995 | .name = "gpt7_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 996 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 997 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 998 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 999 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1000 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, |
| 1001 | .init = &omap2_init_clksel_parent, |
| 1002 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 1003 | .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK, |
| 1004 | .clksel = omap24xx_gpt_clksel, |
| 1005 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1006 | }; |
| 1007 | |
| 1008 | static struct clk gpt8_ick = { |
| 1009 | .name = "gpt8_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1010 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1011 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1012 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1013 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1014 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, |
| 1015 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1016 | }; |
| 1017 | |
| 1018 | static struct clk gpt8_fck = { |
| 1019 | .name = "gpt8_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1020 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1021 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1022 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1023 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1024 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, |
| 1025 | .init = &omap2_init_clksel_parent, |
| 1026 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 1027 | .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK, |
| 1028 | .clksel = omap24xx_gpt_clksel, |
| 1029 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1030 | }; |
| 1031 | |
| 1032 | static struct clk gpt9_ick = { |
| 1033 | .name = "gpt9_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1034 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1035 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1036 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1037 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1038 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, |
| 1039 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1040 | }; |
| 1041 | |
| 1042 | static struct clk gpt9_fck = { |
| 1043 | .name = "gpt9_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1044 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1045 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1046 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1047 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1048 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, |
| 1049 | .init = &omap2_init_clksel_parent, |
| 1050 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 1051 | .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK, |
| 1052 | .clksel = omap24xx_gpt_clksel, |
| 1053 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1054 | }; |
| 1055 | |
| 1056 | static struct clk gpt10_ick = { |
| 1057 | .name = "gpt10_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1058 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1059 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1060 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1061 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1062 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, |
| 1063 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1064 | }; |
| 1065 | |
| 1066 | static struct clk gpt10_fck = { |
| 1067 | .name = "gpt10_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1068 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1069 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1070 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1071 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1072 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, |
| 1073 | .init = &omap2_init_clksel_parent, |
| 1074 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 1075 | .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK, |
| 1076 | .clksel = omap24xx_gpt_clksel, |
| 1077 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1078 | }; |
| 1079 | |
| 1080 | static struct clk gpt11_ick = { |
| 1081 | .name = "gpt11_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1082 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1083 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1084 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1085 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1086 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, |
| 1087 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1088 | }; |
| 1089 | |
| 1090 | static struct clk gpt11_fck = { |
| 1091 | .name = "gpt11_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1092 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1093 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1094 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1095 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1096 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, |
| 1097 | .init = &omap2_init_clksel_parent, |
| 1098 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 1099 | .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK, |
| 1100 | .clksel = omap24xx_gpt_clksel, |
| 1101 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1102 | }; |
| 1103 | |
| 1104 | static struct clk gpt12_ick = { |
| 1105 | .name = "gpt12_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1106 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1107 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1108 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1109 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1110 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, |
| 1111 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1112 | }; |
| 1113 | |
| 1114 | static struct clk gpt12_fck = { |
| 1115 | .name = "gpt12_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1116 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | f248076 | 2009-04-23 21:11:10 -0600 | [diff] [blame] | 1117 | .parent = &secure_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1118 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1119 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1120 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, |
| 1121 | .init = &omap2_init_clksel_parent, |
| 1122 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 1123 | .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK, |
| 1124 | .clksel = omap24xx_gpt_clksel, |
| 1125 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1126 | }; |
| 1127 | |
| 1128 | static struct clk mcbsp1_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1129 | .name = "mcbsp1_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1130 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1131 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1132 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1133 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1134 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, |
| 1135 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1136 | }; |
| 1137 | |
| 1138 | static struct clk mcbsp1_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1139 | .name = "mcbsp1_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1140 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1141 | .parent = &func_96m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1142 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1143 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1144 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, |
| 1145 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1146 | }; |
| 1147 | |
| 1148 | static struct clk mcbsp2_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1149 | .name = "mcbsp2_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1150 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1151 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1152 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1153 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1154 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, |
| 1155 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1156 | }; |
| 1157 | |
| 1158 | static struct clk mcbsp2_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1159 | .name = "mcbsp2_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1160 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1161 | .parent = &func_96m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1162 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1163 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1164 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, |
| 1165 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1166 | }; |
| 1167 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1168 | static struct clk mcspi1_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1169 | .name = "mcspi1_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1170 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1171 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1172 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1173 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1174 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, |
| 1175 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1176 | }; |
| 1177 | |
| 1178 | static struct clk mcspi1_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1179 | .name = "mcspi1_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1180 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1181 | .parent = &func_48m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1182 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1183 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1184 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, |
| 1185 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1186 | }; |
| 1187 | |
| 1188 | static struct clk mcspi2_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1189 | .name = "mcspi2_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1190 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1191 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1192 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1193 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1194 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, |
| 1195 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1196 | }; |
| 1197 | |
| 1198 | static struct clk mcspi2_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1199 | .name = "mcspi2_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1200 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1201 | .parent = &func_48m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1202 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1203 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1204 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, |
| 1205 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1206 | }; |
| 1207 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1208 | static struct clk uart1_ick = { |
| 1209 | .name = "uart1_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1210 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1211 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1212 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1213 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1214 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, |
| 1215 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1216 | }; |
| 1217 | |
| 1218 | static struct clk uart1_fck = { |
| 1219 | .name = "uart1_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1220 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1221 | .parent = &func_48m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1222 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1223 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1224 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, |
| 1225 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1226 | }; |
| 1227 | |
| 1228 | static struct clk uart2_ick = { |
| 1229 | .name = "uart2_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1230 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1231 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1232 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1233 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1234 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, |
| 1235 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1236 | }; |
| 1237 | |
| 1238 | static struct clk uart2_fck = { |
| 1239 | .name = "uart2_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1240 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1241 | .parent = &func_48m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1242 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1243 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1244 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, |
| 1245 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1246 | }; |
| 1247 | |
| 1248 | static struct clk uart3_ick = { |
| 1249 | .name = "uart3_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1250 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1251 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1252 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1253 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1254 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, |
| 1255 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1256 | }; |
| 1257 | |
| 1258 | static struct clk uart3_fck = { |
| 1259 | .name = "uart3_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1260 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1261 | .parent = &func_48m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1262 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1263 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1264 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, |
| 1265 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1266 | }; |
| 1267 | |
| 1268 | static struct clk gpios_ick = { |
| 1269 | .name = "gpios_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1270 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1271 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1272 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1273 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 1274 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 1275 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1276 | }; |
| 1277 | |
| 1278 | static struct clk gpios_fck = { |
| 1279 | .name = "gpios_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1280 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1281 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1282 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1283 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 1284 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 1285 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1286 | }; |
| 1287 | |
| 1288 | static struct clk mpu_wdt_ick = { |
| 1289 | .name = "mpu_wdt_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1290 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1291 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1292 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1293 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 1294 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, |
| 1295 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1296 | }; |
| 1297 | |
| 1298 | static struct clk mpu_wdt_fck = { |
| 1299 | .name = "mpu_wdt_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1300 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1301 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1302 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1303 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 1304 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, |
| 1305 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1306 | }; |
| 1307 | |
| 1308 | static struct clk sync_32k_ick = { |
| 1309 | .name = "sync_32k_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1310 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1311 | .parent = &l4_ck, |
Russell King | 8ad8ff6 | 2009-01-19 15:27:29 +0000 | [diff] [blame] | 1312 | .flags = ENABLE_ON_INIT, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1313 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1314 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 1315 | .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, |
| 1316 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1317 | }; |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1318 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1319 | static struct clk wdt1_ick = { |
| 1320 | .name = "wdt1_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1321 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1322 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1323 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1324 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 1325 | .enable_bit = OMAP24XX_EN_WDT1_SHIFT, |
| 1326 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1327 | }; |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1328 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1329 | static struct clk omapctrl_ick = { |
| 1330 | .name = "omapctrl_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1331 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1332 | .parent = &l4_ck, |
Russell King | 8ad8ff6 | 2009-01-19 15:27:29 +0000 | [diff] [blame] | 1333 | .flags = ENABLE_ON_INIT, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1334 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1335 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 1336 | .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, |
| 1337 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1338 | }; |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1339 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1340 | static struct clk cam_ick = { |
| 1341 | .name = "cam_ick", |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 1342 | .ops = &clkops_omap2_dflt, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1343 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1344 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1345 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1346 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, |
| 1347 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1348 | }; |
| 1349 | |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1350 | /* |
| 1351 | * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be |
| 1352 | * split into two separate clocks, since the parent clocks are different |
| 1353 | * and the clockdomains are also different. |
| 1354 | */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1355 | static struct clk cam_fck = { |
| 1356 | .name = "cam_fck", |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 1357 | .ops = &clkops_omap2_dflt, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1358 | .parent = &func_96m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1359 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1360 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1361 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, |
| 1362 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1363 | }; |
| 1364 | |
| 1365 | static struct clk mailboxes_ick = { |
| 1366 | .name = "mailboxes_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1367 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1368 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1369 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1370 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1371 | .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, |
| 1372 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1373 | }; |
| 1374 | |
| 1375 | static struct clk wdt4_ick = { |
| 1376 | .name = "wdt4_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1377 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1378 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1379 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1380 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1381 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, |
| 1382 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1383 | }; |
| 1384 | |
| 1385 | static struct clk wdt4_fck = { |
| 1386 | .name = "wdt4_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1387 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1388 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1389 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1390 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1391 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, |
| 1392 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1393 | }; |
| 1394 | |
| 1395 | static struct clk wdt3_ick = { |
| 1396 | .name = "wdt3_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1397 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1398 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1399 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1400 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1401 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, |
| 1402 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1403 | }; |
| 1404 | |
| 1405 | static struct clk wdt3_fck = { |
| 1406 | .name = "wdt3_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1407 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1408 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1409 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1410 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1411 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, |
| 1412 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1413 | }; |
| 1414 | |
| 1415 | static struct clk mspro_ick = { |
| 1416 | .name = "mspro_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1417 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1418 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1419 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1420 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1421 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, |
| 1422 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1423 | }; |
| 1424 | |
| 1425 | static struct clk mspro_fck = { |
| 1426 | .name = "mspro_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1427 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1428 | .parent = &func_96m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1429 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1430 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1431 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, |
| 1432 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1433 | }; |
| 1434 | |
| 1435 | static struct clk mmc_ick = { |
| 1436 | .name = "mmc_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1437 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1438 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1439 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1440 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1441 | .enable_bit = OMAP2420_EN_MMC_SHIFT, |
| 1442 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1443 | }; |
| 1444 | |
| 1445 | static struct clk mmc_fck = { |
| 1446 | .name = "mmc_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1447 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1448 | .parent = &func_96m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1449 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1450 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1451 | .enable_bit = OMAP2420_EN_MMC_SHIFT, |
| 1452 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1453 | }; |
| 1454 | |
| 1455 | static struct clk fac_ick = { |
| 1456 | .name = "fac_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1457 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1458 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1459 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1460 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1461 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, |
| 1462 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1463 | }; |
| 1464 | |
| 1465 | static struct clk fac_fck = { |
| 1466 | .name = "fac_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1467 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1468 | .parent = &func_12m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1469 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1470 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1471 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, |
| 1472 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1473 | }; |
| 1474 | |
| 1475 | static struct clk eac_ick = { |
| 1476 | .name = "eac_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1477 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1478 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1479 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1480 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1481 | .enable_bit = OMAP2420_EN_EAC_SHIFT, |
| 1482 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1483 | }; |
| 1484 | |
| 1485 | static struct clk eac_fck = { |
| 1486 | .name = "eac_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1487 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1488 | .parent = &func_96m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1489 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1490 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1491 | .enable_bit = OMAP2420_EN_EAC_SHIFT, |
| 1492 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1493 | }; |
| 1494 | |
| 1495 | static struct clk hdq_ick = { |
| 1496 | .name = "hdq_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1497 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1498 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1499 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1500 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1501 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, |
| 1502 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1503 | }; |
| 1504 | |
| 1505 | static struct clk hdq_fck = { |
| 1506 | .name = "hdq_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1507 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1508 | .parent = &func_12m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1509 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1510 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1511 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, |
| 1512 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1513 | }; |
| 1514 | |
| 1515 | static struct clk i2c2_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1516 | .name = "i2c2_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1517 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1518 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1519 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1520 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1521 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, |
| 1522 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1523 | }; |
| 1524 | |
| 1525 | static struct clk i2c2_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1526 | .name = "i2c2_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1527 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1528 | .parent = &func_12m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1529 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1530 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1531 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, |
| 1532 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1533 | }; |
| 1534 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1535 | static struct clk i2c1_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1536 | .name = "i2c1_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1537 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1538 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1539 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1540 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1541 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, |
| 1542 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1543 | }; |
| 1544 | |
| 1545 | static struct clk i2c1_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1546 | .name = "i2c1_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1547 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1548 | .parent = &func_12m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1549 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1550 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1551 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, |
| 1552 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1553 | }; |
| 1554 | |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1555 | static struct clk gpmc_fck = { |
| 1556 | .name = "gpmc_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 1557 | .ops = &clkops_null, /* RMK: missing? */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1558 | .parent = &core_l3_ck, |
Russell King | 8ad8ff6 | 2009-01-19 15:27:29 +0000 | [diff] [blame] | 1559 | .flags = ENABLE_ON_INIT, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1560 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1561 | .recalc = &followparent_recalc, |
| 1562 | }; |
| 1563 | |
| 1564 | static struct clk sdma_fck = { |
| 1565 | .name = "sdma_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 1566 | .ops = &clkops_null, /* RMK: missing? */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1567 | .parent = &core_l3_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1568 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1569 | .recalc = &followparent_recalc, |
| 1570 | }; |
| 1571 | |
| 1572 | static struct clk sdma_ick = { |
| 1573 | .name = "sdma_ick", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 1574 | .ops = &clkops_null, /* RMK: missing? */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1575 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1576 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1577 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1578 | }; |
| 1579 | |
| 1580 | static struct clk vlynq_ick = { |
| 1581 | .name = "vlynq_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1582 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1583 | .parent = &core_l3_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1584 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1585 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1586 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, |
| 1587 | .recalc = &followparent_recalc, |
| 1588 | }; |
| 1589 | |
| 1590 | static const struct clksel_rate vlynq_fck_96m_rates[] = { |
| 1591 | { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE }, |
| 1592 | { .div = 0 } |
| 1593 | }; |
| 1594 | |
| 1595 | static const struct clksel_rate vlynq_fck_core_rates[] = { |
| 1596 | { .div = 1, .val = 1, .flags = RATE_IN_242X }, |
| 1597 | { .div = 2, .val = 2, .flags = RATE_IN_242X }, |
| 1598 | { .div = 3, .val = 3, .flags = RATE_IN_242X }, |
| 1599 | { .div = 4, .val = 4, .flags = RATE_IN_242X }, |
| 1600 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, |
| 1601 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, |
| 1602 | { .div = 9, .val = 9, .flags = RATE_IN_242X }, |
| 1603 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, |
| 1604 | { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE }, |
| 1605 | { .div = 18, .val = 18, .flags = RATE_IN_242X }, |
| 1606 | { .div = 0 } |
| 1607 | }; |
| 1608 | |
| 1609 | static const struct clksel vlynq_fck_clksel[] = { |
| 1610 | { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates }, |
| 1611 | { .parent = &core_ck, .rates = vlynq_fck_core_rates }, |
| 1612 | { .parent = NULL } |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1613 | }; |
| 1614 | |
| 1615 | static struct clk vlynq_fck = { |
| 1616 | .name = "vlynq_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1617 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1618 | .parent = &func_96m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1619 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1620 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1621 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, |
| 1622 | .init = &omap2_init_clksel_parent, |
| 1623 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 1624 | .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK, |
| 1625 | .clksel = vlynq_fck_clksel, |
| 1626 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1627 | }; |
| 1628 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1629 | static struct clk des_ick = { |
| 1630 | .name = "des_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1631 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1632 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1633 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1634 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 1635 | .enable_bit = OMAP24XX_EN_DES_SHIFT, |
| 1636 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1637 | }; |
| 1638 | |
| 1639 | static struct clk sha_ick = { |
| 1640 | .name = "sha_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1641 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1642 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1643 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1644 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 1645 | .enable_bit = OMAP24XX_EN_SHA_SHIFT, |
| 1646 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1647 | }; |
| 1648 | |
| 1649 | static struct clk rng_ick = { |
| 1650 | .name = "rng_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1651 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1652 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1653 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1654 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 1655 | .enable_bit = OMAP24XX_EN_RNG_SHIFT, |
| 1656 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1657 | }; |
| 1658 | |
| 1659 | static struct clk aes_ick = { |
| 1660 | .name = "aes_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1661 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1662 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1663 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1664 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 1665 | .enable_bit = OMAP24XX_EN_AES_SHIFT, |
| 1666 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1667 | }; |
| 1668 | |
| 1669 | static struct clk pka_ick = { |
| 1670 | .name = "pka_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1671 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1672 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1673 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1674 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 1675 | .enable_bit = OMAP24XX_EN_PKA_SHIFT, |
| 1676 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1677 | }; |
| 1678 | |
| 1679 | static struct clk usb_fck = { |
| 1680 | .name = "usb_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1681 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1682 | .parent = &func_48m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1683 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1684 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1685 | .enable_bit = OMAP24XX_EN_USB_SHIFT, |
| 1686 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1687 | }; |
| 1688 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1689 | /* |
| 1690 | * This clock is a composite clock which does entire set changes then |
| 1691 | * forces a rebalance. It keys on the MPU speed, but it really could |
| 1692 | * be any key speed part of a set in the rate table. |
| 1693 | * |
| 1694 | * to really change a set, you need memory table sets which get changed |
| 1695 | * in sram, pre-notifiers & post notifiers, changing the top set, without |
| 1696 | * having low level display recalc's won't work... this is why dpm notifiers |
| 1697 | * work, isr's off, walk a list of clocks already _off_ and not messing with |
| 1698 | * the bus. |
| 1699 | * |
| 1700 | * This clock should have no parent. It embodies the entire upper level |
| 1701 | * active set. A parent will mess up some of the init also. |
| 1702 | */ |
| 1703 | static struct clk virt_prcm_set = { |
| 1704 | .name = "virt_prcm_set", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 1705 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1706 | .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1707 | .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1708 | .set_rate = &omap2_select_table_rate, |
| 1709 | .round_rate = &omap2_round_to_table_rate, |
| 1710 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1711 | |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1712 | |
| 1713 | /* |
| 1714 | * clkdev integration |
| 1715 | */ |
| 1716 | |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1717 | static struct omap_clk omap2420_clks[] = { |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1718 | /* external root sources */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1719 | CLK(NULL, "func_32k_ck", &func_32k_ck, CK_242X), |
| 1720 | CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_242X), |
| 1721 | CLK(NULL, "osc_ck", &osc_ck, CK_242X), |
| 1722 | CLK(NULL, "sys_ck", &sys_ck, CK_242X), |
| 1723 | CLK(NULL, "alt_ck", &alt_ck, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1724 | /* internal analog sources */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1725 | CLK(NULL, "dpll_ck", &dpll_ck, CK_242X), |
| 1726 | CLK(NULL, "apll96_ck", &apll96_ck, CK_242X), |
| 1727 | CLK(NULL, "apll54_ck", &apll54_ck, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1728 | /* internal prcm root sources */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1729 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X), |
| 1730 | CLK(NULL, "core_ck", &core_ck, CK_242X), |
| 1731 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X), |
| 1732 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X), |
| 1733 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X), |
| 1734 | CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_242X), |
| 1735 | CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X), |
| 1736 | CLK(NULL, "sys_clkout", &sys_clkout, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1737 | CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X), |
| 1738 | CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X), |
| 1739 | CLK(NULL, "emul_ck", &emul_ck, CK_242X), |
| 1740 | /* mpu domain clocks */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1741 | CLK(NULL, "mpu_ck", &mpu_ck, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1742 | /* dsp domain clocks */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1743 | CLK(NULL, "dsp_fck", &dsp_fck, CK_242X), |
| 1744 | CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1745 | CLK(NULL, "dsp_ick", &dsp_ick, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1746 | CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X), |
| 1747 | CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X), |
| 1748 | /* GFX domain clocks */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1749 | CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_242X), |
| 1750 | CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X), |
| 1751 | CLK(NULL, "gfx_ick", &gfx_ick, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1752 | /* DSS domain clocks */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1753 | CLK("omapdss", "ick", &dss_ick, CK_242X), |
| 1754 | CLK("omapdss", "dss1_fck", &dss1_fck, CK_242X), |
| 1755 | CLK("omapdss", "dss2_fck", &dss2_fck, CK_242X), |
| 1756 | CLK("omapdss", "tv_fck", &dss_54m_fck, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1757 | /* L3 domain clocks */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1758 | CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X), |
| 1759 | CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X), |
| 1760 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1761 | /* L4 domain clocks */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1762 | CLK(NULL, "l4_ck", &l4_ck, CK_242X), |
| 1763 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1764 | /* virtual meta-group clock */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1765 | CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1766 | /* general l4 interface ck, multi-parent functional clk */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1767 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X), |
| 1768 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X), |
| 1769 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X), |
| 1770 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X), |
| 1771 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X), |
| 1772 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X), |
| 1773 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X), |
| 1774 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X), |
| 1775 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X), |
| 1776 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X), |
| 1777 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X), |
| 1778 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X), |
| 1779 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X), |
| 1780 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X), |
| 1781 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X), |
| 1782 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X), |
| 1783 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X), |
| 1784 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X), |
| 1785 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X), |
| 1786 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X), |
| 1787 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X), |
| 1788 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X), |
| 1789 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X), |
| 1790 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X), |
| 1791 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X), |
| 1792 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_242X), |
| 1793 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X), |
| 1794 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_242X), |
| 1795 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X), |
| 1796 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_242X), |
| 1797 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X), |
| 1798 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_242X), |
| 1799 | CLK(NULL, "uart1_ick", &uart1_ick, CK_242X), |
| 1800 | CLK(NULL, "uart1_fck", &uart1_fck, CK_242X), |
| 1801 | CLK(NULL, "uart2_ick", &uart2_ick, CK_242X), |
| 1802 | CLK(NULL, "uart2_fck", &uart2_fck, CK_242X), |
| 1803 | CLK(NULL, "uart3_ick", &uart3_ick, CK_242X), |
| 1804 | CLK(NULL, "uart3_fck", &uart3_fck, CK_242X), |
| 1805 | CLK(NULL, "gpios_ick", &gpios_ick, CK_242X), |
| 1806 | CLK(NULL, "gpios_fck", &gpios_fck, CK_242X), |
| 1807 | CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X), |
| 1808 | CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_242X), |
| 1809 | CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X), |
| 1810 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X), |
| 1811 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X), |
| 1812 | CLK("omap24xxcam", "fck", &cam_fck, CK_242X), |
| 1813 | CLK("omap24xxcam", "ick", &cam_ick, CK_242X), |
| 1814 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X), |
| 1815 | CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X), |
| 1816 | CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1817 | CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X), |
| 1818 | CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X), |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1819 | CLK(NULL, "mspro_ick", &mspro_ick, CK_242X), |
| 1820 | CLK(NULL, "mspro_fck", &mspro_fck, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1821 | CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), |
| 1822 | CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1823 | CLK(NULL, "fac_ick", &fac_ick, CK_242X), |
| 1824 | CLK(NULL, "fac_fck", &fac_fck, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1825 | CLK(NULL, "eac_ick", &eac_ick, CK_242X), |
| 1826 | CLK(NULL, "eac_fck", &eac_fck, CK_242X), |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1827 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X), |
| 1828 | CLK("omap_hdq.1", "fck", &hdq_fck, CK_242X), |
| 1829 | CLK("i2c_omap.1", "ick", &i2c1_ick, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1830 | CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X), |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1831 | CLK("i2c_omap.2", "ick", &i2c2_ick, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1832 | CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X), |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1833 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X), |
| 1834 | CLK(NULL, "sdma_fck", &sdma_fck, CK_242X), |
| 1835 | CLK(NULL, "sdma_ick", &sdma_ick, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1836 | CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), |
| 1837 | CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1838 | CLK(NULL, "des_ick", &des_ick, CK_242X), |
| 1839 | CLK(NULL, "sha_ick", &sha_ick, CK_242X), |
| 1840 | CLK("omap_rng", "ick", &rng_ick, CK_242X), |
| 1841 | CLK(NULL, "aes_ick", &aes_ick, CK_242X), |
| 1842 | CLK(NULL, "pka_ick", &pka_ick, CK_242X), |
| 1843 | CLK(NULL, "usb_fck", &usb_fck, CK_242X), |
Francisco Alecrim | 97b9ad1 | 2010-03-10 18:52:24 -0800 | [diff] [blame] | 1844 | CLK("musb_hdrc", "fck", &osc_ck, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1845 | }; |
| 1846 | |
| 1847 | /* |
| 1848 | * init code |
| 1849 | */ |
| 1850 | |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1851 | int __init omap2420_clk_init(void) |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1852 | { |
| 1853 | const struct prcm_config *prcm; |
| 1854 | struct omap_clk *c; |
| 1855 | u32 clkrate; |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1856 | |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1857 | prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL; |
| 1858 | cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST); |
| 1859 | cpu_mask = RATE_IN_242X; |
| 1860 | rate_table = omap2420_rate_table; |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1861 | |
| 1862 | clk_init(&omap2_clk_functions); |
| 1863 | |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1864 | for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks); |
| 1865 | c++) |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1866 | clk_preinit(c->lk.clk); |
| 1867 | |
| 1868 | osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); |
| 1869 | propagate_rate(&osc_ck); |
Paul Walmsley | 44da0a5 | 2010-01-26 20:13:08 -0700 | [diff] [blame] | 1870 | sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck); |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1871 | propagate_rate(&sys_ck); |
| 1872 | |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1873 | for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks); |
| 1874 | c++) { |
| 1875 | clkdev_add(&c->lk); |
| 1876 | clk_register(c->lk.clk); |
| 1877 | omap2_init_clk_clkdm(c->lk.clk); |
| 1878 | } |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1879 | |
| 1880 | /* Check the MPU rate set by bootloader */ |
| 1881 | clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); |
| 1882 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { |
| 1883 | if (!(prcm->flags & cpu_mask)) |
| 1884 | continue; |
| 1885 | if (prcm->xtal_speed != sys_ck.rate) |
| 1886 | continue; |
| 1887 | if (prcm->dpll_speed <= clkrate) |
| 1888 | break; |
| 1889 | } |
| 1890 | curr_prcm_set = prcm; |
| 1891 | |
| 1892 | recalculate_root_clocks(); |
| 1893 | |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1894 | pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", |
| 1895 | (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, |
| 1896 | (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1897 | |
| 1898 | /* |
| 1899 | * Only enable those clocks we will need, let the drivers |
| 1900 | * enable other clocks as necessary |
| 1901 | */ |
| 1902 | clk_enable_init_clocks(); |
| 1903 | |
| 1904 | /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ |
| 1905 | vclk = clk_get(NULL, "virt_prcm_set"); |
| 1906 | sclk = clk_get(NULL, "sys_ck"); |
| 1907 | dclk = clk_get(NULL, "dpll_ck"); |
| 1908 | |
| 1909 | return 0; |
| 1910 | } |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 1911 | |