Benoît Cousson | 0be1621 | 2010-09-21 10:34:10 -0600 | [diff] [blame] | 1 | /* |
| 2 | * OMAP4 PRM module functions |
| 3 | * |
Benoit Cousson | eaac329 | 2011-07-10 05:56:31 -0600 | [diff] [blame] | 4 | * Copyright (C) 2011 Texas Instruments, Inc. |
Benoît Cousson | 0be1621 | 2010-09-21 10:34:10 -0600 | [diff] [blame] | 5 | * Copyright (C) 2010 Nokia Corporation |
| 6 | * Benoît Cousson |
| 7 | * Paul Walmsley |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/delay.h> |
| 16 | #include <linux/errno.h> |
| 17 | #include <linux/err.h> |
Paul Walmsley | 2ace831 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 18 | #include <linux/io.h> |
Benoît Cousson | 0be1621 | 2010-09-21 10:34:10 -0600 | [diff] [blame] | 19 | |
| 20 | #include <plat/common.h> |
| 21 | #include <plat/cpu.h> |
| 22 | #include <plat/prcm.h> |
| 23 | |
Kevin Hilman | 58aaa59 | 2011-03-28 10:52:04 -0700 | [diff] [blame^] | 24 | #include "vp.h" |
Paul Walmsley | d198b51 | 2010-12-21 15:30:54 -0700 | [diff] [blame] | 25 | #include "prm44xx.h" |
Benoît Cousson | 0be1621 | 2010-09-21 10:34:10 -0600 | [diff] [blame] | 26 | #include "prm-regbits-44xx.h" |
| 27 | |
Paul Walmsley | 2ace831 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 28 | /* PRM low-level functions */ |
| 29 | |
| 30 | /* Read a register in a CM/PRM instance in the PRM module */ |
| 31 | u32 omap4_prm_read_inst_reg(s16 inst, u16 reg) |
| 32 | { |
| 33 | return __raw_readl(OMAP44XX_PRM_REGADDR(inst, reg)); |
| 34 | } |
| 35 | |
| 36 | /* Write into a register in a CM/PRM instance in the PRM module */ |
| 37 | void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg) |
| 38 | { |
| 39 | __raw_writel(val, OMAP44XX_PRM_REGADDR(inst, reg)); |
| 40 | } |
| 41 | |
| 42 | /* Read-modify-write a register in a PRM module. Caller must lock */ |
| 43 | u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg) |
| 44 | { |
| 45 | u32 v; |
| 46 | |
| 47 | v = omap4_prm_read_inst_reg(inst, reg); |
| 48 | v &= ~mask; |
| 49 | v |= bits; |
| 50 | omap4_prm_write_inst_reg(v, inst, reg); |
| 51 | |
| 52 | return v; |
| 53 | } |
Kevin Hilman | 58aaa59 | 2011-03-28 10:52:04 -0700 | [diff] [blame^] | 54 | |
| 55 | /* PRM VP */ |
| 56 | |
| 57 | /* |
| 58 | * struct omap4_vp - OMAP4 VP register access description. |
| 59 | * @irqstatus_mpu: offset to IRQSTATUS_MPU register for VP |
| 60 | * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg |
| 61 | */ |
| 62 | struct omap4_vp { |
| 63 | u32 irqstatus_mpu; |
| 64 | u32 tranxdone_status; |
| 65 | }; |
| 66 | |
| 67 | static struct omap4_vp omap4_vp[] = { |
| 68 | [OMAP4_VP_VDD_MPU_ID] = { |
| 69 | .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET, |
| 70 | .tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK, |
| 71 | }, |
| 72 | [OMAP4_VP_VDD_IVA_ID] = { |
| 73 | .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET, |
| 74 | .tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK, |
| 75 | }, |
| 76 | [OMAP4_VP_VDD_CORE_ID] = { |
| 77 | .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET, |
| 78 | .tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK, |
| 79 | }, |
| 80 | }; |
| 81 | |
| 82 | u32 omap4_prm_vp_check_txdone(u8 vp_id) |
| 83 | { |
| 84 | struct omap4_vp *vp = &omap4_vp[vp_id]; |
| 85 | u32 irqstatus; |
| 86 | |
| 87 | irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, |
| 88 | OMAP4430_PRM_OCP_SOCKET_INST, |
| 89 | vp->irqstatus_mpu); |
| 90 | return irqstatus & vp->tranxdone_status; |
| 91 | } |
| 92 | |
| 93 | void omap4_prm_vp_clear_txdone(u8 vp_id) |
| 94 | { |
| 95 | struct omap4_vp *vp = &omap4_vp[vp_id]; |
| 96 | |
| 97 | omap4_prminst_write_inst_reg(vp->tranxdone_status, |
| 98 | OMAP4430_PRM_PARTITION, |
| 99 | OMAP4430_PRM_OCP_SOCKET_INST, |
| 100 | vp->irqstatus_mpu); |
| 101 | }; |