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gerrit-public.fairphone.software / kernel / msm-4.9 / 58bc67fc32b1c67fb045f4828a67134dc8fee631 / . / include / linux / omap-gpmc.h
blob: 45d9075be1e5009dcac3c1db46c6645ac24a4488 [file] [log] [blame]
Tony Lindgrene639cd52014-11-20 12:11:25 -0800[diff] [blame]1/*
2 * OMAP GPMC (General Purpose Memory Controller) defines
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
Roger Quadros58bc67f2015-07-10 15:23:28 +0300[diff] [blame^]10#include <linux/platform_data/gpmc-omap.h>
Tony Lindgrene639cd52014-11-20 12:11:25 -0800[diff] [blame]11
12#define GPMC_CONFIG_WP 0x00000005
13
14#define GPMC_IRQ_FIFOEVENTENABLE 0x01
15#define GPMC_IRQ_COUNT_EVENT 0x02
16
17#define GPMC_BURST_4 4 /* 4 word burst */
18#define GPMC_BURST_8 8 /* 8 word burst */
19#define GPMC_BURST_16 16 /* 16 word burst */
20#define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */
21#define GPMC_DEVWIDTH_16BIT 2 /* 16-bit device width */
22#define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */
23#define GPMC_MUX_AD 2 /* Addr-Data multiplex */
24
25/* bool type time settings */
26struct gpmc_bool_timings {
27 bool cycle2cyclediffcsen;
28 bool cycle2cyclesamecsen;
29 bool we_extra_delay;
30 bool oe_extra_delay;
31 bool adv_extra_delay;
32 bool cs_extra_delay;
33 bool time_para_granularity;
34};
35
36/*
37 * Note that all values in this struct are in nanoseconds except sync_clk
38 * (which is in picoseconds), while the register values are in gpmc_fck cycles.
39 */
40struct gpmc_timings {
41 /* Minimum clock period for synchronous mode (in picoseconds) */
42 u32 sync_clk;
43
44 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
45 u32 cs_on; /* Assertion time */
46 u32 cs_rd_off; /* Read deassertion time */
47 u32 cs_wr_off; /* Write deassertion time */
48
49 /* ADV signal timings corresponding to GPMC_CONFIG3 */
50 u32 adv_on; /* Assertion time */
51 u32 adv_rd_off; /* Read deassertion time */
52 u32 adv_wr_off; /* Write deassertion time */
Neil Armstrong2c92c042015-12-28 14:39:20 +0100[diff] [blame]53 u32 adv_aad_mux_on; /* ADV assertion time for AAD */
54 u32 adv_aad_mux_rd_off; /* ADV read deassertion time for AAD */
55 u32 adv_aad_mux_wr_off; /* ADV write deassertion time for AAD */
Tony Lindgrene639cd52014-11-20 12:11:25 -0800[diff] [blame]56
57 /* WE signals timings corresponding to GPMC_CONFIG4 */
58 u32 we_on; /* WE assertion time */
59 u32 we_off; /* WE deassertion time */
60
61 /* OE signals timings corresponding to GPMC_CONFIG4 */
62 u32 oe_on; /* OE assertion time */
63 u32 oe_off; /* OE deassertion time */
Neil Armstrong2c92c042015-12-28 14:39:20 +0100[diff] [blame]64 u32 oe_aad_mux_on; /* OE assertion time for AAD */
65 u32 oe_aad_mux_off; /* OE deassertion time for AAD */
Tony Lindgrene639cd52014-11-20 12:11:25 -0800[diff] [blame]66
67 /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
68 u32 page_burst_access; /* Multiple access word delay */
69 u32 access; /* Start-cycle to first data valid delay */
70 u32 rd_cycle; /* Total read cycle time */
71 u32 wr_cycle; /* Total write cycle time */
72
73 u32 bus_turnaround;
74 u32 cycle2cycle_delay;
75
76 u32 wait_monitoring;
77 u32 clk_activation;
78
79 /* The following are only on OMAP3430 */
80 u32 wr_access; /* WRACCESSTIME */
81 u32 wr_data_mux_bus; /* WRDATAONADMUXBUS */
82
83 struct gpmc_bool_timings bool_timings;
84};
85
86/* Device timings in picoseconds */
87struct gpmc_device_timings {
88 u32 t_ceasu; /* address setup to CS valid */
89 u32 t_avdasu; /* address setup to ADV valid */
90 /* XXX: try to combine t_avdp_r & t_avdp_w. Issue is
91 * of tusb using these timings even for sync whilst
92 * ideally for adv_rd/(wr)_off it should have considered
93 * t_avdh instead. This indirectly necessitates r/w
94 * variations of t_avdp as it is possible to have one
95 * sync & other async
96 */
97 u32 t_avdp_r; /* ADV low time (what about t_cer ?) */
98 u32 t_avdp_w;
99 u32 t_aavdh; /* address hold time */
100 u32 t_oeasu; /* address setup to OE valid */
101 u32 t_aa; /* access time from ADV assertion */
102 u32 t_iaa; /* initial access time */
103 u32 t_oe; /* access time from OE assertion */
104 u32 t_ce; /* access time from CS asertion */
105 u32 t_rd_cycle; /* read cycle time */
106 u32 t_cez_r; /* read CS deassertion to high Z */
107 u32 t_cez_w; /* write CS deassertion to high Z */
108 u32 t_oez; /* OE deassertion to high Z */
109 u32 t_weasu; /* address setup to WE valid */
110 u32 t_wpl; /* write assertion time */
111 u32 t_wph; /* write deassertion time */
112 u32 t_wr_cycle; /* write cycle time */
113
114 u32 clk;
115 u32 t_bacc; /* burst access valid clock to output delay */
116 u32 t_ces; /* CS setup time to clk */
117 u32 t_avds; /* ADV setup time to clk */
118 u32 t_avdh; /* ADV hold time from clk */
119 u32 t_ach; /* address hold time from clk */
120 u32 t_rdyo; /* clk to ready valid */
121
122 u32 t_ce_rdyz; /* XXX: description ?, or use t_cez instead */
123 u32 t_ce_avd; /* CS on to ADV on delay */
124
125 /* XXX: check the possibility of combining
126 * cyc_aavhd_oe & cyc_aavdh_we
127 */
128 u8 cyc_aavdh_oe;/* read address hold time in cycles */
129 u8 cyc_aavdh_we;/* write address hold time in cycles */
130 u8 cyc_oe; /* access time from OE assertion in cycles */
131 u8 cyc_wpl; /* write deassertion time in cycles */
132 u32 cyc_iaa; /* initial access time in cycles */
133
134 /* extra delays */
135 bool ce_xdelay;
136 bool avd_xdelay;
137 bool oe_xdelay;
138 bool we_xdelay;
139};
140
141struct gpmc_settings {
142 bool burst_wrap; /* enables wrap bursting */
143 bool burst_read; /* enables read page/burst mode */
144 bool burst_write; /* enables write page/burst mode */
145 bool device_nand; /* device is NAND */
146 bool sync_read; /* enables synchronous reads */
147 bool sync_write; /* enables synchronous writes */
148 bool wait_on_read; /* monitor wait on reads */
149 bool wait_on_write; /* monitor wait on writes */
150 u32 burst_len; /* page/burst length */
151 u32 device_width; /* device bus width (8 or 16 bit) */
152 u32 mux_add_data; /* multiplex address & data */
153 u32 wait_pin; /* wait-pin to be used */
154};
155
156extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
157 struct gpmc_settings *gpmc_s,
158 struct gpmc_device_timings *dev_t);
159
160struct gpmc_nand_regs;
161struct device_node;
162
163extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
164extern int gpmc_get_client_irq(unsigned irq_config);
165
166extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
167
168extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
169extern int gpmc_calc_divider(unsigned int sync_clk);
Robert ABEL2e676902015-02-27 16:56:53 +0100[diff] [blame]170extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
171 const struct gpmc_settings *s);
Tony Lindgrene639cd52014-11-20 12:11:25 -0800[diff] [blame]172extern int gpmc_cs_program_settings(int cs, struct gpmc_settings *p);
173extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
174extern void gpmc_cs_free(int cs);
175extern int gpmc_configure(int cmd, int wval);
176extern void gpmc_read_settings_dt(struct device_node *np,
177 struct gpmc_settings *p);
178
179extern void omap3_gpmc_save_context(void);
180extern void omap3_gpmc_restore_context(void);
181
182struct gpmc_timings;
183struct omap_nand_platform_data;
184struct omap_onenand_platform_data;
185
186#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2)
187extern int gpmc_nand_init(struct omap_nand_platform_data *d,
188 struct gpmc_timings *gpmc_t);
189#else
190static inline int gpmc_nand_init(struct omap_nand_platform_data *d,
191 struct gpmc_timings *gpmc_t)
192{
193 return 0;
194}
195#endif
196
197#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
198extern void gpmc_onenand_init(struct omap_onenand_platform_data *d);
199#else
200#define board_onenand_data NULL
201static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d)
202{
203}
204#endif