Jesper Nilsson | 58d0831 | 2007-11-29 17:21:59 +0100 | [diff] [blame^] | 1 | #ifndef __iop_sw_spu_defs_asm_h |
| 2 | #define __iop_sw_spu_defs_asm_h |
| 3 | |
| 4 | /* |
| 5 | * This file is autogenerated from |
| 6 | * file: iop_sw_spu.r |
| 7 | * |
| 8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_spu_defs_asm.h iop_sw_spu.r |
| 9 | * Any changes here will be lost. |
| 10 | * |
| 11 | * -*- buffer-read-only: t -*- |
| 12 | */ |
| 13 | |
| 14 | #ifndef REG_FIELD |
| 15 | #define REG_FIELD( scope, reg, field, value ) \ |
| 16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) |
| 17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) |
| 18 | #endif |
| 19 | |
| 20 | #ifndef REG_STATE |
| 21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ |
| 22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) |
| 23 | #define REG_STATE_X_( k, shift ) (k << shift) |
| 24 | #endif |
| 25 | |
| 26 | #ifndef REG_MASK |
| 27 | #define REG_MASK( scope, reg, field ) \ |
| 28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) |
| 29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) |
| 30 | #endif |
| 31 | |
| 32 | #ifndef REG_LSB |
| 33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb |
| 34 | #endif |
| 35 | |
| 36 | #ifndef REG_BIT |
| 37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit |
| 38 | #endif |
| 39 | |
| 40 | #ifndef REG_ADDR |
| 41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) |
| 42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) |
| 43 | #endif |
| 44 | |
| 45 | #ifndef REG_ADDR_VECT |
| 46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ |
| 47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ |
| 48 | STRIDE_##scope##_##reg ) |
| 49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ |
| 50 | ((inst) + offs + (index) * stride) |
| 51 | #endif |
| 52 | |
| 53 | /* Register r_mpu_trace, scope iop_sw_spu, type r */ |
| 54 | #define reg_iop_sw_spu_r_mpu_trace_offset 0 |
| 55 | |
| 56 | /* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ |
| 57 | #define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0 |
| 58 | #define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1 |
| 59 | #define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0 |
| 60 | #define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1 |
| 61 | #define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2 |
| 62 | #define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3 |
| 63 | #define reg_iop_sw_spu_rw_mc_ctrl___size___width 3 |
| 64 | #define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___lsb 6 |
| 65 | #define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___width 1 |
| 66 | #define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___bit 6 |
| 67 | #define reg_iop_sw_spu_rw_mc_ctrl_offset 4 |
| 68 | |
| 69 | /* Register rw_mc_data, scope iop_sw_spu, type rw */ |
| 70 | #define reg_iop_sw_spu_rw_mc_data___val___lsb 0 |
| 71 | #define reg_iop_sw_spu_rw_mc_data___val___width 32 |
| 72 | #define reg_iop_sw_spu_rw_mc_data_offset 8 |
| 73 | |
| 74 | /* Register rw_mc_addr, scope iop_sw_spu, type rw */ |
| 75 | #define reg_iop_sw_spu_rw_mc_addr_offset 12 |
| 76 | |
| 77 | /* Register rs_mc_data, scope iop_sw_spu, type rs */ |
| 78 | #define reg_iop_sw_spu_rs_mc_data_offset 16 |
| 79 | |
| 80 | /* Register r_mc_data, scope iop_sw_spu, type r */ |
| 81 | #define reg_iop_sw_spu_r_mc_data_offset 20 |
| 82 | |
| 83 | /* Register r_mc_stat, scope iop_sw_spu, type r */ |
| 84 | #define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0 |
| 85 | #define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1 |
| 86 | #define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0 |
| 87 | #define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1 |
| 88 | #define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1 |
| 89 | #define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1 |
| 90 | #define reg_iop_sw_spu_r_mc_stat___busy_spu___lsb 2 |
| 91 | #define reg_iop_sw_spu_r_mc_stat___busy_spu___width 1 |
| 92 | #define reg_iop_sw_spu_r_mc_stat___busy_spu___bit 2 |
| 93 | #define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 3 |
| 94 | #define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1 |
| 95 | #define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 3 |
| 96 | #define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 4 |
| 97 | #define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1 |
| 98 | #define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 4 |
| 99 | #define reg_iop_sw_spu_r_mc_stat___owned_by_spu___lsb 5 |
| 100 | #define reg_iop_sw_spu_r_mc_stat___owned_by_spu___width 1 |
| 101 | #define reg_iop_sw_spu_r_mc_stat___owned_by_spu___bit 5 |
| 102 | #define reg_iop_sw_spu_r_mc_stat_offset 24 |
| 103 | |
| 104 | /* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */ |
| 105 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte0___lsb 0 |
| 106 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte0___width 8 |
| 107 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte1___lsb 8 |
| 108 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte1___width 8 |
| 109 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte2___lsb 16 |
| 110 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte2___width 8 |
| 111 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte3___lsb 24 |
| 112 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte3___width 8 |
| 113 | #define reg_iop_sw_spu_rw_bus_clr_mask_offset 28 |
| 114 | |
| 115 | /* Register rw_bus_set_mask, scope iop_sw_spu, type rw */ |
| 116 | #define reg_iop_sw_spu_rw_bus_set_mask___byte0___lsb 0 |
| 117 | #define reg_iop_sw_spu_rw_bus_set_mask___byte0___width 8 |
| 118 | #define reg_iop_sw_spu_rw_bus_set_mask___byte1___lsb 8 |
| 119 | #define reg_iop_sw_spu_rw_bus_set_mask___byte1___width 8 |
| 120 | #define reg_iop_sw_spu_rw_bus_set_mask___byte2___lsb 16 |
| 121 | #define reg_iop_sw_spu_rw_bus_set_mask___byte2___width 8 |
| 122 | #define reg_iop_sw_spu_rw_bus_set_mask___byte3___lsb 24 |
| 123 | #define reg_iop_sw_spu_rw_bus_set_mask___byte3___width 8 |
| 124 | #define reg_iop_sw_spu_rw_bus_set_mask_offset 32 |
| 125 | |
| 126 | /* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */ |
| 127 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___lsb 0 |
| 128 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___width 1 |
| 129 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___bit 0 |
| 130 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___lsb 1 |
| 131 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___width 1 |
| 132 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___bit 1 |
| 133 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___lsb 2 |
| 134 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___width 1 |
| 135 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___bit 2 |
| 136 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___lsb 3 |
| 137 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___width 1 |
| 138 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___bit 3 |
| 139 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask_offset 36 |
| 140 | |
| 141 | /* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */ |
| 142 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___lsb 0 |
| 143 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___width 1 |
| 144 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___bit 0 |
| 145 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___lsb 1 |
| 146 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___width 1 |
| 147 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___bit 1 |
| 148 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___lsb 2 |
| 149 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___width 1 |
| 150 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___bit 2 |
| 151 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___lsb 3 |
| 152 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___width 1 |
| 153 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___bit 3 |
| 154 | #define reg_iop_sw_spu_rw_bus_oe_set_mask_offset 40 |
| 155 | |
| 156 | /* Register r_bus_in, scope iop_sw_spu, type r */ |
| 157 | #define reg_iop_sw_spu_r_bus_in_offset 44 |
| 158 | |
| 159 | /* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ |
| 160 | #define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0 |
| 161 | #define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32 |
| 162 | #define reg_iop_sw_spu_rw_gio_clr_mask_offset 48 |
| 163 | |
| 164 | /* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ |
| 165 | #define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0 |
| 166 | #define reg_iop_sw_spu_rw_gio_set_mask___val___width 32 |
| 167 | #define reg_iop_sw_spu_rw_gio_set_mask_offset 52 |
| 168 | |
| 169 | /* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ |
| 170 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0 |
| 171 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32 |
| 172 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 56 |
| 173 | |
| 174 | /* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ |
| 175 | #define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0 |
| 176 | #define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32 |
| 177 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 60 |
| 178 | |
| 179 | /* Register r_gio_in, scope iop_sw_spu, type r */ |
| 180 | #define reg_iop_sw_spu_r_gio_in_offset 64 |
| 181 | |
| 182 | /* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */ |
| 183 | #define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___lsb 0 |
| 184 | #define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___width 8 |
| 185 | #define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___lsb 8 |
| 186 | #define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___width 8 |
| 187 | #define reg_iop_sw_spu_rw_bus_clr_mask_lo_offset 68 |
| 188 | |
| 189 | /* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */ |
| 190 | #define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___lsb 0 |
| 191 | #define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___width 8 |
| 192 | #define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___lsb 8 |
| 193 | #define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___width 8 |
| 194 | #define reg_iop_sw_spu_rw_bus_clr_mask_hi_offset 72 |
| 195 | |
| 196 | /* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */ |
| 197 | #define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___lsb 0 |
| 198 | #define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___width 8 |
| 199 | #define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___lsb 8 |
| 200 | #define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___width 8 |
| 201 | #define reg_iop_sw_spu_rw_bus_set_mask_lo_offset 76 |
| 202 | |
| 203 | /* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */ |
| 204 | #define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___lsb 0 |
| 205 | #define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___width 8 |
| 206 | #define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___lsb 8 |
| 207 | #define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___width 8 |
| 208 | #define reg_iop_sw_spu_rw_bus_set_mask_hi_offset 80 |
| 209 | |
| 210 | /* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ |
| 211 | #define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0 |
| 212 | #define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16 |
| 213 | #define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 84 |
| 214 | |
| 215 | /* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ |
| 216 | #define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0 |
| 217 | #define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16 |
| 218 | #define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 88 |
| 219 | |
| 220 | /* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ |
| 221 | #define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0 |
| 222 | #define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16 |
| 223 | #define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 92 |
| 224 | |
| 225 | /* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ |
| 226 | #define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0 |
| 227 | #define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16 |
| 228 | #define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 96 |
| 229 | |
| 230 | /* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ |
| 231 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0 |
| 232 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16 |
| 233 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 100 |
| 234 | |
| 235 | /* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ |
| 236 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0 |
| 237 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16 |
| 238 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 104 |
| 239 | |
| 240 | /* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ |
| 241 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0 |
| 242 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16 |
| 243 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 108 |
| 244 | |
| 245 | /* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ |
| 246 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0 |
| 247 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16 |
| 248 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 112 |
| 249 | |
| 250 | /* Register rw_cpu_intr, scope iop_sw_spu, type rw */ |
| 251 | #define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0 |
| 252 | #define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1 |
| 253 | #define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0 |
| 254 | #define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1 |
| 255 | #define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1 |
| 256 | #define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1 |
| 257 | #define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2 |
| 258 | #define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1 |
| 259 | #define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2 |
| 260 | #define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3 |
| 261 | #define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1 |
| 262 | #define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3 |
| 263 | #define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4 |
| 264 | #define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1 |
| 265 | #define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4 |
| 266 | #define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5 |
| 267 | #define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1 |
| 268 | #define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5 |
| 269 | #define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6 |
| 270 | #define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1 |
| 271 | #define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6 |
| 272 | #define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7 |
| 273 | #define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1 |
| 274 | #define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7 |
| 275 | #define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8 |
| 276 | #define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1 |
| 277 | #define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8 |
| 278 | #define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9 |
| 279 | #define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1 |
| 280 | #define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9 |
| 281 | #define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10 |
| 282 | #define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1 |
| 283 | #define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10 |
| 284 | #define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11 |
| 285 | #define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1 |
| 286 | #define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11 |
| 287 | #define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12 |
| 288 | #define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1 |
| 289 | #define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12 |
| 290 | #define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13 |
| 291 | #define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1 |
| 292 | #define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13 |
| 293 | #define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14 |
| 294 | #define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1 |
| 295 | #define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14 |
| 296 | #define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15 |
| 297 | #define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1 |
| 298 | #define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15 |
| 299 | #define reg_iop_sw_spu_rw_cpu_intr_offset 116 |
| 300 | |
| 301 | /* Register r_cpu_intr, scope iop_sw_spu, type r */ |
| 302 | #define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0 |
| 303 | #define reg_iop_sw_spu_r_cpu_intr___intr0___width 1 |
| 304 | #define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0 |
| 305 | #define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1 |
| 306 | #define reg_iop_sw_spu_r_cpu_intr___intr1___width 1 |
| 307 | #define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1 |
| 308 | #define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2 |
| 309 | #define reg_iop_sw_spu_r_cpu_intr___intr2___width 1 |
| 310 | #define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2 |
| 311 | #define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3 |
| 312 | #define reg_iop_sw_spu_r_cpu_intr___intr3___width 1 |
| 313 | #define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3 |
| 314 | #define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4 |
| 315 | #define reg_iop_sw_spu_r_cpu_intr___intr4___width 1 |
| 316 | #define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4 |
| 317 | #define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5 |
| 318 | #define reg_iop_sw_spu_r_cpu_intr___intr5___width 1 |
| 319 | #define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5 |
| 320 | #define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6 |
| 321 | #define reg_iop_sw_spu_r_cpu_intr___intr6___width 1 |
| 322 | #define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6 |
| 323 | #define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7 |
| 324 | #define reg_iop_sw_spu_r_cpu_intr___intr7___width 1 |
| 325 | #define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7 |
| 326 | #define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8 |
| 327 | #define reg_iop_sw_spu_r_cpu_intr___intr8___width 1 |
| 328 | #define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8 |
| 329 | #define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9 |
| 330 | #define reg_iop_sw_spu_r_cpu_intr___intr9___width 1 |
| 331 | #define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9 |
| 332 | #define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10 |
| 333 | #define reg_iop_sw_spu_r_cpu_intr___intr10___width 1 |
| 334 | #define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10 |
| 335 | #define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11 |
| 336 | #define reg_iop_sw_spu_r_cpu_intr___intr11___width 1 |
| 337 | #define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11 |
| 338 | #define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12 |
| 339 | #define reg_iop_sw_spu_r_cpu_intr___intr12___width 1 |
| 340 | #define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12 |
| 341 | #define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13 |
| 342 | #define reg_iop_sw_spu_r_cpu_intr___intr13___width 1 |
| 343 | #define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13 |
| 344 | #define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14 |
| 345 | #define reg_iop_sw_spu_r_cpu_intr___intr14___width 1 |
| 346 | #define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14 |
| 347 | #define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15 |
| 348 | #define reg_iop_sw_spu_r_cpu_intr___intr15___width 1 |
| 349 | #define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15 |
| 350 | #define reg_iop_sw_spu_r_cpu_intr_offset 120 |
| 351 | |
| 352 | /* Register r_hw_intr, scope iop_sw_spu, type r */ |
| 353 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0 |
| 354 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1 |
| 355 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0 |
| 356 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1 |
| 357 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1 |
| 358 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1 |
| 359 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2 |
| 360 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1 |
| 361 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2 |
| 362 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3 |
| 363 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1 |
| 364 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3 |
| 365 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4 |
| 366 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1 |
| 367 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4 |
| 368 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5 |
| 369 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1 |
| 370 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5 |
| 371 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6 |
| 372 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1 |
| 373 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6 |
| 374 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7 |
| 375 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1 |
| 376 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7 |
| 377 | #define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8 |
| 378 | #define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1 |
| 379 | #define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8 |
| 380 | #define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9 |
| 381 | #define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1 |
| 382 | #define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9 |
| 383 | #define reg_iop_sw_spu_r_hw_intr___fifo_out___lsb 10 |
| 384 | #define reg_iop_sw_spu_r_hw_intr___fifo_out___width 1 |
| 385 | #define reg_iop_sw_spu_r_hw_intr___fifo_out___bit 10 |
| 386 | #define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___lsb 11 |
| 387 | #define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___width 1 |
| 388 | #define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___bit 11 |
| 389 | #define reg_iop_sw_spu_r_hw_intr___fifo_in___lsb 12 |
| 390 | #define reg_iop_sw_spu_r_hw_intr___fifo_in___width 1 |
| 391 | #define reg_iop_sw_spu_r_hw_intr___fifo_in___bit 12 |
| 392 | #define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___lsb 13 |
| 393 | #define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___width 1 |
| 394 | #define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___bit 13 |
| 395 | #define reg_iop_sw_spu_r_hw_intr___dmc_out___lsb 14 |
| 396 | #define reg_iop_sw_spu_r_hw_intr___dmc_out___width 1 |
| 397 | #define reg_iop_sw_spu_r_hw_intr___dmc_out___bit 14 |
| 398 | #define reg_iop_sw_spu_r_hw_intr___dmc_in___lsb 15 |
| 399 | #define reg_iop_sw_spu_r_hw_intr___dmc_in___width 1 |
| 400 | #define reg_iop_sw_spu_r_hw_intr___dmc_in___bit 15 |
| 401 | #define reg_iop_sw_spu_r_hw_intr_offset 124 |
| 402 | |
| 403 | /* Register rw_mpu_intr, scope iop_sw_spu, type rw */ |
| 404 | #define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0 |
| 405 | #define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1 |
| 406 | #define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0 |
| 407 | #define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1 |
| 408 | #define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1 |
| 409 | #define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1 |
| 410 | #define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2 |
| 411 | #define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1 |
| 412 | #define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2 |
| 413 | #define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3 |
| 414 | #define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1 |
| 415 | #define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3 |
| 416 | #define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4 |
| 417 | #define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1 |
| 418 | #define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4 |
| 419 | #define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5 |
| 420 | #define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1 |
| 421 | #define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5 |
| 422 | #define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6 |
| 423 | #define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1 |
| 424 | #define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6 |
| 425 | #define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7 |
| 426 | #define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1 |
| 427 | #define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7 |
| 428 | #define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8 |
| 429 | #define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1 |
| 430 | #define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8 |
| 431 | #define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9 |
| 432 | #define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1 |
| 433 | #define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9 |
| 434 | #define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10 |
| 435 | #define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1 |
| 436 | #define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10 |
| 437 | #define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11 |
| 438 | #define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1 |
| 439 | #define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11 |
| 440 | #define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12 |
| 441 | #define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1 |
| 442 | #define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12 |
| 443 | #define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13 |
| 444 | #define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1 |
| 445 | #define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13 |
| 446 | #define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14 |
| 447 | #define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1 |
| 448 | #define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14 |
| 449 | #define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15 |
| 450 | #define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1 |
| 451 | #define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15 |
| 452 | #define reg_iop_sw_spu_rw_mpu_intr_offset 128 |
| 453 | |
| 454 | /* Register r_mpu_intr, scope iop_sw_spu, type r */ |
| 455 | #define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0 |
| 456 | #define reg_iop_sw_spu_r_mpu_intr___intr0___width 1 |
| 457 | #define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0 |
| 458 | #define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1 |
| 459 | #define reg_iop_sw_spu_r_mpu_intr___intr1___width 1 |
| 460 | #define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1 |
| 461 | #define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2 |
| 462 | #define reg_iop_sw_spu_r_mpu_intr___intr2___width 1 |
| 463 | #define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2 |
| 464 | #define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3 |
| 465 | #define reg_iop_sw_spu_r_mpu_intr___intr3___width 1 |
| 466 | #define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3 |
| 467 | #define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4 |
| 468 | #define reg_iop_sw_spu_r_mpu_intr___intr4___width 1 |
| 469 | #define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4 |
| 470 | #define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5 |
| 471 | #define reg_iop_sw_spu_r_mpu_intr___intr5___width 1 |
| 472 | #define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5 |
| 473 | #define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6 |
| 474 | #define reg_iop_sw_spu_r_mpu_intr___intr6___width 1 |
| 475 | #define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6 |
| 476 | #define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7 |
| 477 | #define reg_iop_sw_spu_r_mpu_intr___intr7___width 1 |
| 478 | #define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7 |
| 479 | #define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8 |
| 480 | #define reg_iop_sw_spu_r_mpu_intr___intr8___width 1 |
| 481 | #define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8 |
| 482 | #define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9 |
| 483 | #define reg_iop_sw_spu_r_mpu_intr___intr9___width 1 |
| 484 | #define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9 |
| 485 | #define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10 |
| 486 | #define reg_iop_sw_spu_r_mpu_intr___intr10___width 1 |
| 487 | #define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10 |
| 488 | #define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11 |
| 489 | #define reg_iop_sw_spu_r_mpu_intr___intr11___width 1 |
| 490 | #define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11 |
| 491 | #define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12 |
| 492 | #define reg_iop_sw_spu_r_mpu_intr___intr12___width 1 |
| 493 | #define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12 |
| 494 | #define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13 |
| 495 | #define reg_iop_sw_spu_r_mpu_intr___intr13___width 1 |
| 496 | #define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13 |
| 497 | #define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14 |
| 498 | #define reg_iop_sw_spu_r_mpu_intr___intr14___width 1 |
| 499 | #define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14 |
| 500 | #define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15 |
| 501 | #define reg_iop_sw_spu_r_mpu_intr___intr15___width 1 |
| 502 | #define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15 |
| 503 | #define reg_iop_sw_spu_r_mpu_intr_offset 132 |
| 504 | |
| 505 | |
| 506 | /* Constants */ |
| 507 | #define regk_iop_sw_spu_copy 0x00000000 |
| 508 | #define regk_iop_sw_spu_no 0x00000000 |
| 509 | #define regk_iop_sw_spu_nop 0x00000000 |
| 510 | #define regk_iop_sw_spu_rd 0x00000002 |
| 511 | #define regk_iop_sw_spu_reg_copy 0x00000001 |
| 512 | #define regk_iop_sw_spu_rw_bus_clr_mask_default 0x00000000 |
| 513 | #define regk_iop_sw_spu_rw_bus_oe_clr_mask_default 0x00000000 |
| 514 | #define regk_iop_sw_spu_rw_bus_oe_set_mask_default 0x00000000 |
| 515 | #define regk_iop_sw_spu_rw_bus_set_mask_default 0x00000000 |
| 516 | #define regk_iop_sw_spu_rw_gio_clr_mask_default 0x00000000 |
| 517 | #define regk_iop_sw_spu_rw_gio_oe_clr_mask_default 0x00000000 |
| 518 | #define regk_iop_sw_spu_rw_gio_oe_set_mask_default 0x00000000 |
| 519 | #define regk_iop_sw_spu_rw_gio_set_mask_default 0x00000000 |
| 520 | #define regk_iop_sw_spu_set 0x00000001 |
| 521 | #define regk_iop_sw_spu_wr 0x00000003 |
| 522 | #define regk_iop_sw_spu_yes 0x00000001 |
| 523 | #endif /* __iop_sw_spu_defs_asm_h */ |