Clarence Ip | 8e8f355 | 2016-05-30 11:42:25 -0400 | [diff] [blame] | 1 | #ifndef _SDE_DRM_H_ |
| 2 | #define _SDE_DRM_H_ |
| 3 | |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 4 | #include "drm.h" |
| 5 | |
Clarence Ip | 8e8f355 | 2016-05-30 11:42:25 -0400 | [diff] [blame] | 6 | /* Total number of supported color planes */ |
| 7 | #define SDE_MAX_PLANES 4 |
| 8 | |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 9 | /* Total number of parameterized detail enhancer mapping curves */ |
| 10 | #define SDE_MAX_DE_CURVES 3 |
abeykun | 4106012 | 2016-11-28 13:02:01 -0500 | [diff] [blame] | 11 | |
| 12 | /* Y/RGB and UV filter configuration */ |
| 13 | #define FILTER_EDGE_DIRECTED_2D 0x0 |
| 14 | #define FILTER_CIRCULAR_2D 0x1 |
| 15 | #define FILTER_SEPARABLE_1D 0x2 |
| 16 | #define FILTER_BILINEAR 0x3 |
| 17 | |
| 18 | /* Alpha filters */ |
| 19 | #define FILTER_ALPHA_DROP_REPEAT 0x0 |
| 20 | #define FILTER_ALPHA_BILINEAR 0x1 |
| 21 | #define FILTER_ALPHA_2D 0x3 |
| 22 | |
| 23 | /* Blend filters */ |
| 24 | #define FILTER_BLEND_CIRCULAR_2D 0x0 |
| 25 | #define FILTER_BLEND_SEPARABLE_1D 0x1 |
| 26 | |
| 27 | /* LUT configuration flags */ |
| 28 | #define SCALER_LUT_SWAP 0x1 |
| 29 | #define SCALER_LUT_DIR_WR 0x2 |
| 30 | #define SCALER_LUT_Y_CIR_WR 0x4 |
| 31 | #define SCALER_LUT_UV_CIR_WR 0x8 |
| 32 | #define SCALER_LUT_Y_SEP_WR 0x10 |
| 33 | #define SCALER_LUT_UV_SEP_WR 0x20 |
| 34 | |
Clarence Ip | 8e8f355 | 2016-05-30 11:42:25 -0400 | [diff] [blame] | 35 | /** |
| 36 | * Blend operations for "blend_op" property |
| 37 | * |
| 38 | * @SDE_DRM_BLEND_OP_NOT_DEFINED: No blend operation defined for the layer. |
| 39 | * @SDE_DRM_BLEND_OP_OPAQUE: Apply a constant blend operation. The layer |
| 40 | * would appear opaque in case fg plane alpha |
| 41 | * is 0xff. |
| 42 | * @SDE_DRM_BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already |
| 43 | * has alpha pre-multiplication done. If the fg |
| 44 | * plane alpha is less than 0xff, apply |
| 45 | * modulation as well. This operation is |
| 46 | * intended on layers having alpha channel. |
| 47 | * @SDE_DRM_BLEND_OP_COVERAGE: Apply source over blend rule. Layer is not |
| 48 | * alpha pre-multiplied. Apply |
| 49 | * pre-multiplication. If fg plane alpha is |
| 50 | * less than 0xff, apply modulation as well. |
| 51 | * @SDE_DRM_BLEND_OP_MAX: Used to track maximum blend operation |
| 52 | * possible by mdp. |
| 53 | */ |
| 54 | #define SDE_DRM_BLEND_OP_NOT_DEFINED 0 |
| 55 | #define SDE_DRM_BLEND_OP_OPAQUE 1 |
| 56 | #define SDE_DRM_BLEND_OP_PREMULTIPLIED 2 |
| 57 | #define SDE_DRM_BLEND_OP_COVERAGE 3 |
| 58 | #define SDE_DRM_BLEND_OP_MAX 4 |
| 59 | |
| 60 | /** |
| 61 | * Bit masks for "src_config" property |
| 62 | * construct bitmask via (1UL << SDE_DRM_<flag>) |
| 63 | */ |
| 64 | #define SDE_DRM_DEINTERLACE 0 /* Specifies interlaced input */ |
| 65 | |
| 66 | /* DRM bitmasks are restricted to 0..63 */ |
| 67 | #define SDE_DRM_BITMASK_COUNT 64 |
| 68 | |
| 69 | /** |
| 70 | * struct sde_drm_pix_ext_v1 - version 1 of pixel ext structure |
abeykun | 4106012 | 2016-11-28 13:02:01 -0500 | [diff] [blame] | 71 | * @num_ext_pxls_lr: Number of total horizontal pixels |
| 72 | * @num_ext_pxls_tb: Number of total vertical lines |
| 73 | * @left_ftch: Number of extra pixels to overfetch from left |
| 74 | * @right_ftch: Number of extra pixels to overfetch from right |
| 75 | * @top_ftch: Number of extra lines to overfetch from top |
| 76 | * @btm_ftch: Number of extra lines to overfetch from bottom |
| 77 | * @left_rpt: Number of extra pixels to repeat from left |
| 78 | * @right_rpt: Number of extra pixels to repeat from right |
| 79 | * @top_rpt: Number of extra lines to repeat from top |
| 80 | * @btm_rpt: Number of extra lines to repeat from bottom |
Clarence Ip | 8e8f355 | 2016-05-30 11:42:25 -0400 | [diff] [blame] | 81 | */ |
| 82 | struct sde_drm_pix_ext_v1 { |
| 83 | /* |
| 84 | * Number of pixels ext in left, right, top and bottom direction |
abeykun | 4106012 | 2016-11-28 13:02:01 -0500 | [diff] [blame] | 85 | * for all color components. |
Clarence Ip | 8e8f355 | 2016-05-30 11:42:25 -0400 | [diff] [blame] | 86 | */ |
abeykun | 4106012 | 2016-11-28 13:02:01 -0500 | [diff] [blame] | 87 | int32_t num_ext_pxls_lr[SDE_MAX_PLANES]; |
| 88 | int32_t num_ext_pxls_tb[SDE_MAX_PLANES]; |
Clarence Ip | 8e8f355 | 2016-05-30 11:42:25 -0400 | [diff] [blame] | 89 | |
| 90 | /* |
| 91 | * Number of pixels needs to be overfetched in left, right, top |
| 92 | * and bottom directions from source image for scaling. |
| 93 | */ |
abeykun | 4106012 | 2016-11-28 13:02:01 -0500 | [diff] [blame] | 94 | int32_t left_ftch[SDE_MAX_PLANES]; |
| 95 | int32_t right_ftch[SDE_MAX_PLANES]; |
| 96 | int32_t top_ftch[SDE_MAX_PLANES]; |
| 97 | int32_t btm_ftch[SDE_MAX_PLANES]; |
Clarence Ip | 8e8f355 | 2016-05-30 11:42:25 -0400 | [diff] [blame] | 98 | /* |
| 99 | * Number of pixels needs to be repeated in left, right, top and |
| 100 | * bottom directions for scaling. |
| 101 | */ |
abeykun | 4106012 | 2016-11-28 13:02:01 -0500 | [diff] [blame] | 102 | int32_t left_rpt[SDE_MAX_PLANES]; |
| 103 | int32_t right_rpt[SDE_MAX_PLANES]; |
| 104 | int32_t top_rpt[SDE_MAX_PLANES]; |
| 105 | int32_t btm_rpt[SDE_MAX_PLANES]; |
Clarence Ip | 8e8f355 | 2016-05-30 11:42:25 -0400 | [diff] [blame] | 106 | |
Clarence Ip | 8e8f355 | 2016-05-30 11:42:25 -0400 | [diff] [blame] | 107 | }; |
| 108 | |
| 109 | /** |
Clarence Ip | 8e8f355 | 2016-05-30 11:42:25 -0400 | [diff] [blame] | 110 | * struct sde_drm_scaler_v1 - version 1 of struct sde_drm_scaler |
Clarence Ip | 8e8f355 | 2016-05-30 11:42:25 -0400 | [diff] [blame] | 111 | * @lr: Pixel extension settings for left/right |
| 112 | * @tb: Pixel extension settings for top/botton |
Clarence Ip | 8e8f355 | 2016-05-30 11:42:25 -0400 | [diff] [blame] | 113 | * @init_phase_x: Initial scaler phase values for x |
| 114 | * @phase_step_x: Phase step values for x |
| 115 | * @init_phase_y: Initial scaler phase values for y |
| 116 | * @phase_step_y: Phase step values for y |
| 117 | * @horz_filter: Horizontal filter array |
| 118 | * @vert_filter: Vertical filter array |
| 119 | */ |
| 120 | struct sde_drm_scaler_v1 { |
| 121 | /* |
Clarence Ip | 8e8f355 | 2016-05-30 11:42:25 -0400 | [diff] [blame] | 122 | * Pix ext settings |
| 123 | */ |
abeykun | 4106012 | 2016-11-28 13:02:01 -0500 | [diff] [blame] | 124 | struct sde_drm_pix_ext_v1 pe; |
Clarence Ip | 8e8f355 | 2016-05-30 11:42:25 -0400 | [diff] [blame] | 125 | /* |
Clarence Ip | 8e8f355 | 2016-05-30 11:42:25 -0400 | [diff] [blame] | 126 | * Phase settings |
| 127 | */ |
| 128 | int32_t init_phase_x[SDE_MAX_PLANES]; |
| 129 | int32_t phase_step_x[SDE_MAX_PLANES]; |
| 130 | int32_t init_phase_y[SDE_MAX_PLANES]; |
| 131 | int32_t phase_step_y[SDE_MAX_PLANES]; |
| 132 | |
| 133 | /* |
| 134 | * Filter type to be used for scaling in horizontal and vertical |
| 135 | * directions |
| 136 | */ |
| 137 | uint32_t horz_filter[SDE_MAX_PLANES]; |
| 138 | uint32_t vert_filter[SDE_MAX_PLANES]; |
| 139 | }; |
| 140 | |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 141 | /** |
| 142 | * struct sde_drm_de_v1 - version 1 of detail enhancer structure |
| 143 | * @enable: Enables/disables detail enhancer |
| 144 | * @sharpen_level1: Sharpening strength for noise |
| 145 | * @sharpen_level2: Sharpening strength for context |
| 146 | * @clip: Clip coefficient |
| 147 | * @limit: Detail enhancer limit factor |
| 148 | * @thr_quiet: Quite zone threshold |
| 149 | * @thr_dieout: Die-out zone threshold |
| 150 | * @thr_low: Linear zone left threshold |
| 151 | * @thr_high: Linear zone right threshold |
| 152 | * @prec_shift: Detail enhancer precision |
| 153 | * @adjust_a: Mapping curves A coefficients |
| 154 | * @adjust_b: Mapping curves B coefficients |
| 155 | * @adjust_c: Mapping curves C coefficients |
| 156 | */ |
| 157 | struct sde_drm_de_v1 { |
| 158 | uint32_t enable; |
| 159 | int16_t sharpen_level1; |
| 160 | int16_t sharpen_level2; |
| 161 | uint16_t clip; |
| 162 | uint16_t limit; |
| 163 | uint16_t thr_quiet; |
| 164 | uint16_t thr_dieout; |
| 165 | uint16_t thr_low; |
| 166 | uint16_t thr_high; |
| 167 | uint16_t prec_shift; |
| 168 | int16_t adjust_a[SDE_MAX_DE_CURVES]; |
| 169 | int16_t adjust_b[SDE_MAX_DE_CURVES]; |
| 170 | int16_t adjust_c[SDE_MAX_DE_CURVES]; |
| 171 | }; |
| 172 | |
| 173 | /** |
| 174 | * struct sde_drm_scaler_v2 - version 2 of struct sde_drm_scaler |
abeykun | 4106012 | 2016-11-28 13:02:01 -0500 | [diff] [blame] | 175 | * @enable: Scaler enable |
| 176 | * @dir_en: Detail enhancer enable |
| 177 | * @pe: Pixel extension settings |
| 178 | * @horz_decimate: Horizontal decimation factor |
| 179 | * @vert_decimate: Vertical decimation factor |
| 180 | * @init_phase_x: Initial scaler phase values for x |
| 181 | * @phase_step_x: Phase step values for x |
| 182 | * @init_phase_y: Initial scaler phase values for y |
| 183 | * @phase_step_y: Phase step values for y |
| 184 | * @preload_x: Horizontal preload value |
| 185 | * @preload_y: Vertical preload value |
| 186 | * @src_width: Source width |
| 187 | * @src_height: Source height |
| 188 | * @dst_width: Destination width |
| 189 | * @dst_height: Destination height |
| 190 | * @y_rgb_filter_cfg: Y/RGB plane filter configuration |
| 191 | * @uv_filter_cfg: UV plane filter configuration |
| 192 | * @alpha_filter_cfg: Alpha filter configuration |
| 193 | * @blend_cfg: Selection of blend coefficients |
| 194 | * @lut_flag: LUT configuration flags |
| 195 | * @dir_lut_idx: 2d 4x4 LUT index |
| 196 | * @y_rgb_cir_lut_idx: Y/RGB circular LUT index |
| 197 | * @uv_cir_lut_idx: UV circular LUT index |
| 198 | * @y_rgb_sep_lut_idx: Y/RGB separable LUT index |
| 199 | * @uv_sep_lut_idx: UV separable LUT index |
| 200 | * @de: Detail enhancer settings |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 201 | */ |
| 202 | struct sde_drm_scaler_v2 { |
| 203 | /* |
| 204 | * General definitions |
| 205 | */ |
| 206 | uint32_t enable; |
| 207 | uint32_t dir_en; |
| 208 | |
| 209 | /* |
| 210 | * Pix ext settings |
| 211 | */ |
abeykun | 4106012 | 2016-11-28 13:02:01 -0500 | [diff] [blame] | 212 | struct sde_drm_pix_ext_v1 pe; |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 213 | |
| 214 | /* |
| 215 | * Decimation settings |
| 216 | */ |
| 217 | uint32_t horz_decimate; |
| 218 | uint32_t vert_decimate; |
| 219 | |
| 220 | /* |
| 221 | * Phase settings |
| 222 | */ |
| 223 | int32_t init_phase_x[SDE_MAX_PLANES]; |
| 224 | int32_t phase_step_x[SDE_MAX_PLANES]; |
| 225 | int32_t init_phase_y[SDE_MAX_PLANES]; |
| 226 | int32_t phase_step_y[SDE_MAX_PLANES]; |
| 227 | |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 228 | uint32_t preload_x[SDE_MAX_PLANES]; |
| 229 | uint32_t preload_y[SDE_MAX_PLANES]; |
| 230 | uint32_t src_width[SDE_MAX_PLANES]; |
| 231 | uint32_t src_height[SDE_MAX_PLANES]; |
| 232 | |
| 233 | uint32_t dst_width; |
| 234 | uint32_t dst_height; |
| 235 | |
| 236 | uint32_t y_rgb_filter_cfg; |
| 237 | uint32_t uv_filter_cfg; |
| 238 | uint32_t alpha_filter_cfg; |
| 239 | uint32_t blend_cfg; |
| 240 | |
| 241 | uint32_t lut_flag; |
| 242 | uint32_t dir_lut_idx; |
| 243 | |
| 244 | /* for Y(RGB) and UV planes*/ |
| 245 | uint32_t y_rgb_cir_lut_idx; |
| 246 | uint32_t uv_cir_lut_idx; |
| 247 | uint32_t y_rgb_sep_lut_idx; |
| 248 | uint32_t uv_sep_lut_idx; |
| 249 | |
| 250 | /* |
| 251 | * Detail enhancer settings |
| 252 | */ |
| 253 | struct sde_drm_de_v1 de; |
| 254 | }; |
| 255 | |
| 256 | |
Clarence Ip | 8e8f355 | 2016-05-30 11:42:25 -0400 | [diff] [blame] | 257 | /* |
| 258 | * Define constants for struct sde_drm_csc |
| 259 | */ |
| 260 | #define SDE_CSC_MATRIX_COEFF_SIZE 9 |
| 261 | #define SDE_CSC_CLAMP_SIZE 6 |
| 262 | #define SDE_CSC_BIAS_SIZE 3 |
| 263 | |
Clarence Ip | 8e8f355 | 2016-05-30 11:42:25 -0400 | [diff] [blame] | 264 | /** |
| 265 | * struct sde_drm_csc_v1 - version 1 of struct sde_drm_csc |
| 266 | * @ctm_coeff: Matrix coefficients, in S31.32 format |
| 267 | * @pre_bias: Pre-bias array values |
| 268 | * @post_bias: Post-bias array values |
| 269 | * @pre_clamp: Pre-clamp array values |
| 270 | * @post_clamp: Post-clamp array values |
| 271 | */ |
| 272 | struct sde_drm_csc_v1 { |
| 273 | int64_t ctm_coeff[SDE_CSC_MATRIX_COEFF_SIZE]; |
| 274 | uint32_t pre_bias[SDE_CSC_BIAS_SIZE]; |
| 275 | uint32_t post_bias[SDE_CSC_BIAS_SIZE]; |
| 276 | uint32_t pre_clamp[SDE_CSC_CLAMP_SIZE]; |
| 277 | uint32_t post_clamp[SDE_CSC_CLAMP_SIZE]; |
| 278 | }; |
| 279 | |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 280 | /** |
| 281 | * struct sde_drm_color - struct to store the color and alpha values |
| 282 | * @color_0: Color 0 value |
| 283 | * @color_1: Color 1 value |
| 284 | * @color_2: Color 2 value |
| 285 | * @color_3: Color 3 value |
| 286 | */ |
| 287 | struct sde_drm_color { |
| 288 | uint32_t color_0; |
| 289 | uint32_t color_1; |
| 290 | uint32_t color_2; |
| 291 | uint32_t color_3; |
| 292 | }; |
| 293 | |
| 294 | /* Total number of supported dim layers */ |
| 295 | #define SDE_MAX_DIM_LAYERS 7 |
| 296 | |
| 297 | /* SDE_DRM_DIM_LAYER_CONFIG_FLAG - flags for Dim Layer */ |
| 298 | /* Color fill inside of the rect, including border */ |
| 299 | #define SDE_DRM_DIM_LAYER_INCLUSIVE 0x1 |
| 300 | /* Color fill outside of the rect, excluding border */ |
| 301 | #define SDE_DRM_DIM_LAYER_EXCLUSIVE 0x2 |
| 302 | |
| 303 | /** |
| 304 | * struct sde_drm_dim_layer - dim layer cfg struct |
| 305 | * @flags: Refer SDE_DRM_DIM_LAYER_CONFIG_FLAG for possible values |
| 306 | * @stage: Blending stage of the dim layer |
| 307 | * @color_fill: Color fill for dim layer |
| 308 | * @rect: Dim layer coordinates |
| 309 | */ |
| 310 | struct sde_drm_dim_layer_cfg { |
| 311 | uint32_t flags; |
| 312 | uint32_t stage; |
| 313 | struct sde_drm_color color_fill; |
| 314 | struct drm_clip_rect rect; |
| 315 | }; |
| 316 | |
| 317 | /** |
| 318 | * struct sde_drm_dim_layer_v1 - version 1 of dim layer struct |
| 319 | * @num_layers: Numer of Dim Layers |
| 320 | * @layer: Dim layer user cfgs ptr for the num_layers |
| 321 | */ |
| 322 | struct sde_drm_dim_layer_v1 { |
| 323 | uint32_t num_layers; |
| 324 | struct sde_drm_dim_layer_cfg layer_cfg[SDE_MAX_DIM_LAYERS]; |
| 325 | }; |
| 326 | |
Alan Kwong | bb27c09 | 2016-07-20 16:41:25 -0400 | [diff] [blame] | 327 | /* Writeback Config version definition */ |
| 328 | #define SDE_DRM_WB_CFG 0x1 |
| 329 | |
| 330 | /* SDE_DRM_WB_CONFIG_FLAGS - Writeback configuration flags */ |
| 331 | #define SDE_DRM_WB_CFG_FLAGS_CONNECTED (1<<0) |
| 332 | |
| 333 | /** |
| 334 | * struct sde_drm_wb_cfg - Writeback configuration structure |
| 335 | * @flags: see DRM_MSM_WB_CONFIG_FLAGS |
| 336 | * @connector_id: writeback connector identifier |
| 337 | * @count_modes: Count of modes in modes_ptr |
| 338 | * @modes: Pointer to struct drm_mode_modeinfo |
| 339 | */ |
| 340 | struct sde_drm_wb_cfg { |
| 341 | uint32_t flags; |
| 342 | uint32_t connector_id; |
| 343 | uint32_t count_modes; |
| 344 | uint64_t modes; |
| 345 | }; |
| 346 | |
Clarence Ip | 8e8f355 | 2016-05-30 11:42:25 -0400 | [diff] [blame] | 347 | #endif /* _SDE_DRM_H_ */ |