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gerrit-public.fairphone.software / kernel / msm-4.9 / 58ecb23f64ee3a2ef66bb55b2e1e841385b6d08b / . / arch / arm / boot / dts / tegra20-medcom-wide.dts
blob: 6d3a4cbc36cc358ecdac0313283078e0d1fd4545 [file] [log] [blame]
Thierry Reding731fb452012-09-20 17:06:08 +0200[diff] [blame]1/dts-v1/;
2
Stephen Warren1bd0bd42012-10-17 16:38:21 -0600[diff] [blame]3#include "tegra20-tamonten.dtsi"
Thierry Reding731fb452012-09-20 17:06:08 +0200[diff] [blame]4
5/ {
6 model = "Avionic Design Medcom-Wide board";
7 compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
8
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame^]9 pwm@7000a000 {
Andrew Chewb69cd982013-03-12 16:40:51 -0700[diff] [blame]10 status = "okay";
11 };
12
Thierry Reding731fb452012-09-20 17:06:08 +0200[diff] [blame]13 i2c@7000c000 {
14 wm8903: wm8903@1a {
15 compatible = "wlf,wm8903";
16 reg = <0x1a>;
17 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]18 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
Thierry Reding731fb452012-09-20 17:06:08 +0200[diff] [blame]19
20 gpio-controller;
21 #gpio-cells = <2>;
22
23 micdet-cfg = <0>;
24 micdet-delay = <100>;
25 gpio-cfg = <0xffffffff
26 0xffffffff
27 0
28 0xffffffff
29 0xffffffff>;
30 };
31 };
32
33 backlight {
34 compatible = "pwm-backlight";
35 pwms = <&pwm 0 5000000>;
36
37 brightness-levels = <0 4 8 16 32 64 128 255>;
38 default-brightness-level = <6>;
39 };
40
41 sound {
42 compatible = "ad,tegra-audio-wm8903-medcom-wide",
43 "nvidia,tegra-audio-wm8903";
44 nvidia,model = "Avionic Design Medcom-Wide";
45
46 nvidia,audio-routing =
47 "Headphone Jack", "HPOUTR",
48 "Headphone Jack", "HPOUTL",
49 "Int Spk", "ROP",
50 "Int Spk", "RON",
51 "Int Spk", "LOP",
52 "Int Spk", "LON",
53 "Mic Jack", "MICBIAS",
54 "IN1L", "Mic Jack";
55
56 nvidia,i2s-controller = <&tegra_i2s1>;
57 nvidia,audio-codec = <&wm8903>;
58
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]59 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
60 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]61
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300[diff] [blame]62 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
63 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
64 <&tegra_car TEGRA20_CLK_CDEV1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]65 clock-names = "pll_a", "pll_a_out0", "mclk";
Thierry Reding731fb452012-09-20 17:06:08 +0200[diff] [blame]66 };
67};