blob: bce764099853f24059ff9099b77a2aff9a8636e4 [file] [log] [blame]
Peter De Schrijveradd29e62011-10-12 14:53:05 +03001/dts-v1/;
2
Stephen Warren1bd0bd42012-10-17 16:38:21 -06003#include "tegra20.dtsi"
Peter De Schrijveradd29e62011-10-12 14:53:05 +03004
5/ {
Bryan Wu8fef5df2012-12-20 09:41:29 +00006 model = "NVIDIA Tegra20 Ventana evaluation board";
Peter De Schrijveradd29e62011-10-12 14:53:05 +03007 compatible = "nvidia,ventana", "nvidia,tegra20";
8
Peter De Schrijveradd29e62011-10-12 14:53:05 +03009 memory {
Stephen Warren95decf82012-05-11 16:11:38 -060010 reg = <0x00000000 0x40000000>;
Peter De Schrijveradd29e62011-10-12 14:53:05 +030011 };
12
Stephen Warren58ecb232013-11-25 17:53:16 -070013 host1x@50000000 {
14 hdmi@54280000 {
Stephen Warren97d55202013-01-02 14:53:21 -070015 status = "okay";
16
17 vdd-supply = <&hdmi_vdd_reg>;
18 pll-supply = <&hdmi_pll_reg>;
19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
Stephen Warren3325f1b2013-02-12 17:25:15 -070021 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
22 GPIO_ACTIVE_HIGH>;
Stephen Warren97d55202013-01-02 14:53:21 -070023 };
24 };
25
Stephen Warren58ecb232013-11-25 17:53:16 -070026 pinmux@70000014 {
Stephen Warrenecc295b2012-03-15 16:27:36 -060027 pinctrl-names = "default";
28 pinctrl-0 = <&state_default>;
29
30 state_default: pinmux {
31 ata {
32 nvidia,pins = "ata";
33 nvidia,function = "ide";
34 };
35 atb {
36 nvidia,pins = "atb", "gma", "gme";
37 nvidia,function = "sdio4";
38 };
39 atc {
40 nvidia,pins = "atc";
41 nvidia,function = "nand";
42 };
43 atd {
44 nvidia,pins = "atd", "ate", "gmb", "spia",
45 "spib", "spic";
46 nvidia,function = "gmi";
47 };
48 cdev1 {
49 nvidia,pins = "cdev1";
50 nvidia,function = "plla_out";
51 };
52 cdev2 {
53 nvidia,pins = "cdev2";
54 nvidia,function = "pllp_out4";
55 };
56 crtp {
57 nvidia,pins = "crtp", "lm1";
58 nvidia,function = "crt";
59 };
60 csus {
61 nvidia,pins = "csus";
62 nvidia,function = "vi_sensor_clk";
63 };
64 dap1 {
65 nvidia,pins = "dap1";
66 nvidia,function = "dap1";
67 };
68 dap2 {
69 nvidia,pins = "dap2";
70 nvidia,function = "dap2";
71 };
72 dap3 {
73 nvidia,pins = "dap3";
74 nvidia,function = "dap3";
75 };
76 dap4 {
77 nvidia,pins = "dap4";
78 nvidia,function = "dap4";
79 };
Stephen Warrenecc295b2012-03-15 16:27:36 -060080 dta {
81 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
82 nvidia,function = "vi";
83 };
84 dtf {
85 nvidia,pins = "dtf";
86 nvidia,function = "i2c3";
87 };
88 gmc {
89 nvidia,pins = "gmc";
90 nvidia,function = "uartd";
91 };
92 gmd {
93 nvidia,pins = "gmd";
94 nvidia,function = "sflash";
95 };
96 gpu {
97 nvidia,pins = "gpu";
98 nvidia,function = "pwm";
99 };
100 gpu7 {
101 nvidia,pins = "gpu7";
102 nvidia,function = "rtck";
103 };
104 gpv {
105 nvidia,pins = "gpv", "slxa", "slxk";
106 nvidia,function = "pcie";
107 };
108 hdint {
Mark Zhangcf633462012-10-25 14:52:30 +0800109 nvidia,pins = "hdint";
Stephen Warrenecc295b2012-03-15 16:27:36 -0600110 nvidia,function = "hdmi";
111 };
112 i2cp {
113 nvidia,pins = "i2cp";
114 nvidia,function = "i2cp";
115 };
116 irrx {
117 nvidia,pins = "irrx", "irtx";
118 nvidia,function = "uartb";
119 };
120 kbca {
121 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
122 "kbce", "kbcf";
123 nvidia,function = "kbc";
124 };
125 lcsn {
126 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
127 "lsdi", "lvp0";
128 nvidia,function = "rsvd4";
129 };
130 ld0 {
131 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
132 "ld5", "ld6", "ld7", "ld8", "ld9",
133 "ld10", "ld11", "ld12", "ld13", "ld14",
134 "ld15", "ld16", "ld17", "ldi", "lhp0",
135 "lhp1", "lhp2", "lhs", "lpp", "lpw0",
136 "lpw2", "lsc0", "lsc1", "lsck", "lsda",
137 "lspi", "lvp1", "lvs";
138 nvidia,function = "displaya";
139 };
Mark Zhangcf633462012-10-25 14:52:30 +0800140 owc {
141 nvidia,pins = "owc", "spdi", "spdo", "uac";
142 nvidia,function = "rsvd2";
143 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600144 pmc {
145 nvidia,pins = "pmc";
146 nvidia,function = "pwr_on";
147 };
148 rm {
149 nvidia,pins = "rm";
150 nvidia,function = "i2c1";
151 };
152 sdb {
153 nvidia,pins = "sdb", "sdc", "sdd", "slxc";
154 nvidia,function = "sdio3";
155 };
156 sdio1 {
157 nvidia,pins = "sdio1";
158 nvidia,function = "sdio1";
159 };
160 slxd {
161 nvidia,pins = "slxd";
162 nvidia,function = "spdif";
163 };
164 spid {
165 nvidia,pins = "spid", "spie", "spif";
166 nvidia,function = "spi1";
167 };
168 spig {
169 nvidia,pins = "spig", "spih";
170 nvidia,function = "spi2_alt";
171 };
172 uaa {
173 nvidia,pins = "uaa", "uab", "uda";
174 nvidia,function = "ulpi";
175 };
176 uad {
177 nvidia,pins = "uad";
178 nvidia,function = "irda";
179 };
180 uca {
181 nvidia,pins = "uca", "ucb";
182 nvidia,function = "uartc";
183 };
184 conf_ata {
185 nvidia,pins = "ata", "atb", "atc", "atd",
186 "cdev1", "cdev2", "dap1", "dap2",
187 "dap4", "ddc", "dtf", "gma", "gmc",
188 "gme", "gpu", "gpu7", "i2cp", "irrx",
189 "irtx", "pta", "rm", "sdc", "sdd",
190 "slxc", "slxd", "slxk", "spdi", "spdo",
191 "uac", "uad", "uca", "ucb", "uda";
192 nvidia,pull = <0>;
193 nvidia,tristate = <0>;
194 };
195 conf_ate {
196 nvidia,pins = "ate", "csus", "dap3", "gmd",
197 "gpv", "owc", "spia", "spib", "spic",
198 "spid", "spie", "spig";
199 nvidia,pull = <0>;
200 nvidia,tristate = <1>;
201 };
202 conf_ck32 {
203 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
204 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
205 nvidia,pull = <0>;
206 };
207 conf_crtp {
208 nvidia,pins = "crtp", "gmb", "slxa", "spih";
209 nvidia,pull = <2>;
210 nvidia,tristate = <1>;
211 };
212 conf_dta {
213 nvidia,pins = "dta", "dtb", "dtc", "dtd";
214 nvidia,pull = <1>;
215 nvidia,tristate = <0>;
216 };
217 conf_dte {
218 nvidia,pins = "dte", "spif";
219 nvidia,pull = <1>;
220 nvidia,tristate = <1>;
221 };
222 conf_hdint {
223 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
224 "lpw1", "lsck", "lsda", "lsdi", "lvp0";
225 nvidia,tristate = <1>;
226 };
227 conf_kbca {
228 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
229 "kbce", "kbcf", "sdio1", "uaa", "uab";
230 nvidia,pull = <2>;
231 nvidia,tristate = <0>;
232 };
233 conf_lc {
234 nvidia,pins = "lc", "ls";
235 nvidia,pull = <2>;
236 };
237 conf_ld0 {
238 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
239 "ld5", "ld6", "ld7", "ld8", "ld9",
240 "ld10", "ld11", "ld12", "ld13", "ld14",
241 "ld15", "ld16", "ld17", "ldi", "lhp0",
242 "lhp1", "lhp2", "lhs", "lm0", "lpp",
243 "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
244 "lvp1", "lvs", "pmc", "sdb";
245 nvidia,tristate = <0>;
246 };
247 conf_ld17_0 {
248 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
249 "ld23_22";
250 nvidia,pull = <1>;
251 };
Wei Nic7294292012-09-21 16:54:58 +0800252 drive_sdio1 {
253 nvidia,pins = "drive_sdio1";
254 nvidia,high-speed-mode = <0>;
255 nvidia,schmitt = <1>;
256 nvidia,low-power-mode = <3>;
257 nvidia,pull-down-strength = <31>;
258 nvidia,pull-up-strength = <31>;
259 nvidia,slew-rate-rising = <3>;
260 nvidia,slew-rate-falling = <3>;
261 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600262 };
Mark Zhangcf633462012-10-25 14:52:30 +0800263
264 state_i2cmux_ddc: pinmux_i2cmux_ddc {
265 ddc {
266 nvidia,pins = "ddc";
267 nvidia,function = "i2c2";
268 };
269 pta {
270 nvidia,pins = "pta";
271 nvidia,function = "rsvd4";
272 };
273 };
274
275 state_i2cmux_pta: pinmux_i2cmux_pta {
276 ddc {
277 nvidia,pins = "ddc";
278 nvidia,function = "rsvd4";
279 };
280 pta {
281 nvidia,pins = "pta";
282 nvidia,function = "i2c2";
283 };
284 };
285
286 state_i2cmux_idle: pinmux_i2cmux_idle {
287 ddc {
288 nvidia,pins = "ddc";
289 nvidia,function = "rsvd4";
290 };
291 pta {
292 nvidia,pins = "pta";
293 nvidia,function = "rsvd4";
294 };
295 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600296 };
297
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600298 i2s@70002800 {
299 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600300 };
301
302 serial@70006300 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600303 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600304 };
305
Stephen Warren88950f3b2011-11-21 14:44:09 -0700306 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600307 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700308 clock-frequency = <400000>;
Stephen Warren797acf72012-01-11 16:09:57 -0700309
310 wm8903: wm8903@1a {
311 compatible = "wlf,wm8903";
312 reg = <0x1a>;
313 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700314 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren797acf72012-01-11 16:09:57 -0700315
316 gpio-controller;
317 #gpio-cells = <2>;
318
319 micdet-cfg = <0>;
320 micdet-delay = <100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600321 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
Stephen Warren797acf72012-01-11 16:09:57 -0700322 };
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530323
324 /* ALS and proximity sensor */
325 isl29018@44 {
326 compatible = "isil,isl29018";
327 reg = <0x44>;
328 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700329 interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530330 };
Stephen Warren88950f3b2011-11-21 14:44:09 -0700331 };
332
333 i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600334 status = "okay";
Stephen Warren97d55202013-01-02 14:53:21 -0700335 clock-frequency = <100000>;
Stephen Warren88950f3b2011-11-21 14:44:09 -0700336 };
337
Mark Zhangcf633462012-10-25 14:52:30 +0800338 i2cmux {
339 compatible = "i2c-mux-pinctrl";
340 #address-cells = <1>;
341 #size-cells = <0>;
342
343 i2c-parent = <&{/i2c@7000c400}>;
344
345 pinctrl-names = "ddc", "pta", "idle";
346 pinctrl-0 = <&state_i2cmux_ddc>;
347 pinctrl-1 = <&state_i2cmux_pta>;
348 pinctrl-2 = <&state_i2cmux_idle>;
349
Stephen Warren97d55202013-01-02 14:53:21 -0700350 hdmi_ddc: i2c@0 {
Mark Zhangcf633462012-10-25 14:52:30 +0800351 reg = <0>;
352 #address-cells = <1>;
353 #size-cells = <0>;
354 };
355
356 i2c@1 {
357 reg = <1>;
358 #address-cells = <1>;
359 #size-cells = <0>;
360 };
361 };
362
Stephen Warren88950f3b2011-11-21 14:44:09 -0700363 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600364 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700365 clock-frequency = <400000>;
366 };
367
368 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600369 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700370 clock-frequency = <400000>;
Stephen Warren017a0102012-06-20 16:53:41 -0600371
372 pmic: tps6586x@34 {
373 compatible = "ti,tps6586x";
374 reg = <0x34>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700375 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren017a0102012-06-20 16:53:41 -0600376
Stephen Warren44b12ef2012-09-11 11:42:26 -0600377 ti,system-power-controller;
378
Stephen Warren017a0102012-06-20 16:53:41 -0600379 #gpio-cells = <2>;
380 gpio-controller;
381
382 sys-supply = <&vdd_5v0_reg>;
383 vin-sm0-supply = <&sys_reg>;
384 vin-sm1-supply = <&sys_reg>;
385 vin-sm2-supply = <&sys_reg>;
386 vinldo01-supply = <&sm2_reg>;
387 vinldo23-supply = <&sm2_reg>;
388 vinldo4-supply = <&sm2_reg>;
389 vinldo678-supply = <&sm2_reg>;
390 vinldo9-supply = <&sm2_reg>;
391
392 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600393 sys_reg: sys {
Stephen Warren017a0102012-06-20 16:53:41 -0600394 regulator-name = "vdd_sys";
395 regulator-always-on;
396 };
397
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600398 sm0 {
Stephen Warren017a0102012-06-20 16:53:41 -0600399 regulator-name = "vdd_sm0,vdd_core";
400 regulator-min-microvolt = <1200000>;
401 regulator-max-microvolt = <1200000>;
402 regulator-always-on;
403 };
404
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600405 sm1 {
Stephen Warren017a0102012-06-20 16:53:41 -0600406 regulator-name = "vdd_sm1,vdd_cpu";
407 regulator-min-microvolt = <1000000>;
408 regulator-max-microvolt = <1000000>;
409 regulator-always-on;
410 };
411
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600412 sm2_reg: sm2 {
Stephen Warren017a0102012-06-20 16:53:41 -0600413 regulator-name = "vdd_sm2,vin_ldo*";
414 regulator-min-microvolt = <3700000>;
415 regulator-max-microvolt = <3700000>;
416 regulator-always-on;
417 };
418
419 /* LDO0 is not connected to anything */
420
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600421 ldo1 {
Stephen Warren017a0102012-06-20 16:53:41 -0600422 regulator-name = "vdd_ldo1,avdd_pll*";
423 regulator-min-microvolt = <1100000>;
424 regulator-max-microvolt = <1100000>;
425 regulator-always-on;
426 };
427
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600428 ldo2 {
Stephen Warren017a0102012-06-20 16:53:41 -0600429 regulator-name = "vdd_ldo2,vdd_rtc";
430 regulator-min-microvolt = <1200000>;
431 regulator-max-microvolt = <1200000>;
432 };
433
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600434 ldo3 {
Stephen Warren017a0102012-06-20 16:53:41 -0600435 regulator-name = "vdd_ldo3,avdd_usb*";
436 regulator-min-microvolt = <3300000>;
437 regulator-max-microvolt = <3300000>;
438 regulator-always-on;
439 };
440
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600441 ldo4 {
Stephen Warren017a0102012-06-20 16:53:41 -0600442 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
443 regulator-min-microvolt = <1800000>;
444 regulator-max-microvolt = <1800000>;
445 regulator-always-on;
446 };
447
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600448 ldo5 {
Stephen Warren017a0102012-06-20 16:53:41 -0600449 regulator-name = "vdd_ldo5,vcore_mmc";
450 regulator-min-microvolt = <2850000>;
451 regulator-max-microvolt = <2850000>;
452 regulator-always-on;
453 };
454
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600455 ldo6 {
Stephen Warren017a0102012-06-20 16:53:41 -0600456 regulator-name = "vdd_ldo6,avdd_vdac";
457 regulator-min-microvolt = <1800000>;
458 regulator-max-microvolt = <1800000>;
459 };
460
Stephen Warren97d55202013-01-02 14:53:21 -0700461 hdmi_vdd_reg: ldo7 {
Stephen Warren017a0102012-06-20 16:53:41 -0600462 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
463 regulator-min-microvolt = <3300000>;
464 regulator-max-microvolt = <3300000>;
465 };
466
Stephen Warren97d55202013-01-02 14:53:21 -0700467 hdmi_pll_reg: ldo8 {
Stephen Warren017a0102012-06-20 16:53:41 -0600468 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
469 regulator-min-microvolt = <1800000>;
470 regulator-max-microvolt = <1800000>;
471 };
472
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600473 ldo9 {
Stephen Warren017a0102012-06-20 16:53:41 -0600474 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
475 regulator-min-microvolt = <2850000>;
476 regulator-max-microvolt = <2850000>;
477 regulator-always-on;
478 };
479
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600480 ldo_rtc {
Stephen Warren017a0102012-06-20 16:53:41 -0600481 regulator-name = "vdd_rtc_out,vdd_cell";
482 regulator-min-microvolt = <3300000>;
483 regulator-max-microvolt = <3300000>;
484 regulator-always-on;
485 };
486 };
487 };
Thierry Redingee9f7262012-11-09 23:01:21 +0100488
489 temperature-sensor@4c {
490 compatible = "onnn,nct1008";
491 reg = <0x4c>;
492 };
Stephen Warren017a0102012-06-20 16:53:41 -0600493 };
494
Stephen Warren58ecb232013-11-25 17:53:16 -0700495 pmc@7000e400 {
Stephen Warren017a0102012-06-20 16:53:41 -0600496 nvidia,invert-interrupt;
Joseph Lo47d2d632013-08-12 17:40:07 +0800497 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800498 nvidia,cpu-pwr-good-time = <2000>;
499 nvidia,cpu-pwr-off-time = <100>;
500 nvidia,core-pwr-good-time = <3845 3845>;
501 nvidia,core-pwr-off-time = <458>;
502 nvidia,sys-clock-req-active-high;
Stephen Warren88950f3b2011-11-21 14:44:09 -0700503 };
504
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600505 usb@c5000000 {
506 status = "okay";
507 };
508
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530509 usb-phy@c5000000 {
510 status = "okay";
511 };
512
Stephen Warrenc04abb32012-05-11 17:03:26 -0600513 usb@c5004000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600514 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700515 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
516 GPIO_ACTIVE_LOW>;
Venu Byravarasu9dffe3b2013-05-16 19:42:56 +0530517 };
518
519 usb-phy@c5004000 {
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530520 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700521 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
522 GPIO_ACTIVE_LOW>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600523 };
524
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600525 usb@c5008000 {
526 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600527 };
528
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530529 usb-phy@c5008000 {
530 status = "okay";
531 };
532
Wei Nic7294292012-09-21 16:54:58 +0800533 sdhci@c8000000 {
534 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700535 power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
Wei Nic7294292012-09-21 16:54:58 +0800536 bus-width = <4>;
Joseph Lo7a2617a2013-04-03 14:34:39 -0600537 keep-power-in-suspend;
Wei Nic7294292012-09-21 16:54:58 +0800538 };
539
Stephen Warrenc04abb32012-05-11 17:03:26 -0600540 sdhci@c8000400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600541 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700542 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
543 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
544 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200545 bus-width = <4>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600546 };
547
548 sdhci@c8000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600549 status = "okay";
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200550 bus-width = <8>;
Joseph Lo7a2617a2013-04-03 14:34:39 -0600551 non-removable;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600552 };
553
Joseph Lo7021d122013-04-03 19:31:27 +0800554 clocks {
555 compatible = "simple-bus";
556 #address-cells = <1>;
557 #size-cells = <0>;
558
Stephen Warren58ecb232013-11-25 17:53:16 -0700559 clk32k_in: clock@0 {
Joseph Lo7021d122013-04-03 19:31:27 +0800560 compatible = "fixed-clock";
561 reg=<0>;
562 #clock-cells = <0>;
563 clock-frequency = <32768>;
564 };
565 };
566
Joseph Lo5741a252013-04-03 19:31:48 +0800567 gpio-keys {
568 compatible = "gpio-keys";
569
570 power {
571 label = "Power";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700572 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
Joseph Lo5741a252013-04-03 19:31:48 +0800573 linux,code = <116>; /* KEY_POWER */
574 gpio-key,wakeup;
575 };
576 };
577
Stephen Warren017a0102012-06-20 16:53:41 -0600578 regulators {
579 compatible = "simple-bus";
580 #address-cells = <1>;
581 #size-cells = <0>;
582
583 vdd_5v0_reg: regulator@0 {
584 compatible = "regulator-fixed";
585 reg = <0>;
586 regulator-name = "vdd_5v0";
587 regulator-min-microvolt = <5000000>;
588 regulator-max-microvolt = <5000000>;
589 regulator-always-on;
590 };
591
592 regulator@1 {
593 compatible = "regulator-fixed";
594 reg = <1>;
595 regulator-name = "vdd_1v5";
596 regulator-min-microvolt = <1500000>;
597 regulator-max-microvolt = <1500000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700598 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
Stephen Warren017a0102012-06-20 16:53:41 -0600599 };
600
601 regulator@2 {
602 compatible = "regulator-fixed";
603 reg = <2>;
604 regulator-name = "vdd_1v2";
605 regulator-min-microvolt = <1200000>;
606 regulator-max-microvolt = <1200000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700607 gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
Stephen Warren017a0102012-06-20 16:53:41 -0600608 enable-active-high;
609 };
610
611 regulator@3 {
612 compatible = "regulator-fixed";
613 reg = <3>;
614 regulator-name = "vdd_pnl";
615 regulator-min-microvolt = <2800000>;
616 regulator-max-microvolt = <2800000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700617 gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
Stephen Warren017a0102012-06-20 16:53:41 -0600618 enable-active-high;
619 };
620
621 regulator@4 {
622 compatible = "regulator-fixed";
623 reg = <4>;
624 regulator-name = "vdd_bl";
625 regulator-min-microvolt = <2800000>;
626 regulator-max-microvolt = <2800000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700627 gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
Stephen Warren017a0102012-06-20 16:53:41 -0600628 enable-active-high;
629 };
630 };
631
Stephen Warren797acf72012-01-11 16:09:57 -0700632 sound {
633 compatible = "nvidia,tegra-audio-wm8903-ventana",
634 "nvidia,tegra-audio-wm8903";
635 nvidia,model = "NVIDIA Tegra Ventana";
636
637 nvidia,audio-routing =
638 "Headphone Jack", "HPOUTR",
639 "Headphone Jack", "HPOUTL",
640 "Int Spk", "ROP",
641 "Int Spk", "RON",
642 "Int Spk", "LOP",
643 "Int Spk", "LON",
644 "Mic Jack", "MICBIAS",
645 "IN1L", "Mic Jack";
646
647 nvidia,i2s-controller = <&tegra_i2s1>;
648 nvidia,audio-codec = <&wm8903>;
649
Stephen Warren3325f1b2013-02-12 17:25:15 -0700650 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
651 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
652 nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
653 GPIO_ACTIVE_HIGH>;
654 nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
655 GPIO_ACTIVE_HIGH>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600656
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300657 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
658 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
659 <&tegra_car TEGRA20_CLK_CDEV1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600660 clock-names = "pll_a", "pll_a_out0", "mclk";
Stephen Warren797acf72012-01-11 16:09:57 -0700661 };
Peter De Schrijveradd29e62011-10-12 14:53:05 +0300662};