Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2013-2014, 2016-2018, The Linux Foundation. All rights reserved. |
| 2 | * Copyright (C) 2007 Google Incorporated |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | */ |
| 14 | #ifndef MDP3_H |
| 15 | #define MDP3_H |
| 16 | |
| 17 | #include <linux/types.h> |
| 18 | #include <linux/mutex.h> |
| 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/io.h> |
| 21 | |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 22 | #include "mdss_dsi_clk.h" |
| 23 | #include "mdp3_dma.h" |
| 24 | #include "mdss_fb.h" |
| 25 | #include "mdss.h" |
| 26 | |
| 27 | #define MDP_VSYNC_CLK_RATE 19200000 |
| 28 | #define MDP_CORE_CLK_RATE_SVS 160000000 |
| 29 | #define MDP_CORE_CLK_RATE_SUPER_SVS 200000000 |
| 30 | #define MDP_CORE_CLK_RATE_MAX 307200000 |
| 31 | |
| 32 | #define CLK_FUDGE_NUM 12 |
| 33 | #define CLK_FUDGE_DEN 10 |
| 34 | |
| 35 | /* PPP cant work at SVS for panel res above qHD */ |
| 36 | #define SVS_MAX_PIXEL (540 * 960) |
| 37 | |
| 38 | #define KOFF_TIMEOUT_MS 84 |
| 39 | #define KOFF_TIMEOUT msecs_to_jiffies(KOFF_TIMEOUT_MS) |
| 40 | #define WAIT_DMA_TIMEOUT msecs_to_jiffies(84) |
| 41 | |
| 42 | /* |
| 43 | * MDP_DEINTERLACE & MDP_SHARPENING Flags are not valid for MDP3 |
| 44 | * so using them together for MDP_SMART_BLIT. |
| 45 | */ |
| 46 | #define MDP_SMART_BLIT 0xC0000000 |
| 47 | |
| 48 | #define BITS_PER_BYTE 8 |
| 49 | #define MDP_IMGTYPE_LIMIT1 0x100 |
| 50 | #define BITS_TO_BYTES(x) DIV_ROUND_UP(x, BITS_PER_BYTE) |
| 51 | |
| 52 | enum { |
| 53 | MDP3_CLK_AHB, |
| 54 | MDP3_CLK_AXI, |
| 55 | MDP3_CLK_MDP_SRC, |
| 56 | MDP3_CLK_MDP_CORE, |
| 57 | MDP3_CLK_VSYNC, |
| 58 | MDP3_CLK_DSI, |
| 59 | MDP3_MAX_CLK |
| 60 | }; |
| 61 | |
| 62 | enum { |
| 63 | MDP3_BUS_HANDLE, |
| 64 | MDP3_BUS_HANDLE_MAX, |
| 65 | }; |
| 66 | |
| 67 | enum { |
| 68 | MDP3_IOMMU_DOMAIN_UNSECURE, |
| 69 | MDP3_IOMMU_DOMAIN_SECURE, |
| 70 | MDP3_IOMMU_DOMAIN_MAX, |
| 71 | }; |
| 72 | |
| 73 | enum { |
| 74 | MDP3_IOMMU_CTX_MDP_0, |
| 75 | MDP3_IOMMU_CTX_MDP_1, |
| 76 | MDP3_IOMMU_CTX_MAX |
| 77 | }; |
| 78 | |
| 79 | /* Keep DSI entry in sync with mdss |
| 80 | * which is being used by DSI 6G |
| 81 | */ |
| 82 | enum { |
| 83 | MDP3_CLIENT_DMA_P, |
| 84 | MDP3_CLIENT_DSI = 1, |
| 85 | MDP3_CLIENT_PPP, |
| 86 | MDP3_CLIENT_IOMMU, |
| 87 | MDP3_CLIENT_MAX, |
| 88 | }; |
| 89 | |
| 90 | enum { |
| 91 | DI_PARTITION_NUM = 0, |
| 92 | DI_DOMAIN_NUM = 1, |
| 93 | DI_MAX, |
| 94 | }; |
| 95 | |
| 96 | struct mdp3_bus_handle_map { |
| 97 | struct msm_bus_vectors *bus_vector; |
| 98 | struct msm_bus_paths *usecases; |
| 99 | struct msm_bus_scale_pdata *scale_pdata; |
| 100 | int current_bus_idx; |
| 101 | int ref_cnt; |
| 102 | u64 restore_ab[MDP3_CLIENT_MAX]; |
| 103 | u64 restore_ib[MDP3_CLIENT_MAX]; |
| 104 | u64 ab[MDP3_CLIENT_MAX]; |
| 105 | u64 ib[MDP3_CLIENT_MAX]; |
| 106 | u32 handle; |
| 107 | }; |
| 108 | |
| 109 | struct mdp3_iommu_domain_map { |
| 110 | u32 domain_type; |
| 111 | char *client_name; |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 112 | int npartitions; |
| 113 | int domain_idx; |
| 114 | struct iommu_domain *domain; |
| 115 | }; |
| 116 | |
| 117 | struct mdp3_iommu_ctx_map { |
| 118 | u32 ctx_type; |
| 119 | struct mdp3_iommu_domain_map *domain; |
| 120 | char *ctx_name; |
| 121 | struct device *ctx; |
| 122 | int attached; |
| 123 | }; |
| 124 | |
| 125 | struct mdp3_iommu_meta { |
| 126 | struct rb_node node; |
| 127 | struct ion_handle *handle; |
| 128 | struct rb_root iommu_maps; |
| 129 | struct kref ref; |
| 130 | struct sg_table *table; |
| 131 | struct dma_buf *dbuf; |
| 132 | int mapped_size; |
| 133 | unsigned long size; |
| 134 | dma_addr_t iova_addr; |
| 135 | unsigned long flags; |
| 136 | }; |
| 137 | |
| 138 | #define MDP3_MAX_INTR 28 |
| 139 | |
| 140 | struct mdp3_intr_cb { |
| 141 | void (*cb)(int type, void *); |
| 142 | void *data; |
| 143 | }; |
| 144 | |
| 145 | #define SMART_BLIT_RGB_EN 1 |
| 146 | #define SMART_BLIT_YUV_EN 2 |
| 147 | |
| 148 | struct mdp3_hw_resource { |
| 149 | struct platform_device *pdev; |
| 150 | u32 mdp_rev; |
| 151 | |
| 152 | struct mutex res_mutex; |
| 153 | |
| 154 | struct clk *clocks[MDP3_MAX_CLK]; |
| 155 | int clock_ref_count[MDP3_MAX_CLK]; |
| 156 | unsigned long dma_core_clk_request; |
| 157 | unsigned long ppp_core_clk_request; |
| 158 | struct mdss_hw mdp3_hw; |
| 159 | struct mdss_util_intf *mdss_util; |
| 160 | |
| 161 | char __iomem *mdp_base; |
| 162 | size_t mdp_reg_size; |
| 163 | |
| 164 | char __iomem *vbif_base; |
| 165 | size_t vbif_reg_size; |
| 166 | |
| 167 | struct mdp3_bus_handle_map *bus_handle; |
| 168 | |
| 169 | struct ion_client *ion_client; |
| 170 | struct mdp3_iommu_domain_map *domains; |
| 171 | struct mdp3_iommu_ctx_map *iommu_contexts; |
| 172 | unsigned int iommu_ref_cnt; |
| 173 | bool allow_iommu_update; |
| 174 | struct ion_handle *ion_handle; |
| 175 | struct mutex iommu_lock; |
| 176 | struct mutex fs_idle_pc_lock; |
| 177 | |
| 178 | struct mdp3_dma dma[MDP3_DMA_MAX]; |
| 179 | struct mdp3_intf intf[MDP3_DMA_OUTPUT_SEL_MAX]; |
| 180 | |
| 181 | struct rb_root iommu_root; |
| 182 | spinlock_t irq_lock; |
| 183 | u32 irq_ref_count[MDP3_MAX_INTR]; |
| 184 | u32 irq_mask; |
| 185 | int irq_ref_cnt; |
| 186 | struct mdp3_intr_cb callbacks[MDP3_MAX_INTR]; |
| 187 | u32 underrun_cnt; |
| 188 | |
| 189 | int irq_registered; |
| 190 | |
| 191 | unsigned long splash_mem_addr; |
| 192 | u32 splash_mem_size; |
| 193 | struct mdss_panel_cfg pan_cfg; |
| 194 | |
| 195 | int clk_prepare_count; |
| 196 | int cont_splash_en; |
| 197 | |
| 198 | bool batfet_required; |
| 199 | struct regulator *batfet; |
| 200 | struct regulator *vdd_cx; |
| 201 | struct regulator *fs; |
| 202 | bool fs_ena; |
| 203 | int clk_ena; |
| 204 | bool idle_pc_enabled; |
| 205 | bool idle_pc; |
| 206 | atomic_t active_intf_cnt; |
| 207 | u8 smart_blit_en; |
| 208 | bool solid_fill_vote_en; |
| 209 | struct list_head reg_bus_clist; |
| 210 | struct mutex reg_bus_lock; |
| 211 | |
| 212 | u32 max_bw; |
| 213 | |
| 214 | u8 ppp_formats[BITS_TO_BYTES(MDP_IMGTYPE_LIMIT1)]; |
| 215 | u8 dma_formats[BITS_TO_BYTES(MDP_IMGTYPE_LIMIT1)]; |
| 216 | }; |
| 217 | |
| 218 | struct mdp3_img_data { |
| 219 | dma_addr_t addr; |
| 220 | unsigned long len; |
| 221 | u32 offset; |
| 222 | u32 flags; |
| 223 | u32 padding; |
| 224 | int p_need; |
| 225 | struct ion_handle *srcp_ihdl; |
| 226 | u32 dir; |
| 227 | u32 domain; |
| 228 | bool mapped; |
| 229 | bool skip_detach; |
| 230 | struct fd srcp_f; |
| 231 | struct dma_buf *srcp_dma_buf; |
| 232 | struct dma_buf_attachment *srcp_attachment; |
| 233 | struct sg_table *srcp_table; |
| 234 | struct sg_table *tab_clone; |
| 235 | }; |
| 236 | |
| 237 | extern struct mdp3_hw_resource *mdp3_res; |
| 238 | |
| 239 | struct mdp3_dma *mdp3_get_dma_pipe(int capability); |
| 240 | struct mdp3_intf *mdp3_get_display_intf(int type); |
| 241 | void mdp3_irq_enable(int type); |
| 242 | void mdp3_irq_disable(int type); |
| 243 | void mdp3_irq_disable_nosync(int type); |
| 244 | int mdp3_set_intr_callback(u32 type, struct mdp3_intr_cb *cb); |
| 245 | void mdp3_irq_register(void); |
| 246 | void mdp3_irq_deregister(void); |
| 247 | int mdp3_clk_set_rate(int clk_type, unsigned long clk_rate, int client); |
| 248 | int mdp3_clk_enable(int enable, int dsi_clk); |
| 249 | int mdp3_res_update(int enable, int dsi_clk, int client); |
| 250 | int mdp3_bus_scale_set_quota(int client, u64 ab_quota, u64 ib_quota); |
| 251 | int mdp3_put_img(struct mdp3_img_data *data, int client); |
| 252 | int mdp3_get_img(struct msmfb_data *img, struct mdp3_img_data *data, |
| 253 | int client); |
| 254 | int mdp3_iommu_enable(int client); |
| 255 | int mdp3_iommu_disable(int client); |
| 256 | int mdp3_iommu_is_attached(void); |
| 257 | void mdp3_free(struct msm_fb_data_type *mfd); |
| 258 | int mdp3_parse_dt_splash(struct msm_fb_data_type *mfd); |
| 259 | void mdp3_release_splash_memory(struct msm_fb_data_type *mfd); |
| 260 | int mdp3_create_sysfs_link(struct device *dev); |
| 261 | int mdp3_get_cont_spash_en(void); |
| 262 | int mdp3_get_mdp_dsi_clk(void); |
| 263 | int mdp3_put_mdp_dsi_clk(void); |
| 264 | |
| 265 | int mdp3_misr_set(struct mdp_misr *misr_req); |
| 266 | int mdp3_misr_get(struct mdp_misr *misr_resp); |
| 267 | void mdp3_enable_regulator(int enable); |
| 268 | void mdp3_check_dsi_ctrl_status(struct work_struct *work, |
| 269 | uint32_t interval); |
| 270 | int mdp3_dynamic_clock_gating_ctrl(int enable); |
| 271 | int mdp3_footswitch_ctrl(int enable); |
| 272 | int mdp3_qos_remapper_setup(struct mdss_panel_data *panel); |
| 273 | int mdp3_splash_done(struct mdss_panel_info *panel_info); |
| 274 | int mdp3_autorefresh_disable(struct mdss_panel_info *panel_info); |
| 275 | u64 mdp3_clk_round_off(u64 clk_rate); |
| 276 | |
| 277 | void mdp3_calc_dma_res(struct mdss_panel_info *panel_info, u64 *clk_rate, |
| 278 | u64 *ab, u64 *ib, uint32_t bpp); |
| 279 | void mdp3_clear_irq(u32 interrupt_mask); |
| 280 | int mdp3_enable_panic_ctrl(void); |
| 281 | |
| 282 | int mdp3_layer_pre_commit(struct msm_fb_data_type *mfd, |
| 283 | struct file *file, struct mdp_layer_commit_v1 *commit); |
| 284 | int mdp3_layer_atomic_validate(struct msm_fb_data_type *mfd, |
| 285 | struct file *file, struct mdp_layer_commit_v1 *commit); |
| 286 | |
| 287 | #define MDP3_REG_WRITE(addr, val) writel_relaxed(val, mdp3_res->mdp_base + addr) |
| 288 | #define MDP3_REG_READ(addr) readl_relaxed(mdp3_res->mdp_base + addr) |
| 289 | #define VBIF_REG_WRITE(off, val) writel_relaxed(val, mdp3_res->vbif_base + off) |
| 290 | #define VBIF_REG_READ(off) readl_relaxed(mdp3_res->vbif_base + off) |
| 291 | |
| 292 | #endif /* MDP3_H */ |